bcm2835reg.h revision 1.33
1 /* $NetBSD: bcm2835reg.h,v 1.33 2024/10/06 20:55:12 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Nick Hudson 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Reference: BCM2835 ARM Peripherals 34 * 35 * http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf 36 */ 37 38 #ifndef _BCM2835REG_H_ 39 #define _BCM2835REG_H_ 40 41 #include "opt_bcm283x.h" 42 43 #if defined(SOC_BCM2835) + defined(SOC_BCM2836) != 1 44 #error Must define SOC_BCM2835 or SOC_BCM2836, and not both 45 #endif 46 47 #define BCM2711_PERIPHERALS_BASE 0xfe000000 48 #define BCM2836_PERIPHERALS_BASE 0x3f000000 49 #define BCM2835_PERIPHERALS_BASE 0x20000000 50 #define BCM283X_PERIPHERALS_SIZE 0x01000000 /* 16MBytes */ 51 #define BCM283X_PERIPHERALS_BASE_BUS 0x7e000000 52 53 #define BCM2711_PERIPHERALS_PHYS_TO_BUS(a) \ 54 ((a) - BCM2711_PERIPHERALS_BASE + BCM283X_PERIPHERALS_BASE_BUS) 55 #define BCM2711_PERIPHERALS_BUS_TO_PHYS(a) \ 56 ((a) - BCM283X_PERIPHERALS_BASE_BUS + BCM2711_PERIPHERALS_BASE) 57 58 #define BCM2836_PERIPHERALS_PHYS_TO_BUS(a) \ 59 ((a) - BCM2836_PERIPHERALS_BASE + BCM283X_PERIPHERALS_BASE_BUS) 60 #define BCM2836_PERIPHERALS_BUS_TO_PHYS(a) \ 61 ((a) - BCM283X_PERIPHERALS_BASE_BUS + BCM2836_PERIPHERALS_BASE) 62 63 #define BCM2835_PERIPHERALS_PHYS_TO_BUS(a) \ 64 ((a) - BCM2835_PERIPHERALS_BASE + BCM283X_PERIPHERALS_BASE_BUS) 65 #define BCM2835_PERIPHERALS_BUS_TO_PHYS(a) \ 66 ((a) - BCM283X_PERIPHERALS_BASE_BUS + BCM2835_PERIPHERALS_BASE) 67 68 #define BCM2835_STIMER_BASE (BCM283X_PERIPHERALS_BASE_BUS + 0x00003000) 69 #define BCM2835_DMA0_BASE (BCM283X_PERIPHERALS_BASE_BUS + 0x00007000) 70 #define BCM2835_ARM_BASE (BCM283X_PERIPHERALS_BASE_BUS + 0x0000B000) 71 #define BCM2835_PM_BASE (BCM283X_PERIPHERALS_BASE_BUS + 0x00100000) 72 #define BCM2835_CM_BASE (BCM283X_PERIPHERALS_BASE_BUS + 0x00101000) 73 #define BCM2835_RNG_BASE (BCM283X_PERIPHERALS_BASE_BUS + 0x00104000) 74 #define BCM2835_GPIO_BASE (BCM283X_PERIPHERALS_BASE_BUS + 0x00200000) 75 #define BCM2835_UART0_BASE (BCM283X_PERIPHERALS_BASE_BUS + 0x00201000) 76 #define BCM2835_SDHOST_BASE (BCM283X_PERIPHERALS_BASE_BUS + 0x00202000) 77 #define BCM2835_PCM_BASE (BCM283X_PERIPHERALS_BASE_BUS + 0x00203000) 78 #define BCM2835_SPI0_BASE (BCM283X_PERIPHERALS_BASE_BUS + 0x00204000) 79 #define BCM2835_BSC0_BASE (BCM283X_PERIPHERALS_BASE_BUS + 0x00205000) 80 #define BCM2835_PWM_BASE (BCM283X_PERIPHERALS_BASE_BUS + 0x0020C000) 81 #define BCM2835_BSCSPISLV_BASE (BCM283X_PERIPHERALS_BASE_BUS + 0x00214000) 82 #define BCM2835_AUX_BASE (BCM283X_PERIPHERALS_BASE_BUS + 0x00215000) 83 #define BCM2835_AUX_UART_BASE (BCM283X_PERIPHERALS_BASE_BUS + 0x00215040) 84 #define BCM2835_EMMC_BASE (BCM283X_PERIPHERALS_BASE_BUS + 0x00300000) 85 #define BCM2835_BSC1_BASE (BCM283X_PERIPHERALS_BASE_BUS + 0x00804000) 86 #define BCM2835_BSC2_BASE (BCM283X_PERIPHERALS_BASE_BUS + 0x00805000) 87 #define BCM2835_USB_BASE (BCM283X_PERIPHERALS_BASE_BUS + 0x00980000) 88 #define BCM2835_DMA15_BASE (BCM283X_PERIPHERALS_BASE_BUS + 0x00E05000) 89 90 #define BCM2835_STIMER_SIZE 0x1c 91 #define BCM2835_DMA0_SIZE 0x1000 92 #define BCM2835_ARM_SIZE 0x1000 93 #define BCM2835_PM_SIZE 0x1000 94 #define BCM2835_CM_SIZE 0xa8 95 #define BCM2835_RNG_SIZE 0x1000 96 #define BCM2835_GPIO_SIZE 0x1000 97 #define BCM2835_UART0_SIZE 0x90 98 #define BCM2835_PCM_SIZE 0x1000 99 #define BCM2835_SPI0_SIZE 0x1000 100 #define BCM2835_BSC_SIZE 0x1000 101 #define BCM2835_PWM_SIZE 0x28 102 #define BCM2835_AUX_SIZE 0x8 103 #define BCM2835_AUX_UART_SIZE 0x40 104 #define BCM2835_SDHOST_SIZE 0x1000 105 #define BCM2835_EMMC_SIZE 0x1000 106 #define BCM2835_USB_SIZE 0x20000 107 #define BCM2835_DMA15_SIZE 0x100 108 109 110 #define BCM2835_BUSADDR_CACHE_MASK 0xc0000000 111 #define BCM2835_BUSADDR_CACHE_COHERENT 0x40000000 112 #define BCM2835_BUSADDR_CACHE_L1L2 0x00000000 113 #define BCM2835_BUSADDR_CACHE_L2ONLY 0x80000000 114 #define BCM2835_BUSADDR_CACHE_DIRECT 0xc0000000 115 116 #define BCM2835_ARMICU_BASE (BCM2835_ARM_BASE + 0x0200) 117 #define BCM2835_ARMICU_SIZE 0x200 118 119 #define BCM2835_VCHIQ_BASE (BCM2835_ARM_BASE + 0x0800) 120 #define BCM2835_VCHIQ_SIZE 0x50 121 122 #define BCM2835_ARMMBOX_BASE (BCM2835_ARM_BASE + 0x0880) 123 #define BCM2835_ARMMBOX_SIZE 0x40 124 125 #define BCM2835_INTC_BASE (0x0) /* Relative to BCM2835_ARMICU_BASE */ 126 127 #define BCM2711_SCB_BASE 0xfc000000 128 #define BCM2711_SCB_SIZE 0x03800000 129 #define BCM2711_SCB_BASE_BUS 0x7c000000 130 131 #define BCM2711_SCB_PHYS_TO_BUS(a) \ 132 ((a) - BCM2711_SCB_BASE + BCM2711_SCB_BASE_BUS) 133 #define BCM2711_SCB_BUS_TO_PHYS(a) \ 134 ((a) - BCM2711_SCB_BASE_BUS + BCM2711_SCB_BASE) 135 136 /* Interrupt controller */ 137 #define BCM2835_INTC_IRQBPENDING (BCM2835_INTC_BASE + 0x00) /* IRQ Basic pending */ 138 #define BCM2835_INTC_IRQ1PENDING (BCM2835_INTC_BASE + 0x04) /* IRQ pending 1 */ 139 #define BCM2835_INTC_IRQ2PENDING (BCM2835_INTC_BASE + 0x08) /* IRQ pending 2 */ 140 #define BCM2835_INTC_FIQCTL (BCM2835_INTC_BASE + 0x0c) /* FIQ control */ 141 #define BCM2835_INTC_IRQ1ENABLE (BCM2835_INTC_BASE + 0x10) /* Enable IRQs 1 */ 142 #define BCM2835_INTC_IRQ2ENABLE (BCM2835_INTC_BASE + 0x14) /* Enable IRQs 2 */ 143 #define BCM2835_INTC_IRQBENABLE (BCM2835_INTC_BASE + 0x18) /* Enable Basic IRQs */ 144 #define BCM2835_INTC_IRQ1DISABLE (BCM2835_INTC_BASE + 0x1c) /* Disable IRQ 1 */ 145 #define BCM2835_INTC_IRQ2DISABLE (BCM2835_INTC_BASE + 0x20) /* Disable IRQ 2 */ 146 #define BCM2835_INTC_IRQBDISABLE (BCM2835_INTC_BASE + 0x24) /* Disable Basic IRQs */ 147 148 #define BCM2835_INTC_ENABLEBASE (BCM2835_INTC_BASE + 0x10) 149 #define BCM2835_INTC_DISABLEBASE (BCM2835_INTC_BASE + 0x1c) 150 151 #define BCM2836_NCPUS 4 152 #define BCM2836_NIRQPERCPU 32 153 154 #define BCM2836_INT_CNTPSIRQ 0 155 #define BCM2836_INT_CNTPNSIRQ 1 156 #define BCM2836_INT_CNTHPIRQ 2 157 #define BCM2836_INT_CNTVIRQ 3 158 #define BCM2836_INT_MAILBOX0 4 159 #define BCM2836_INT_MAILBOX1 5 160 #define BCM2836_INT_MAILBOX2 6 161 #define BCM2836_INT_MAILBOX3 7 162 #define BCM2836_INT_GPU_FAST 8 163 #define BCM2836_INT_PMU_FAST 9 164 #define BCM2836_INT_ZERO 10 165 #define BCM2836_INT_TIMER 11 166 #define BCM2836_INT_NLOCAL 12 167 168 #define BCM2835_UART0_CLK 3000000 169 170 #define BCM2711_ARM_LOCAL_BASE_BUS 0x40000000 171 #define BCM2711_ARM_LOCAL_BASE 0xff800000 172 #define BCM2711_ARM_LOCAL_SIZE 0x00100000 /* 1MBytes */ 173 174 #define BCM2711_ARM_LOCAL_PHYS_TO_BUS(a) \ 175 ((a) - BCM2711_ARM_LOCAL_BASE + BCM2711_ARM_LOCAL_BASE_BUS) 176 #define BCM2711_ARM_LOCAL_BUS_TO_PHYS(a) \ 177 ((a) - BCM2711_ARM_LOCAL_BASE_BUS + BCM2711_ARM_LOCAL_BASE) 178 179 #define BCM2836_ARM_LOCAL_BASE 0x40000000 180 #define BCM2836_ARM_LOCAL_SIZE 0x00001000 /* 4KBytes */ 181 182 #define BCM2836_LOCAL_CONTROL 0x000 /* ARM_CONTROL */ 183 #define BCM2836_LOCAL_PRESCALER 0x008 184 #define BCM2836_LOCAL_GPU_INT_ROUTING 0x00c /* CORE_IRQ_CONTROL */ 185 #define BCM2836_LOCAL_PM_ROUTING_SET 0x010 /* PMU_CONTROL_SET */ 186 #define BCM2836_LOCAL_PM_ROUTING_CLR 0x014 /* PMU_CONTROL_CLR */ 187 #define BCM2836_LOCAL_TIMER_LS 0x01c 188 #define BCM2836_LOCAL_TIMER_MS 0x020 189 #define BCM2836_LOCAL_INT_ROUTING 0x024 /* PERI_IRQ_ROUTE0 */ 190 #define BCM2836_LOCAL_AXI_COUNT 0x02c 191 #define BCM2836_LOCAL_AXI_IRQ 0x030 /* AXI_QUIET_TIME */ 192 #define BCM2836_LOCAL_TIMER_CONTROL 0x034 193 #define BCM2836_LOCAL_TIMER_WRITE 0x038 /* LOCAL_TIMER_IRQ */ 194 195 196 #define BCM2836_LOCAL_TIMER_IRQ_CONTROL_BASE 0x40 197 #define BCM2836_LOCAL_MAILBOX_IRQ_CONTROL_BASE 0x50 198 #define BCM2836_LOCAL_INTC_IRQPENDING_BASE 0x60 199 #define BCM2836_LOCAL_INTC_FIQPENDING_BASE 0x70 200 201 #define BCM2836_LOCAL_TIMER_IRQ_CONTROL_SIZE 0x10 202 #define BCM2836_LOCAL_MAILBOX_IRQ_CONTROL_SIZE 0x10 203 204 #define BCM2836_LOCAL_TIMER_IRQ_CONTROLN(n) (BCM2836_LOCAL_TIMER_IRQ_CONTROL_BASE + 4*(n)) 205 #define BCM2836_LOCAL_MAILBOX_IRQ_CONTROLN(n) (BCM2836_LOCAL_MAILBOX_IRQ_CONTROL_BASE + 4*(n)) 206 #define BCM2836_LOCAL_INTC_IRQPENDINGN(n) (BCM2836_LOCAL_INTC_IRQPENDING_BASE + 4*(n)) 207 #define BCM2836_LOCAL_INTC_FIQPENDINGN(n) (BCM2836_LOCAL_INTC_FIQPENDING_BASE + 4*(n)) 208 209 #define BCM2836_LOCAL_MAILBOX0_SETN(n) (0x80 + 0x10 * (n)) 210 #define BCM2836_LOCAL_MAILBOX1_SETN(n) (0x84 + 0x10 * (n)) 211 #define BCM2836_LOCAL_MAILBOX2_SETN(n) (0x88 + 0x10 * (n)) 212 #define BCM2836_LOCAL_MAILBOX3_SETN(n) (0x8c + 0x10 * (n)) 213 #define BCM2836_LOCAL_MAILBOX0_CLRN(n) (0xc0 + 0x10 * (n)) 214 #define BCM2836_LOCAL_MAILBOX1_CLRN(n) (0xc4 + 0x10 * (n)) 215 #define BCM2836_LOCAL_MAILBOX2_CLRN(n) (0xc8 + 0x10 * (n)) 216 #define BCM2836_LOCAL_MAILBOX3_CLRN(n) (0xcc + 0x10 * (n)) 217 218 #define BCM2836_ARM_SMP_BASE 0x00000000 219 #define BCM2836_ARM_SMP_SIZE 0x00001000 /* 4KBytes */ 220 221 #endif /* _BCM2835REG_H_ */ 222
Indexes created Wed Oct 01 19:09:53 GMT 2025