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bcm2835reg.h revision 1.7 
      1 /*	$NetBSD: bcm2835reg.h,v 1.7 2013/01/08 21:58:40 skrll Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2012 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Nick Hudson
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 /*
     33  * Reference: BCM2835 ARM Periperhals
     34  *
     35  * 	http://dmkenr5gtnd8f.cloudfront.net/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
     36  */
     37 
     38 #ifndef	_BCM2835REG_H_
     39 #define	_BCM2835REG_H_
     40 
     41 #define	BCM2835_PERIPHERALS_BASE	0x20000000
     42 #define	BCM2835_PERIPHERALS_SIZE	0x01000000	/* 16MBytes */
     43 
     44 #define	BCM2835_STIMER_BASE	(BCM2835_PERIPHERALS_BASE + 0x00003000)
     45 #define	BCM2835_DMA0_BASE	(BCM2835_PERIPHERALS_BASE + 0x00007000)
     46 #define	BCM2835_ARM_BASE	(BCM2835_PERIPHERALS_BASE + 0x0000B000)
     47 #define	BCM2835_PM_BASE		(BCM2835_PERIPHERALS_BASE + 0x00100000)
     48 #define	BCM2835_GPIO_BASE	(BCM2835_PERIPHERALS_BASE + 0x00200000)
     49 #define	BCM2835_UART0_BASE	(BCM2835_PERIPHERALS_BASE + 0x00201000)
     50 #define	BCM2835_PCM_BASE	(BCM2835_PERIPHERALS_BASE + 0x00203000)
     51 #define	BCM2835_SPI0_BASE	(BCM2835_PERIPHERALS_BASE + 0x00204000)
     52 #define	BCM2835_BSC0_BASE	(BCM2835_PERIPHERALS_BASE + 0x00205000)
     53 #define	BCM2835_BSCSPISLV_BASE	(BCM2835_PERIPHERALS_BASE + 0x00214000)
     54 #define	BCM2835_AUX_BASE	(BCM2835_PERIPHERALS_BASE + 0x00215000)
     55 #define	BCM2835_EMMC_BASE	(BCM2835_PERIPHERALS_BASE + 0x00300000)
     56 #define	BCM2835_BSC1_BASE	(BCM2835_PERIPHERALS_BASE + 0x00804000)
     57 #define	BCM2835_BSC2_BASE	(BCM2835_PERIPHERALS_BASE + 0x00805000)
     58 #define	BCM2835_USB_BASE	(BCM2835_PERIPHERALS_BASE + 0x00980000)
     59 #define	BCM2835_DMA15_BASE	(BCM2835_PERIPHERALS_BASE + 0x00E05000)
     60 
     61 #define	BCM2835_STIMER_SIZE	0x1c
     62 #define	BCM2835_DMA0_SIZE	0x1000
     63 #define	BCM2835_ARM_SIZE	0x1000
     64 #define	BCM2835_PM_SIZE		0x1000
     65 #define	BCM2835_GPIO_SIZE	0x1000
     66 #define	BCM2835_UART0_SIZE	0x90
     67 #define	BCM2835_PCM_SIZE	0x1000
     68 #define	BCM2835_SPI0_SIZE	0x1000
     69 #define	BCM2835_BSC_SIZE	0x1000
     70 #define	BCM2835_AUX_SIZE	0x1000
     71 #define	BCM2835_EMMC_SIZE	0x1000
     72 #define	BCM2835_USB_SIZE	0x20000
     73 #define	BCM2835_DMA15_SIZE	0x100
     74 
     75 #define BCM2835_IOPHYSTOVIRT(a) \
     76     ((0xf0000000 | (((a) & 0xf0000000) >> 4)) + ((a) & ~0xf0000000))
     77 
     78 #define	BCM2835_PERIPHERALS_VBASE \
     79 	BCM2835_IOPHYSTOVIRT(BCM2835_PERIPHERALS_BASE)
     80 #define	BCM2835_STIMER_VBASE	BCM2835_IOPHYSTOVIRT(BCM2835_ST_BASE)
     81 #define	BCM2835_PM_VBASE	BCM2835_IOPHYSTOVIRT(BCM2835_PM_BASE)
     82 #define	BCM2835_UART0_VBASE	BCM2835_IOPHYSTOVIRT(BCM2835_UART0_BASE)
     83 #define	BCM2835_EMMC_VBASE	BCM2835_IOPHYSTOVIRT(BCM2835_EMMC_BASE)
     84 
     85 #define	BCM2835_ARMICU_BASE	(BCM2835_ARM_BASE + 0x0200)
     86 #define	BCM2835_ARMICU_SIZE	0x200
     87 
     88 #define	BCM2835_ARMMBOX_BASE	(BCM2835_ARM_BASE + 0x0880)
     89 #define	BCM2835_ARMMBOX_SIZE	0x40
     90 
     91 #define	BCM2835_ARMICU_VBASE	BCM2835_IOPHYSTOVIRT(BCM2835_ARMICU_BASE)
     92 
     93 #define	BCM2835_INTC_BASE	(0x0)	/* Relative to BCM2835_ARMICU_BASE */
     94 
     95 /* Interrupt controller */
     96 #define	BCM2835_INTC_IRQBPENDING	(BCM2835_INTC_BASE + 0x00)	/* IRQ Basic pending */
     97 #define	BCM2835_INTC_IRQ1PENDING	(BCM2835_INTC_BASE + 0x04)	/* IRQ pending 1 */
     98 #define	BCM2835_INTC_IRQ2PENDING	(BCM2835_INTC_BASE + 0x08)	/* IRQ pending 2 */
     99 #define	BCM2835_INTC_FIQCTL		(BCM2835_INTC_BASE + 0x0c)	/* FIQ control */
    100 #define	BCM2835_INTC_IRQ1ENABLE		(BCM2835_INTC_BASE + 0x10)	/* Enable IRQs 1 */
    101 #define	BCM2835_INTC_IRQ2ENABLE		(BCM2835_INTC_BASE + 0x14)	/* Enable IRQs 2 */
    102 #define	BCM2835_INTC_IRQBENABLE		(BCM2835_INTC_BASE + 0x18)	/* Enable Basic IRQs */
    103 #define	BCM2835_INTC_IRQ1DISABLE	(BCM2835_INTC_BASE + 0x1c)	/* Disable IRQ 1 */
    104 #define	BCM2835_INTC_IRQ2DISABLE	(BCM2835_INTC_BASE + 0x20)	/* Disable IRQ 2 */
    105 #define	BCM2835_INTC_IRQBDISABLE	(BCM2835_INTC_BASE + 0x24)	/* Disable Basic IRQs */
    106 
    107 #define	BCM2835_INTC_ENABLEBASE		(BCM2835_INTC_BASE + 0x10)
    108 #define	BCM2835_INTC_DISABLEBASE	(BCM2835_INTC_BASE + 0x1c)
    109 
    110 /* Interrupt source */
    111 #define	BCM2835_INT_GPU0BASE		0
    112 #define	BCM2835_INT_TIMER0		(BCM2835_INT_GPU0BASE + 0)
    113 #define	BCM2835_INT_TIMER1		(BCM2835_INT_GPU0BASE + 1)
    114 #define	BCM2835_INT_TIMER2		(BCM2835_INT_GPU0BASE + 2)
    115 #define	BCM2835_INT_TIMER3		(BCM2835_INT_GPU0BASE + 3)
    116 #define	BCM2835_INT_USB			(BCM2835_INT_GPU0BASE + 9)
    117 #define	BCM2835_INT_DMA2		(BCM2835_INT_GPU0BASE + 18)
    118 #define	BCM2835_INT_DMA3		(BCM2835_INT_GPU0BASE + 19)
    119 #define	BCM2835_INT_AUX			(BCM2835_INT_GPU0BASE + 29)
    120 #define	BCM2835_INT_ARM			(BCM2835_INT_GPU0BASE + 30)
    121 
    122 #define	BCM2835_INT_GPU1BASE		32
    123 #define	BCM2835_INT_GPIO0		(BCM2835_INT_GPU1BASE + 17)
    124 #define	BCM2835_INT_GPIO1		(BCM2835_INT_GPU1BASE + 18)
    125 #define	BCM2835_INT_GPIO2		(BCM2835_INT_GPU1BASE + 19)
    126 #define	BCM2835_INT_GPIO3		(BCM2835_INT_GPU1BASE + 20)
    127 #define	BCM2835_INT_BSC			(BCM2835_INT_GPU1BASE + 21)
    128 #define	BCM2835_INT_SPI0		(BCM2835_INT_GPU1BASE + 22)
    129 #define	BCM2835_INT_PCM			(BCM2835_INT_GPU1BASE + 23)
    130 #define	BCM2835_INT_UART0		(BCM2835_INT_GPU1BASE + 25)
    131 #define	BCM2835_INT_EMMC		(BCM2835_INT_GPU1BASE + 30)
    132 
    133 #define	BCM2835_INT_BASICBASE		64
    134 #define	BCM2835_INT_ARMTIMER		(BCM2835_INT_BASICBASE + 0)
    135 #define	BCM2835_INT_ARMMAILBOX		(BCM2835_INT_BASICBASE + 1)
    136 #define	BCM2835_INT_ARMDOORBELL0	(BCM2835_INT_BASICBASE + 2)
    137 #define	BCM2835_INT_ARMDOORBELL1	(BCM2835_INT_BASICBASE + 3)
    138 #define	BCM2835_INT_GPU0HALTED		(BCM2835_INT_BASICBASE + 4)
    139 #define	BCM2835_INT_GPU1HALTED		(BCM2835_INT_BASICBASE + 5)
    140 #define	BCM2835_INT_ILLEGALTYPE0	(BCM2835_INT_BASICBASE + 6)
    141 #define	BCM2835_INT_ILLEGALTYPE1	(BCM2835_INT_BASICBASE + 7)
    142 
    143 #define	BCM2835_NIRQ	64 + 8
    144 
    145 #define	BCM2835_UART0_CLK	3000000
    146 
    147 #endif /* _BCM2835REG_H_ */
    148