bcm2838_pcie.c revision 1.1
1 /* $NetBSD: bcm2838_pcie.c,v 1.1 2021/03/08 13:49:01 mlelstv Exp $ */ 2 3 /*- 4 * Copyright (c) 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Michael van Elst 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: bcm2838_pcie.c,v 1.1 2021/03/08 13:49:01 mlelstv Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/device.h> 37 38 #include <dev/pci/pcireg.h> 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pciconf.h> 41 42 #include <dev/fdt/fdtvar.h> 43 44 #include <arch/arm/pci/pci_msi_machdep.h> 45 #include <arch/arm/broadcom/bcm2838_pcie.h> 46 47 #include <arch/evbarm/rpi/vcprop.h> 48 #include <dev/pci/pcidevs.h> 49 50 #define PHYS_HI_RELO __BIT(31) 51 #define PHYS_HI_PREFETCH __BIT(30) 52 #define PHYS_HI_ALIASED __BIT(29) 53 #define PHYS_HI_SPACE __BITS(25,24) 54 #define PHYS_HI_SPACE_CFG 0 55 #define PHYS_HI_SPACE_IO 1 56 #define PHYS_HI_SPACE_MEM32 2 57 #define PHYS_HI_SPACE_MEM64 3 58 59 #define CFG_OFFSET(b,d,f,r) ((b) << 16 | (d) << 1 | (f) << 8 | (r)) 60 61 struct bcmstb_busspace { 62 struct bus_space bst; 63 int (*map)(void *, bus_addr_t, bus_size_t, 64 int, bus_space_handle_t *); 65 int flags; 66 struct { 67 bus_addr_t bpci; 68 bus_addr_t bbus; 69 bus_size_t size; 70 } ranges[4]; 71 size_t nranges; 72 }; 73 74 struct bcmstb_softc { 75 bus_space_tag_t sc_bst; 76 bus_space_handle_t sc_bsh; 77 bus_dma_tag_t sc_dmat; 78 79 kmutex_t sc_lock; 80 const char *sc_name; 81 82 int sc_phandle; 83 84 uint32_t sc_bus_min; 85 uint32_t sc_bus_max; 86 87 struct arm32_pci_chipset sc_pc; 88 89 struct bcmstb_busspace sc_io; 90 struct bcmstb_busspace sc_mem; 91 92 int sc_pci_flags; 93 }; 94 95 static void bcmstb_attach(device_t, struct bcmstb_softc *); 96 static int bcmstb_config(struct bcmstb_softc *); 97 static int bcmstb_setup(struct bcmstb_softc *); 98 static void bcmstb_attach_hook(device_t, device_t, struct pcibus_attach_args *); 99 static int bcmstb_bus_maxdevs(void *, int); 100 static pcitag_t bcmstb_make_tag(void *, int, int, int); 101 static void bcmstb_decompose_tag(void *, pcitag_t, int *, int *, int *); 102 static u_int bcmstb_get_segment(void *); 103 static pcireg_t bcmstb_conf_read(void *, pcitag_t, int); 104 static void bcmstb_conf_write(void *, pcitag_t, int, pcireg_t); 105 static int bcmstb_conf_hook(void *, int, int, int, pcireg_t); 106 static void bcmstb_conf_interrupt(void *, int, int, int, int, int *); 107 108 static int bcmstb_intr_map(const struct pci_attach_args *, pci_intr_handle_t *); 109 static const char *bcmstb_intr_string(void *, pci_intr_handle_t, char *, size_t); 110 static const struct evcnt *bcmstb_intr_evcnt(void *, pci_intr_handle_t); 111 static int bcmstb_intr_setattr(void *, pci_intr_handle_t *, int, uint64_t); 112 static void *bcmstb_intr_establish(void *, pci_intr_handle_t, int, 113 int (*)(void *), void *, const char *); 114 static void bcmstb_intr_disestablish(void *, void *); 115 static int bcmstb_bus_space_map(void *, bus_addr_t, 116 bus_size_t, int, bus_space_handle_t *); 117 118 struct bcm2838pcie_softc { 119 device_t sc_dev; 120 struct bcmstb_softc sc_bcmstb; 121 }; 122 123 static int bcm2838pcie_match(device_t, cfdata_t, void *); 124 static void bcm2838pcie_attach(device_t, device_t, void *); 125 126 CFATTACH_DECL_NEW(bcm2838pcie_fdt, sizeof(struct bcm2838pcie_softc), 127 bcm2838pcie_match, bcm2838pcie_attach, NULL, NULL); 128 129 130 static inline void 131 stb_write(struct bcmstb_softc *sc, int r, uint32_t v) 132 { 133 bus_space_write_4(sc->sc_bst, sc->sc_bsh, r, v); 134 } 135 static inline uint32_t 136 stb_read(struct bcmstb_softc *sc, int r) 137 { 138 uint32_t v; 139 140 v = bus_space_read_4(sc->sc_bst, sc->sc_bsh, r); 141 142 return v; 143 } 144 static inline void 145 stb_setbits(struct bcmstb_softc *sc, int r, uint32_t clr, uint32_t set) 146 { 147 uint32_t w; 148 149 w = stb_read(sc, r); 150 w = (w & ~clr) | set; 151 stb_write(sc, r, w); 152 } 153 #define STBWRITE(sc, r, v) stb_write((sc), (r), (v)) 154 #define STBREAD(sc, r) stb_read((sc), (r)) 155 #define STBRMW(sc, r, c, s) stb_setbits((sc), (r), (c), (s)) 156 157 static const struct device_compatible_entry compat_data[] = { 158 { .compat = "brcm,pci-plat-dev" }, 159 DEVICE_COMPAT_EOL 160 }; 161 162 /* ARGSUSED */ 163 static int 164 bcm2838pcie_match(device_t parent, cfdata_t match, void *aux) 165 { 166 struct fdt_attach_args * const faa = aux; 167 168 return of_compatible_match(faa->faa_phandle, compat_data); 169 } 170 171 static void 172 bcm2838pcie_attach(device_t parent, device_t self, void *aux) 173 { 174 struct bcm2838pcie_softc *sc = device_private(self); 175 struct fdt_attach_args * const faa = aux; 176 bus_addr_t addr; 177 bus_size_t size; 178 bus_dma_tag_t dmat; 179 bus_space_tag_t bst; 180 bus_space_handle_t bsh; 181 int error; 182 183 sc->sc_dev = self; 184 185 mutex_init(&sc->sc_bcmstb.sc_lock, MUTEX_DEFAULT, IPL_HIGH); 186 187 error = fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size); 188 if (error) { 189 aprint_error_dev(sc->sc_dev, ": couldn't get registers\n"); 190 return; 191 } 192 193 // bst = faa->faa_bst; 194 extern struct bus_space arm_generic_bs_tag; 195 bst = &arm_generic_bs_tag; 196 197 if (bus_space_map(faa->faa_bst, addr, size, 0, &bsh)) { 198 aprint_error_dev(sc->sc_dev, ": unable to map device\n"); 199 return; 200 } 201 202 /* RPI4 limits PCIe DMA to the first 3GB */ 203 error = bus_dmatag_subregion(faa->faa_dmat, 0, 0xbfffffff, 204 &dmat, BUS_DMA_WAITOK); 205 206 if (error == EOPNOTSUPP) { 207 /* assume default DMA tag is fine */ 208 dmat = faa->faa_dmat; 209 } else if (error) { 210 aprint_error_dev(sc->sc_dev, ": unable to subregion DMA\n"); 211 bus_space_unmap(faa->faa_bst, bsh, size); 212 return; 213 } 214 215 aprint_naive("\n"); 216 aprint_normal(": Broadcom PCIE Host Controller\n"); 217 218 if (error == 0) 219 aprint_normal_dev(sc->sc_dev, "Using 3GB DMA subregion\n"); 220 221 sc->sc_bcmstb.sc_bst = bst; 222 sc->sc_bcmstb.sc_bsh = bsh; 223 sc->sc_bcmstb.sc_dmat = dmat; 224 sc->sc_bcmstb.sc_name = device_xname(sc->sc_dev); 225 sc->sc_bcmstb.sc_phandle = faa->faa_phandle; 226 227 bcmstb_attach(sc->sc_dev, &sc->sc_bcmstb); 228 } 229 230 static void 231 bcmstb_attach(device_t self, struct bcmstb_softc *sc) 232 { 233 struct arm32_pci_chipset *pc; 234 struct pcibus_attach_args pba; 235 int error; 236 237 // fdtbus_register_interrupt_controller(self, OF_child(sc->sc_phandle), 238 // &bcmstb_intrfuncs); 239 240 pc = &sc->sc_pc; 241 242 pc->pc_conf_v = (void *)sc; 243 pc->pc_attach_hook = bcmstb_attach_hook; 244 pc->pc_bus_maxdevs = bcmstb_bus_maxdevs; 245 pc->pc_make_tag = bcmstb_make_tag; 246 pc->pc_decompose_tag = bcmstb_decompose_tag; 247 pc->pc_get_segment = bcmstb_get_segment; 248 pc->pc_conf_read = bcmstb_conf_read; 249 pc->pc_conf_write = bcmstb_conf_write; 250 pc->pc_conf_hook = bcmstb_conf_hook; 251 pc->pc_conf_interrupt = bcmstb_conf_interrupt; 252 253 pc->pc_intr_v = (void *)sc; 254 pc->pc_intr_map = bcmstb_intr_map; 255 pc->pc_intr_string = bcmstb_intr_string; 256 pc->pc_intr_evcnt = bcmstb_intr_evcnt; 257 pc->pc_intr_setattr = bcmstb_intr_setattr; 258 pc->pc_intr_establish = bcmstb_intr_establish; 259 pc->pc_intr_disestablish = bcmstb_intr_disestablish; 260 261 262 /* XXX bus-range */ 263 sc->sc_bus_min = 0x00; 264 sc->sc_bus_max = 0x01; 265 266 error = bcmstb_config(sc); 267 if (error) { 268 aprint_error_dev(self, "configuration failed: %d\n", error); 269 return; 270 } 271 272 memset(&pba, 0, sizeof(pba)); 273 pba.pba_flags = sc->sc_pci_flags; 274 pba.pba_iot = &sc->sc_io.bst; 275 pba.pba_memt = &sc->sc_mem.bst; 276 pba.pba_dmat = sc->sc_dmat; 277 #ifdef _PCI_HAVE_DMA64 278 pba.pba_dmat64 = sc->sc_dmat; 279 #endif 280 pba.pba_pc = pc; 281 pba.pba_bus = sc->sc_bus_min; 282 283 config_found_ia(self, "pcibus", &pba, pcibusprint); 284 } 285 286 static void 287 bcmstb_makespace(struct bcmstb_softc *sc, struct bcmstb_busspace *bs, int flags) 288 { 289 bs->bst = *sc->sc_bst; 290 bs->bst.bs_cookie = bs; 291 bs->map = bs->bst.bs_map; 292 bs->bst.bs_map = bcmstb_bus_space_map; 293 bs->flags = flags; 294 } 295 296 static int 297 bcmstb_addrange(struct bcmstb_busspace *bs, bus_addr_t pci, bus_addr_t bus, bus_size_t sz) 298 { 299 if (bs->nranges >= __arraycount(bs->ranges)) 300 return -1; 301 302 bs->ranges[bs->nranges].bpci = pci; 303 bs->ranges[bs->nranges].bbus = bus; 304 bs->ranges[bs->nranges].size = sz; 305 ++bs->nranges; 306 307 return 0; 308 } 309 310 static int 311 bcmstb_config(struct bcmstb_softc *sc) 312 { 313 const u_int *ranges; 314 int len, type, error; 315 struct pciconf_resources *pcires; 316 uint32_t phys_hi; 317 uint64_t bus_phys, cpu_phys, size; 318 319 bcmstb_makespace(sc, &sc->sc_io, PCI_FLAGS_IO_OKAY); 320 bcmstb_makespace(sc, &sc->sc_mem, PCI_FLAGS_MEM_OKAY); 321 322 ranges = fdtbus_get_prop(sc->sc_phandle, "ranges", &len); 323 if (ranges == NULL) { 324 aprint_error("%s: missing 'ranges' property\n", sc->sc_name); 325 return ENXIO; 326 } 327 328 pcires = pciconf_resource_init(); 329 330 while (len >= 28) { 331 phys_hi = be32toh(ranges[0]); 332 bus_phys = ((uint64_t)be32toh(ranges[1])) << 32 | be32toh(ranges[2]); 333 cpu_phys = ((uint64_t)be32toh(ranges[3])) << 32 | be32toh(ranges[4]); 334 size = ((uint64_t)be32toh(ranges[5])) << 32 | be32toh(ranges[6]); 335 336 len -= 28; 337 ranges += 7; 338 339 switch (__SHIFTOUT(phys_hi, PHYS_HI_SPACE)) { 340 case PHYS_HI_SPACE_IO: 341 if (bcmstb_addrange(&sc->sc_io, bus_phys, cpu_phys, size)) { 342 aprint_error("%s: too many IO ranges\n", sc->sc_name); 343 continue; 344 } 345 type = PCICONF_RESOURCE_IO; 346 347 aprint_verbose("%s: IO: 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 348 sc->sc_name, 349 bus_phys, size, cpu_phys); 350 351 error = pciconf_resource_add(pcires, type, bus_phys, size); 352 if (error == 0) 353 sc->sc_pci_flags |= PCI_FLAGS_IO_OKAY; 354 break; 355 case PHYS_HI_SPACE_MEM64: 356 /* FALLTHROUGH */ 357 case PHYS_HI_SPACE_MEM32: 358 if (bcmstb_addrange(&sc->sc_mem, bus_phys, cpu_phys, size)) { 359 aprint_error("%s: too many mem ranges\n", sc->sc_name); 360 continue; 361 } 362 if ((phys_hi & PHYS_HI_PREFETCH) != 0 || 363 __SHIFTOUT(phys_hi, PHYS_HI_SPACE) == PHYS_HI_SPACE_MEM64) { 364 type = PCICONF_RESOURCE_PREFETCHABLE_MEM; 365 } else { 366 type = PCICONF_RESOURCE_MEM; 367 } 368 369 aprint_verbose("%s: MMIO (%d-bit%s): 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 370 sc->sc_name, 371 __SHIFTOUT(phys_hi, PHYS_HI_SPACE) == PHYS_HI_SPACE_MEM64 ? 64 : 32, 372 type == PCICONF_RESOURCE_PREFETCHABLE_MEM ? " prefetchable" : "", 373 bus_phys, size, cpu_phys); 374 375 error = pciconf_resource_add(pcires, type, bus_phys, size); 376 if (error == 0) 377 sc->sc_pci_flags |= PCI_FLAGS_MEM_OKAY; 378 break; 379 default: 380 break; 381 } 382 } 383 384 error = bcmstb_setup(sc); 385 if (error) 386 return error; 387 388 error = pci_configure_bus(&sc->sc_pc, pcires, sc->sc_bus_min, 64); 389 pciconf_resource_fini(pcires); 390 391 return error; 392 } 393 394 static void 395 bcmstb_setwin(struct bcmstb_softc *sc, int win, uint64_t pa, uint64_t ca, 396 uint64_t sz) 397 { 398 uint32_t base, limit; 399 400 STBWRITE(sc, PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO(win), pa); 401 STBWRITE(sc, PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI(win), pa >> 32); 402 403 base = (ca >> 20) & 0xfff; 404 limit = ((ca + sz - 1) >> 20) & 0xfff; 405 406 STBRMW(sc, PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT(win), 407 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE 408 | PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT, 409 __SHIFTIN(base, PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE) 410 | __SHIFTIN(limit, PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT)); 411 412 base = (ca >> 32) & 0xff; 413 limit = ((ca + sz - 1) >> 32) & 0xff; 414 415 STBRMW(sc, PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI(win), 416 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE, 417 __SHIFTIN(base, PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE)); 418 419 STBRMW(sc, PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI(win), 420 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT, 421 __SHIFTIN(base, PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT)); 422 } 423 424 static int 425 bcmstb_encode_size(int bits) 426 { 427 /* 4K .. 32K */ 428 if (bits >= 12 && bits <= 15) 429 return 28 + (bits - 12); 430 431 /* 64K .. 32G */ 432 if (bits >= 16 && bits <= 35) 433 return 1 + (bits - 16); 434 435 /* invalid */ 436 return 0; 437 } 438 439 static int 440 bcmstb_setup(struct bcmstb_softc *sc) 441 { 442 struct bcmstb_busspace * const bs = &sc->sc_mem; 443 uint32_t w, m; 444 uint64_t ad; 445 int t, i, sz; 446 447 /* Reset */ 448 STBRMW(sc, PCIE_RGR1_SW_INIT_1, 0, PCIE_RGR1_SW_INIT_1_INIT); 449 delay(200); 450 STBRMW(sc, PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_INIT, 0); 451 452 /* Clear IDDQ */ 453 STBRMW(sc, PCIE_MISC_HARD_PCIE_HARD_DEBUG, 454 PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ, 0); 455 w = STBREAD(sc, PCIE_MISC_HARD_PCIE_HARD_DEBUG); 456 457 delay(100); 458 459 w = STBREAD(sc, PCIE_MISC_REVISION); 460 printf("RootBridge Revision %x\n", 461 (u_int)__SHIFTOUT(w, PCIE_MISC_REVISION_MAJMIN)); 462 463 STBRMW(sc, PCIE_MISC_MISC_CTRL, 464 PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE, /* 128B */ 465 PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN 466 | PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE); 467 468 /* 469 * XXX Inbound window for RPI4 is 3GB, should be parsed 470 * from dma-ranges attribute 471 */ 472 ad = 0; 473 sz = bcmstb_encode_size(32); 474 475 w = (__SHIFTIN(ad, PCIE_MISC_RC_BARx_CONFIG_LO_MATCH_ADDRESS) 476 & PCIE_MISC_RC_BARx_CONFIG_LO_MATCH_ADDRESS) 477 | __SHIFTIN(sz, PCIE_MISC_RC_BARx_CONFIG_LO_SIZE); 478 STBWRITE(sc, PCIE_MISC_RC_BAR2_CONFIG_LO, w); 479 STBWRITE(sc, PCIE_MISC_RC_BAR2_CONFIG_HI, ad >> 32); 480 481 STBRMW(sc, PCIE_MISC_MISC_CTRL, 482 PCIE_MISC_MISC_CTRL_SCB0_SIZE, 483 __SHIFTIN(sz, PCIE_MISC_MISC_CTRL_SCB0_SIZE)); 484 485 /* disable PCIe->GISB window */ 486 STBWRITE(sc, PCIE_MISC_RC_BAR1_CONFIG_LO, 0); 487 STBWRITE(sc, PCIE_MISC_RC_BAR1_CONFIG_HI, 0); 488 /* disable PCIe->SCB window */ 489 STBWRITE(sc, PCIE_MISC_RC_BAR3_CONFIG_LO, 0); 490 STBWRITE(sc, PCIE_MISC_RC_BAR3_CONFIG_HI, 0); 491 492 for (i=0; i<bs->nranges; ++i) { 493 bcmstb_setwin(sc, i, 494 bs->ranges[i].bpci, 495 bs->ranges[i].bbus, 496 bs->ranges[i].size); 497 } 498 499 STBWRITE(sc, PCIE_INTR2_MASK_CLR, ~0); 500 STBWRITE(sc, PCIE_INTR2_MASK_SET, ~0); 501 502 /* Release PERST */ 503 STBRMW(sc, PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_PERST, 0); 504 505 t = 100; 506 m = PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP 507 | PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE; 508 do { 509 w = STBREAD(sc, PCIE_MISC_PCIE_STATUS); 510 delay(1000); 511 --t; 512 } while ((w & m) != m && t > 0); 513 if ((w & m) != m) { 514 printf("PCIe link not ready\n"); 515 return 1; 516 } 517 518 m = PCIE_MISC_PCIE_STATUS_PCIE_PORT; 519 if ((w & m) != m) { 520 printf("PCIe link not in RC mode\n"); 521 return 1; 522 } 523 524 /* advertise L0 and L1s capability */ 525 STBRMW(sc, PCIE_RC_CFG_PRIV1_LINK_CAPABILITY, 526 PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT, 527 __SHIFTIN(0x3, PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT)); 528 529 /* present as PCIe->PCIe bridge */ 530 STBRMW(sc, PCIE_RC_CFG_PRIV1_ID_VAL3, 531 PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE, 532 __SHIFTIN(0x60400, PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE)); 533 534 /* XXX enable SSC */ 535 536 /* clear endian mode == little endian */ 537 STBRMW(sc, PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1, 538 PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2, 539 0); 540 541 /* Gate clock with CLKREQ# */ 542 STBRMW(sc, PCIE_MISC_HARD_PCIE_HARD_DEBUG, 543 0, 544 PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ); 545 546 return 0; 547 } 548 549 static void 550 bcmstb_attach_hook(device_t parent, device_t self, 551 struct pcibus_attach_args *pba) 552 { 553 } 554 555 static int 556 bcmstb_bus_maxdevs(void *v, int bus) 557 { 558 // struct bcmstb_softc *sc = v; 559 560 return 1; 561 } 562 563 static pcitag_t 564 bcmstb_make_tag(void *v, int bus, int device, int function) 565 { 566 return (bus << 20) | (device << 15) | (function << 12); 567 } 568 569 static void 570 bcmstb_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 571 { 572 if (bp != NULL) 573 *bp = (tag >> 20) & 0xff; 574 if (dp != NULL) 575 *dp = (tag >> 15) & 0x1f; 576 if (fp != NULL) 577 *fp = (tag >> 12) & 0x7; 578 } 579 580 static u_int 581 bcmstb_get_segment(void *v) 582 { 583 // struct bcmstb_softc *sc = v; 584 585 return 1; 586 } 587 588 static pcireg_t 589 bcmstb_conf_read(void *v, pcitag_t tag, int offset) 590 { 591 struct bcmstb_softc *sc = v; 592 int bus, dev, fn; 593 uint32_t idx, reg; 594 pcireg_t data; 595 596 if (offset < 0 || offset > 4092) 597 return (pcireg_t) -1; 598 599 bcmstb_decompose_tag(v, tag, &bus, &dev, &fn); 600 601 if (bus < 2 && dev > 0) 602 return (pcireg_t) -1; 603 604 idx = __SHIFTIN(bus, PCIE_EXT_CFG_INDEX_BUSNUM) 605 | __SHIFTIN(dev, PCIE_EXT_CFG_INDEX_SLOT) 606 | __SHIFTIN(fn, PCIE_EXT_CFG_INDEX_FUNC); 607 608 reg = bus > 0 ? PCIE_EXT_CFG_DATA + offset : offset; 609 610 mutex_enter(&sc->sc_lock); 611 STBWRITE(sc, PCIE_EXT_CFG_INDEX, idx); 612 data = STBREAD(sc, reg); 613 mutex_exit(&sc->sc_lock); 614 615 return data; 616 } 617 618 static void 619 bcmstb_conf_write(void *v, pcitag_t tag, int offset, pcireg_t data) 620 { 621 struct bcmstb_softc *sc = v; 622 int bus, dev, fn; 623 uint32_t idx, reg; 624 625 if (offset < 0 || offset > 4092) 626 return; 627 628 bcmstb_decompose_tag(v, tag, &bus, &dev, &fn); 629 630 if (bus < 2 && dev > 0) 631 return; 632 633 idx = __SHIFTIN(bus, PCIE_EXT_CFG_INDEX_BUSNUM) 634 | __SHIFTIN(dev, PCIE_EXT_CFG_INDEX_SLOT) 635 | __SHIFTIN(fn, PCIE_EXT_CFG_INDEX_FUNC); 636 637 reg = bus > 0 ? PCIE_EXT_CFG_DATA + offset : offset; 638 639 mutex_enter(&sc->sc_lock); 640 STBWRITE(sc, PCIE_EXT_CFG_INDEX, idx); 641 STBWRITE(sc, reg, data); 642 mutex_exit(&sc->sc_lock); 643 } 644 645 static int 646 bcmstb_conf_hook(void *v, int bus, int dev, int fn, pcireg_t id) 647 { 648 /* 649 * Newer RPi4 lacks the VL805 EEPROM, so the 650 * firmware needs to be loaded after a reset. 651 * Trigger the GPU to do this. 652 */ 653 654 if (bus == 1 && dev == 0 && fn == 0 && 655 PCI_VENDOR(id) == PCI_VENDOR_VIATECH && 656 PCI_PRODUCT(id) == PCI_PRODUCT_VIATECH_VL805_XHCI) { 657 658 uint32_t idx; 659 idx = __SHIFTIN(bus, PCIE_EXT_CFG_INDEX_BUSNUM) 660 | __SHIFTIN(dev, PCIE_EXT_CFG_INDEX_SLOT) 661 | __SHIFTIN(fn, PCIE_EXT_CFG_INDEX_FUNC); 662 663 rpi_notify_xhci_reset(idx); 664 } 665 666 return PCI_CONF_DEFAULT; 667 } 668 669 static void 670 bcmstb_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *ilinep) 671 { 672 } 673 674 static int 675 bcmstb_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih) 676 { 677 struct bcmstb_softc *sc = pa->pa_pc->pc_intr_v; 678 u_int addr_cells, interrupt_cells; 679 const u_int *imap, *imask; 680 int imaplen, imasklen; 681 u_int match[4]; 682 int index, off; 683 684 if (pa->pa_intrpin == 0) 685 return EINVAL; 686 687 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 688 imask = fdtbus_get_prop(sc->sc_phandle, "interrupt-map-mask", &imasklen) 689 ; 690 if (imap == NULL || imask == NULL || imasklen != 16) 691 return EINVAL; 692 693 off = CFG_OFFSET(pa->pa_bus, pa->pa_device, pa->pa_function, 0); 694 695 /* Convert attach args to specifier */ 696 match[0] = htobe32(off) & imask[0]; 697 match[1] = htobe32(0) & imask[1]; 698 match[2] = htobe32(0) & imask[2]; 699 match[3] = htobe32(pa->pa_intrpin) & imask[3]; 700 701 index = 0; 702 while (imaplen >= 20) { 703 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 704 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 705 addr_cells = 2; 706 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 707 interrupt_cells = 0; 708 if (imaplen < (addr_cells + interrupt_cells) * 4) 709 return ENXIO; 710 711 if ((imap[0] & imask[0]) == match[0] && 712 (imap[1] & imask[1]) == match[1] && 713 (imap[2] & imask[2]) == match[2] && 714 (imap[3] & imask[3]) == match[3]) { 715 *ih = index; 716 return 0; 717 } 718 719 imap += (5 + addr_cells + interrupt_cells); 720 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 721 index++; 722 } 723 724 return EINVAL; 725 } 726 727 static const u_int * 728 bcmstb_find_intr(struct bcmstb_softc *sc, pci_intr_handle_t ih, int *pihandle) 729 { 730 u_int addr_cells, int_cells; 731 u_int iaddr_cells, iint_cells; 732 int imaplen, index; 733 const u_int *imap; 734 int intc; 735 736 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 737 if (imap == NULL) 738 return NULL; 739 imaplen /= 4; 740 741 if (of_getprop_uint32(sc->sc_phandle, "#address-cells", &addr_cells)) 742 return NULL; 743 744 if (of_getprop_uint32(sc->sc_phandle, "#interrupt-cells", &int_cells)) 745 return NULL; 746 747 index = 0; 748 while (imaplen >= int_cells + addr_cells + 1) { 749 750 intc = fdtbus_get_phandle_from_native(be32toh(imap[int_cells + addr_cells])); 751 if (of_getprop_uint32(intc, "#interrupt-cells", &iint_cells)) 752 break; 753 754 if (of_getprop_uint32(intc, "#address-cells", &iaddr_cells)) 755 iaddr_cells = 0; 756 757 imap += addr_cells + int_cells + 1; 758 imaplen -= addr_cells + int_cells + 1; 759 760 if (imaplen < iint_cells + iaddr_cells) 761 break; 762 763 /* XXX, should really match child */ 764 if (index == ih) { 765 *pihandle = intc; 766 return imap; 767 } 768 769 imap += iaddr_cells + iint_cells; 770 imaplen -= iaddr_cells + iint_cells; 771 index++; 772 } 773 774 return NULL; 775 } 776 777 static const char * 778 bcmstb_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 779 { 780 struct bcmstb_softc *sc = v; 781 const int irq = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ); 782 const int vec = __SHIFTOUT(ih, ARM_PCI_INTR_MSI_VEC); 783 const u_int *specifier; 784 int ihandle; 785 786 if (ih & ARM_PCI_INTR_MSIX) { 787 snprintf(buf, len, "irq %d (MSI-X vec %d)", irq, vec); 788 } else if (ih & ARM_PCI_INTR_MSI) { 789 snprintf(buf, len, "irq %d (MSI vec %d)", irq, vec); 790 } else { 791 specifier = bcmstb_find_intr(sc, ih & ARM_PCI_INTR_IRQ, &ihandle); 792 if (specifier == NULL) 793 return NULL; 794 if (!fdtbus_intr_str_raw(ihandle, specifier, buf, len)) 795 return NULL; 796 } 797 798 return buf; 799 } 800 801 static const struct evcnt * 802 bcmstb_intr_evcnt(void *v, pci_intr_handle_t ih) 803 { 804 return NULL; 805 } 806 807 static int 808 bcmstb_intr_setattr(void *v, pci_intr_handle_t *ih, int attr, uint64_t data) 809 { 810 switch (attr) { 811 default: 812 return ENODEV; 813 } 814 } 815 816 static void * 817 bcmstb_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 818 int (*callback)(void *), void *arg, const char *xname) 819 { 820 struct bcmstb_softc *sc = v; 821 const int flags = (ih & ARM_PCI_INTR_MPSAFE) ? FDT_INTR_MPSAFE : 0; 822 const u_int *specifier; 823 int ihandle; 824 825 if ((ih & (ARM_PCI_INTR_MSI | ARM_PCI_INTR_MSIX)) != 0) { 826 // return arm_pci_msi_intr_establish(&sc->sc_pc, ih, ipl, 827 // callback, arg, xname); 828 return NULL; 829 } 830 831 /* should search for PCI device */ 832 specifier = bcmstb_find_intr(sc, ih & ARM_PCI_INTR_IRQ, &ihandle); 833 if (specifier == NULL) 834 return NULL; 835 836 return fdtbus_intr_establish_raw(ihandle, specifier, ipl, flags, 837 callback, arg, xname); 838 } 839 840 static void 841 bcmstb_intr_disestablish(void *v, void *vih) 842 { 843 struct bcmstb_softc *sc = v; 844 845 fdtbus_intr_disestablish(sc->sc_phandle, vih); 846 } 847 848 static int 849 bcmstb_bus_space_map(void *t, bus_addr_t bpa, bus_size_t size, int flag, 850 bus_space_handle_t *bshp) 851 { 852 struct bcmstb_busspace * const bs = t; 853 854 // if ((bs->flags & PCI_FLAGS_IO_OKAY) != 0) { 855 /* Force strongly ordered mapping for all I/O space */ 856 flag = _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED; 857 // } 858 859 for (size_t i = 0; i < bs->nranges; i++) { 860 const bus_addr_t rmin = bs->ranges[i].bpci; 861 const bus_addr_t rmax = bs->ranges[i].bpci - 1 + bs->ranges[i] 862 .size; 863 if ((bpa >= rmin) && ((bpa - 1 + size) <= rmax)) { 864 const bus_addr_t pa = bs->ranges[i].bbus + (bpa - rmin); 865 866 return bs->map(t, pa, size, flag, bshp); 867 } 868 } 869 870 return ERANGE; 871 } 872 873
Indexes created Mon Sep 29 13:09:55 GMT 2025