bcm53xx_board.c revision 1.16
1 /* $NetBSD: bcm53xx_board.c,v 1.16 2013/08/29 15:46:17 riz Exp $ */ 2 /*- 3 * Copyright (c) 2012 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas of 3am Software Foundry. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "opt_broadcom.h" 32 33 #define _ARM32_BUS_DMA_PRIVATE 34 35 #include <sys/cdefs.h> 36 37 __KERNEL_RCSID(1, "$NetBSD: bcm53xx_board.c,v 1.16 2013/08/29 15:46:17 riz Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/bus.h> 41 #include <sys/cpu.h> 42 #include <sys/device.h> 43 44 #include <prop/proplib.h> 45 46 #include <net/if.h> 47 #include <net/if_ether.h> 48 49 #define CRU_PRIVATE 50 #define DDR_PRIVATE 51 #define DMU_PRIVATE 52 #define ARMCORE_PRIVATE 53 #define SRAB_PRIVATE 54 55 #include <arm/cortex/a9tmr_var.h> 56 #include <arm/cortex/pl310_var.h> 57 #include <arm/mainbus/mainbus.h> 58 59 #include <arm/broadcom/bcm53xx_reg.h> 60 #include <arm/broadcom/bcm53xx_var.h> 61 62 bus_space_tag_t bcm53xx_ioreg_bst = &bcmgen_bs_tag; 63 bus_space_handle_t bcm53xx_ioreg_bsh; 64 bus_space_tag_t bcm53xx_armcore_bst = &bcmgen_bs_tag; 65 bus_space_handle_t bcm53xx_armcore_bsh; 66 67 static struct cpu_softc cpu_softc; 68 69 struct arm32_dma_range bcm53xx_dma_ranges[] = { 70 [0] = { 71 .dr_sysbase = 0x80000000, 72 .dr_busbase = 0x80000000, 73 .dr_len = 0x10000000, 74 }, [1] = { 75 .dr_sysbase = 0x90000000, 76 .dr_busbase = 0x90000000, 77 }, 78 }; 79 80 struct arm32_bus_dma_tag bcm53xx_dma_tag = { 81 ._ranges = bcm53xx_dma_ranges, 82 ._nranges = __arraycount(bcm53xx_dma_ranges), 83 _BUS_DMAMAP_FUNCS, 84 _BUS_DMAMEM_FUNCS, 85 _BUS_DMATAG_FUNCS, 86 }; 87 88 struct arm32_dma_range bcm53xx_coherent_dma_ranges[] = { 89 [0] = { 90 .dr_sysbase = 0x80000000, 91 .dr_busbase = 0x80000000, 92 .dr_len = 0x10000000, 93 .dr_flags = _BUS_DMAMAP_COHERENT, 94 }, [1] = { 95 .dr_sysbase = 0x90000000, 96 .dr_busbase = 0x90000000, 97 }, 98 }; 99 100 struct arm32_bus_dma_tag bcm53xx_coherent_dma_tag = { 101 ._ranges = bcm53xx_coherent_dma_ranges, 102 ._nranges = __arraycount(bcm53xx_coherent_dma_ranges), 103 _BUS_DMAMAP_FUNCS, 104 _BUS_DMAMEM_FUNCS, 105 _BUS_DMATAG_FUNCS, 106 }; 107 108 #ifdef _ARM32_NEED_BUS_DMA_BOUNCE 109 struct arm32_bus_dma_tag bcm53xx_bounce_dma_tag = { 110 ._ranges = bcm53xx_coherent_dma_ranges, 111 ._nranges = 1, 112 _BUS_DMAMAP_FUNCS, 113 _BUS_DMAMEM_FUNCS, 114 _BUS_DMATAG_FUNCS, 115 }; 116 #endif 117 118 #ifdef BCM53XX_CONSOLE_EARLY 119 #include <dev/ic/ns16550reg.h> 120 #include <dev/ic/comreg.h> 121 #include <dev/cons.h> 122 123 static vaddr_t com_base; 124 125 static inline uint32_t 126 uart_read(bus_size_t o) 127 { 128 return *(volatile uint8_t *)(com_base + o); 129 } 130 131 static inline void 132 uart_write(bus_size_t o, uint32_t v) 133 { 134 *(volatile uint8_t *)(com_base + o) = v; 135 } 136 137 static int 138 bcm53xx_cngetc(dev_t dv) 139 { 140 if ((uart_read(com_lsr) & LSR_RXRDY) == 0) 141 return -1; 142 143 return uart_read(com_data) & 0xff; 144 } 145 146 static void 147 bcm53xx_cnputc(dev_t dv, int c) 148 { 149 int timo = 150000; 150 151 while ((uart_read(com_lsr) & LSR_TXRDY) == 0 && --timo > 0) 152 ; 153 154 uart_write(com_data, c); 155 156 timo = 150000; 157 while ((uart_read(com_lsr) & LSR_TSRE) == 0 && --timo > 0) 158 ; 159 } 160 161 static struct consdev bcm53xx_earlycons = { 162 .cn_putc = bcm53xx_cnputc, 163 .cn_getc = bcm53xx_cngetc, 164 .cn_pollc = nullcnpollc, 165 }; 166 #endif /* BCM53XX_CONSOLE_EARLY */ 167 168 psize_t 169 bcm53xx_memprobe(void) 170 { 171 bus_space_tag_t bst = bcm53xx_ioreg_bst; 172 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 173 174 /* 175 * First, let's read the magic DDR registers! 176 */ 177 const uint32_t v01 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_01); 178 const uint32_t v82 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_82); 179 const uint32_t v86 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_86); 180 const uint32_t v87 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_87); 181 182 /* 183 * Calculate chip parameters 184 * */ 185 const u_int rows = __SHIFTOUT(v01, CTL_01_MAX_ROW) 186 - __SHIFTOUT(v82, CTL_82_ROW_DIFF); 187 const u_int cols = __SHIFTOUT(v01, CTL_01_MAX_COL) 188 - __SHIFTOUT(v82, CTL_82_COL_DIFF); 189 const u_int banks_log2 = 3 - __SHIFTOUT(v82, CTL_82_BANK_DIFF); 190 191 /* 192 * For each chip select, increase the chip count if if is enabled. 193 */ 194 const u_int max_chips = __SHIFTOUT(v01, CTL_01_MAX_CHIP_SEL); 195 u_int cs_map = __SHIFTOUT(v86, CTL_86_CS_MAP); 196 u_int chips = 0; 197 198 for (u_int i = 0; cs_map != 0 && i < max_chips; i++, cs_map >>= 1) { 199 chips += (cs_map & 1); 200 } 201 202 /* get log2(ddr width) */ 203 204 const u_int ddr_width_log2 = (v87 & CTL_87_REDUC) ? 1 : 2; 205 206 /* 207 * Let's add up all the things that contribute to the size of a chip. 208 */ 209 const u_int chip_size_log2 = cols + rows + banks_log2 + ddr_width_log2; 210 211 /* 212 * Now our memory size is simply the number of chip shifted by the 213 * log2(chip_size). 214 */ 215 return (psize_t) chips << chip_size_log2; 216 } 217 218 static inline uint32_t 219 bcm53xx_freq_calc(struct bcm53xx_clock_info *clk, 220 uint32_t pdiv, uint32_t ndiv_int, uint32_t ndiv_frac) 221 { 222 if (ndiv_frac == 0 && pdiv == 1) 223 return ndiv_int * clk->clk_ref; 224 225 uint64_t freq64 = ((uint64_t)ndiv_int << 30) + ndiv_frac; 226 freq64 *= clk->clk_ref; 227 if (pdiv > 1) 228 freq64 /= pdiv; 229 return (uint32_t) (freq64 >> 30); 230 } 231 232 static uint32_t 233 bcm53xx_value_wrap(uint32_t value, uint32_t mask) 234 { 235 /* 236 * n is n except when n is 0 then n = mask + 1. 237 */ 238 return ((__SHIFTOUT(value, mask) - 1) & __SHIFTOUT(mask, mask)) + 1; 239 } 240 241 static void 242 bcm53xx_genpll_clock_init(struct bcm53xx_clock_info *clk, uint32_t control5, 243 uint32_t control6, uint32_t control7) 244 { 245 const uint32_t pdiv = bcm53xx_value_wrap(control6, 246 GENPLL_CONTROL6_PDIV); 247 const uint32_t ndiv_int = bcm53xx_value_wrap(control5, 248 GENPLL_CONTROL5_NDIV_INT); 249 const uint32_t ndiv_frac = __SHIFTOUT(control5, 250 GENPLL_CONTROL5_NDIV_FRAC); 251 252 clk->clk_genpll = bcm53xx_freq_calc(clk, pdiv, ndiv_int, ndiv_frac); 253 254 const uint32_t ch0_mdiv = bcm53xx_value_wrap(control6, 255 GENPLL_CONTROL6_CH0_MDIV); 256 const uint32_t ch1_mdiv = bcm53xx_value_wrap(control6, 257 GENPLL_CONTROL6_CH1_MDIV); 258 const uint32_t ch2_mdiv = bcm53xx_value_wrap(control6, 259 GENPLL_CONTROL6_CH2_MDIV); 260 const uint32_t ch3_mdiv = bcm53xx_value_wrap(control7, 261 GENPLL_CONTROL7_CH3_MDIV); 262 263 clk->clk_mac = clk->clk_genpll / ch0_mdiv; // GENPLL CH0 264 clk->clk_robo = clk->clk_genpll / ch1_mdiv; // GENPLL CH1 265 clk->clk_usb2 = clk->clk_genpll / ch2_mdiv; // GENPLL CH2 266 clk->clk_iproc = clk->clk_genpll / ch3_mdiv; // GENPLL CH3 267 } 268 269 static void 270 bcm53xx_lcpll_clock_init(struct bcm53xx_clock_info *clk, uint32_t control1, 271 uint32_t control2) 272 { 273 const uint32_t pdiv = bcm53xx_value_wrap(control1, 274 LCPLL_CONTROL1_PDIV); 275 const uint32_t ndiv_int = bcm53xx_value_wrap(control1, 276 LCPLL_CONTROL1_NDIV_INT); 277 const uint32_t ndiv_frac = __SHIFTOUT(control1, 278 LCPLL_CONTROL1_NDIV_FRAC); 279 280 clk->clk_lcpll = bcm53xx_freq_calc(clk, pdiv, ndiv_int, ndiv_frac); 281 282 const uint32_t ch0_mdiv = bcm53xx_value_wrap(control2, 283 LCPLL_CONTROL2_CH0_MDIV); 284 const uint32_t ch1_mdiv = bcm53xx_value_wrap(control2, 285 LCPLL_CONTROL2_CH1_MDIV); 286 const uint32_t ch2_mdiv = bcm53xx_value_wrap(control2, 287 LCPLL_CONTROL2_CH2_MDIV); 288 const uint32_t ch3_mdiv = bcm53xx_value_wrap(control2, 289 LCPLL_CONTROL2_CH3_MDIV); 290 291 clk->clk_pcie_ref = clk->clk_lcpll / ch0_mdiv; // LCPLL CH0 292 clk->clk_sdio = clk->clk_lcpll / ch1_mdiv; // LCPLL CH1 293 clk->clk_ddr_ref = clk->clk_lcpll / ch2_mdiv; // LCPLL CH2 294 clk->clk_axi = clk->clk_lcpll / ch3_mdiv; // LCPLL CH3 295 } 296 297 static void 298 bcm53xx_usb_clock_init(struct bcm53xx_clock_info *clk, uint32_t usb2_control) 299 { 300 const uint32_t pdiv = bcm53xx_value_wrap(usb2_control, 301 USB2_CONTROL_PDIV); 302 const uint32_t ndiv = bcm53xx_value_wrap(usb2_control, 303 USB2_CONTROL_NDIV_INT); 304 305 uint32_t usb_ref = (clk->clk_usb2 / pdiv) * ndiv; 306 if (usb_ref != USB2_REF_CLK) { 307 /* 308 * USB Reference Clock isn't 1.92GHz. So we need to modify 309 * USB2_CONTROL to produce it. 310 */ 311 uint32_t new_ndiv = (USB2_REF_CLK / clk->clk_usb2) * pdiv; 312 usb2_control &= ~USB2_CONTROL_NDIV_INT; 313 usb2_control |= __SHIFTIN(new_ndiv, USB2_CONTROL_NDIV_INT); 314 315 // Allow Clocks to be modified 316 bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh, 317 CRU_BASE + CRU_CLKSET_KEY, CRU_CLKSET_KEY_MAGIC); 318 319 // Update USB2 clock generator 320 bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh, 321 CRU_BASE + CRU_USB2_CONTROL, usb2_control); 322 323 // Prevent Clock modification 324 bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh, 325 CRU_BASE + CRU_CLKSET_KEY, 0); 326 327 usb_ref = (clk->clk_usb2 / pdiv) * new_ndiv; 328 } 329 330 clk->clk_usb_ref = usb_ref; 331 } 332 333 334 static void 335 bcm53xx_clock_init(struct bcm53xx_clock_info *clk) 336 { 337 clk->clk_ref = BCM53XX_REF_CLK; 338 clk->clk_sys = 8*clk->clk_ref; 339 } 340 341 /* 342 * F(ddr) = ((1 / pdiv) * ndiv * CH2) / (post_div * 2) 343 */ 344 static void 345 bcm53xx_get_ddr_freq(struct bcm53xx_clock_info *clk, uint32_t pll_status, 346 uint32_t pll_dividers) 347 { 348 const bool clocking_4x = (pll_status & PLL_STATUS_CLOCKING_4X) != 0; 349 u_int post_div = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_POST_DIV); 350 u_int pdiv = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_PDIV); 351 u_int ndiv = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_NDIV); 352 353 pdiv = ((pdiv - (clocking_4x ? 1 : 5)) & 7) + 1; 354 355 clk->clk_ddr_mhz = __SHIFTOUT(pll_status, PLL_STATUS_MHZ); 356 clk->clk_ddr = (clk->clk_ddr_ref / pdiv) * ndiv / (2 + post_div); 357 } 358 359 /* 360 * CPU_CLK = (1 / pdiv) * (ndiv_int + (ndiv_frac / 0x40000000)) x F(ref) 361 */ 362 static void 363 bcm53xx_get_cpu_freq(struct bcm53xx_clock_info *clk, 364 uint32_t pllarma, uint32_t pllarmb, uint32_t policy) 365 { 366 policy = __SHIFTOUT(policy, CLK_POLICY_FREQ_POLICY2); 367 368 if (policy == CLK_POLICY_REF_CLK) { 369 clk->clk_cpu = clk->clk_ref; 370 clk->clk_apb = clk->clk_cpu; 371 return; 372 } 373 374 if (policy == CLK_POLICY_SYS_CLK) { 375 clk->clk_cpu = clk->clk_sys; 376 clk->clk_apb = clk->clk_cpu / 4; 377 return; 378 } 379 380 const u_int pdiv = bcm53xx_value_wrap(pllarma, CLK_PLLARMA_PDIV); 381 const u_int ndiv_int = bcm53xx_value_wrap(pllarma, CLK_PLLARMA_NDIV_INT); 382 const u_int ndiv_frac = __SHIFTOUT(pllarmb, CLK_PLLARMB_NDIV_FRAC); 383 // const u_int apb_clk_div = __SHIFTOUT(apb_clk_div, CLK_APB_DIV_VALUE)+1; 384 385 const u_int cpu_div = (policy == CLK_POLICY_ARM_PLL_CH0) ? 4 : 2; 386 387 clk->clk_cpu = bcm53xx_freq_calc(clk, pdiv, ndiv_int, ndiv_frac) / cpu_div; 388 clk->clk_apb = clk->clk_cpu / 4; 389 } 390 391 struct bcm53xx_chip_state { 392 uint32_t bcs_lcpll_control1; 393 uint32_t bcs_lcpll_control2; 394 395 uint32_t bcs_genpll_control5; 396 uint32_t bcs_genpll_control6; 397 uint32_t bcs_genpll_control7; 398 399 uint32_t bcs_usb2_control; 400 401 uint32_t bcs_ddr_phy_ctl_pll_status; 402 uint32_t bcs_ddr_phy_ctl_pll_dividers; 403 404 uint32_t bcs_armcore_clk_policy; 405 uint32_t bcs_armcore_clk_pllarma; 406 uint32_t bcs_armcore_clk_pllarmb; 407 }; 408 409 static void 410 bcm53xx_get_chip_ioreg_state(struct bcm53xx_chip_state *bcs, 411 bus_space_tag_t bst, bus_space_handle_t bsh) 412 { 413 bcs->bcs_lcpll_control1 = bus_space_read_4(bst, bsh, 414 DMU_BASE + DMU_LCPLL_CONTROL1); 415 bcs->bcs_lcpll_control2 = bus_space_read_4(bst, bsh, 416 DMU_BASE + DMU_LCPLL_CONTROL2); 417 418 bcs->bcs_genpll_control5 = bus_space_read_4(bst, bsh, 419 CRU_BASE + CRU_GENPLL_CONTROL5); 420 bcs->bcs_genpll_control6 = bus_space_read_4(bst, bsh, 421 CRU_BASE + CRU_GENPLL_CONTROL6); 422 bcs->bcs_genpll_control7 = bus_space_read_4(bst, bsh, 423 CRU_BASE + CRU_GENPLL_CONTROL7); 424 425 bcs->bcs_usb2_control = bus_space_read_4(bst, bsh, 426 CRU_BASE + CRU_USB2_CONTROL); 427 428 bcs->bcs_ddr_phy_ctl_pll_status = bus_space_read_4(bst, bsh, 429 DDR_BASE + DDR_PHY_CTL_PLL_STATUS); 430 bcs->bcs_ddr_phy_ctl_pll_dividers = bus_space_read_4(bst, bsh, 431 DDR_BASE + DDR_PHY_CTL_PLL_DIVIDERS); 432 } 433 434 static void 435 bcm53xx_get_chip_armcore_state(struct bcm53xx_chip_state *bcs, 436 bus_space_tag_t bst, bus_space_handle_t bsh) 437 { 438 bcs->bcs_armcore_clk_policy = bus_space_read_4(bst, bsh, 439 ARMCORE_CLK_POLICY_FREQ); 440 bcs->bcs_armcore_clk_pllarma = bus_space_read_4(bst, bsh, 441 ARMCORE_CLK_PLLARMA); 442 bcs->bcs_armcore_clk_pllarmb = bus_space_read_4(bst, bsh, 443 ARMCORE_CLK_PLLARMB); 444 } 445 446 void 447 bcm53xx_cpu_softc_init(struct cpu_info *ci) 448 { 449 struct cpu_softc * const cpu = ci->ci_softc; 450 451 cpu->cpu_ioreg_bst = bcm53xx_ioreg_bst; 452 cpu->cpu_ioreg_bsh = bcm53xx_ioreg_bsh; 453 454 cpu->cpu_armcore_bst = bcm53xx_armcore_bst; 455 cpu->cpu_armcore_bsh = bcm53xx_armcore_bsh; 456 } 457 458 void 459 bcm53xx_print_clocks(void) 460 { 461 #if defined(VERBOSE_INIT_ARM) 462 const struct bcm53xx_clock_info * const clk = &cpu_softc.cpu_clk; 463 printf("ref clk = %u (%#x)\n", clk->clk_ref, clk->clk_ref); 464 printf("sys clk = %u (%#x)\n", clk->clk_sys, clk->clk_sys); 465 printf("lcpll clk = %u (%#x)\n", clk->clk_lcpll, clk->clk_lcpll); 466 printf("pcie ref clk = %u (%#x) [CH0]\n", clk->clk_pcie_ref, clk->clk_pcie_ref); 467 printf("sdio clk = %u (%#x) [CH1]\n", clk->clk_sdio, clk->clk_sdio); 468 printf("ddr ref clk = %u (%#x) [CH2]\n", clk->clk_ddr_ref, clk->clk_ddr_ref); 469 printf("axi clk = %u (%#x) [CH3]\n", clk->clk_axi, clk->clk_axi); 470 printf("genpll clk = %u (%#x)\n", clk->clk_genpll, clk->clk_genpll); 471 printf("mac clk = %u (%#x) [CH0]\n", clk->clk_mac, clk->clk_mac); 472 printf("robo clk = %u (%#x) [CH1]\n", clk->clk_robo, clk->clk_robo); 473 printf("usb2 clk = %u (%#x) [CH2]\n", clk->clk_usb2, clk->clk_usb2); 474 printf("iproc clk = %u (%#x) [CH3]\n", clk->clk_iproc, clk->clk_iproc); 475 printf("ddr clk = %u (%#x)\n", clk->clk_ddr, clk->clk_ddr); 476 printf("ddr mhz = %u (%#x)\n", clk->clk_ddr_mhz, clk->clk_ddr_mhz); 477 printf("cpu clk = %u (%#x)\n", clk->clk_cpu, clk->clk_cpu); 478 printf("apb clk = %u (%#x)\n", clk->clk_apb, clk->clk_apb); 479 printf("usb ref clk = %u (%#x)\n", clk->clk_usb_ref, clk->clk_usb_ref); 480 #endif 481 } 482 483 void 484 bcm53xx_bootstrap(vaddr_t iobase) 485 { 486 struct bcm53xx_chip_state bcs; 487 int error; 488 489 #ifdef BCM53XX_CONSOLE_EARLY 490 com_base = iobase + CCA_UART0_BASE; 491 cn_tab = &bcm53xx_earlycons; 492 #endif 493 494 bcm53xx_ioreg_bsh = (bus_space_handle_t) iobase; 495 error = bus_space_map(bcm53xx_ioreg_bst, BCM53XX_IOREG_PBASE, 496 BCM53XX_IOREG_SIZE, 0, &bcm53xx_ioreg_bsh); 497 if (error) 498 panic("%s: failed to map BCM53xx %s registers: %d", 499 __func__, "io", error); 500 501 bcm53xx_armcore_bsh = (bus_space_handle_t) iobase + BCM53XX_IOREG_SIZE; 502 error = bus_space_map(bcm53xx_armcore_bst, BCM53XX_ARMCORE_PBASE, 503 BCM53XX_ARMCORE_SIZE, 0, &bcm53xx_armcore_bsh); 504 if (error) 505 panic("%s: failed to map BCM53xx %s registers: %d", 506 __func__, "armcore", error); 507 508 curcpu()->ci_softc = &cpu_softc; 509 510 bcm53xx_get_chip_ioreg_state(&bcs, bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh); 511 bcm53xx_get_chip_armcore_state(&bcs, bcm53xx_armcore_bst, bcm53xx_armcore_bsh); 512 513 struct bcm53xx_clock_info * const clk = &cpu_softc.cpu_clk; 514 515 bcm53xx_clock_init(clk); 516 bcm53xx_lcpll_clock_init(clk, bcs.bcs_lcpll_control1, 517 bcs.bcs_lcpll_control2); 518 bcm53xx_genpll_clock_init(clk, bcs.bcs_genpll_control5, 519 bcs.bcs_genpll_control6, bcs.bcs_genpll_control7); 520 bcm53xx_usb_clock_init(clk, bcs.bcs_usb2_control); 521 bcm53xx_get_ddr_freq(clk, bcs.bcs_ddr_phy_ctl_pll_status, 522 bcs.bcs_ddr_phy_ctl_pll_dividers); 523 bcm53xx_get_cpu_freq(clk, bcs.bcs_armcore_clk_pllarma, 524 bcs.bcs_armcore_clk_pllarmb, bcs.bcs_armcore_clk_policy); 525 526 curcpu()->ci_data.cpu_cc_freq = clk->clk_cpu; 527 528 arml2cc_init(bcm53xx_armcore_bst, bcm53xx_armcore_bsh, ARMCORE_L2C_BASE); 529 } 530 531 void 532 bcm53xx_dma_bootstrap(psize_t memsize) 533 { 534 if (memsize <= 256*1024*1024) { 535 bcm53xx_dma_ranges[0].dr_len = memsize; 536 bcm53xx_coherent_dma_ranges[0].dr_len = memsize; 537 bcm53xx_dma_tag._nranges = 1; 538 bcm53xx_coherent_dma_tag._nranges = 1; 539 } else { 540 /* 541 * By setting up two ranges, bus_dmamem_alloc will always 542 * try to allocate from range 0 first resulting in allocations 543 * below 256MB which for PCI and GMAC are coherent. 544 */ 545 bcm53xx_dma_ranges[1].dr_len = memsize - 0x10000000; 546 bcm53xx_coherent_dma_ranges[1].dr_len = memsize - 0x10000000; 547 } 548 KASSERT(bcm53xx_dma_tag._ranges[0].dr_flags == 0); 549 KASSERT(bcm53xx_coherent_dma_tag._ranges[0].dr_flags == _BUS_DMAMAP_COHERENT); 550 #ifdef _ARM32_NEED_BUS_DMA_BOUNCE 551 KASSERT(bcm53xx_bounce_dma_tag._ranges[0].dr_flags == _BUS_DMAMAP_COHERENT); 552 #endif 553 } 554 555 #ifdef MULTIPROCESSOR 556 void 557 bcm53xx_cpu_hatch(struct cpu_info *ci) 558 { 559 a9tmr_init_cpu_clock(ci); 560 } 561 #endif 562 563 void 564 bcm53xx_device_register(device_t self, void *aux) 565 { 566 prop_dictionary_t dict = device_properties(self); 567 568 if (device_is_a(self, "armperiph") 569 && device_is_a(device_parent(self), "mainbus")) { 570 /* 571 * XXX KLUDGE ALERT XXX 572 * The iot mainbus supplies is completely wrong since it scales 573 * addresses by 2. The simpliest remedy is to replace with our 574 * bus space used for the armcore regisers (which armperiph uses). 575 */ 576 struct mainbus_attach_args * const mb = aux; 577 mb->mb_iot = bcm53xx_armcore_bst; 578 return; 579 } 580 581 /* 582 * We need to tell the A9 Global/Watchdog Timer 583 * what frequency it runs at. 584 */ 585 if (device_is_a(self, "a9tmr") || device_is_a(self, "a9wdt")) { 586 /* 587 * This clock always runs at (arm_clk div 2) and only goes 588 * to timers that are part of the A9 MP core subsystem. 589 */ 590 prop_dictionary_set_uint32(dict, "frequency", 591 cpu_softc.cpu_clk.clk_cpu / 2); 592 return; 593 } 594 595 if (device_is_a(self, "bcmeth")) { 596 const struct bcmccb_attach_args * const ccbaa = aux; 597 const uint8_t enaddr[ETHER_ADDR_LEN] = { 598 0x00, 0x01, 0x02, 0x03, 0x04, 599 0x05 + 2 * ccbaa->ccbaa_loc.loc_port, 600 }; 601 prop_data_t pd = prop_data_create_data(enaddr, ETHER_ADDR_LEN); 602 KASSERT(pd != NULL); 603 if (prop_dictionary_set(device_properties(self), "mac-address", pd) == false) { 604 printf("WARNING: Unable to set mac-address property for %s\n", device_xname(self)); 605 } 606 prop_object_release(pd); 607 } 608 } 609 610 static kmutex_t srab_lock __cacheline_aligned; 611 612 void 613 bcm53xx_srab_init(void) 614 { 615 mutex_init(&srab_lock, MUTEX_DEFAULT, IPL_VM); 616 617 bcm53xx_srab_write_4(0x0079, 0x90); // reset switch 618 for (u_int port = 0; port < 8; port++) { 619 /* per port control: no stp */ 620 bcm53xx_srab_write_4(port, 0x00); 621 } 622 bcm53xx_srab_write_4(0x0008, 0x1c); // IMP port (enab UC/MC/BC) 623 bcm53xx_srab_write_4(0x000e, 0xbb); // IMP port force-link 1G 624 bcm53xx_srab_write_4(0x005d, 0x7b); // port5 force-link 1G 625 bcm53xx_srab_write_4(0x005f, 0x7b); // port7 force-link 1G 626 bcm53xx_srab_write_4(0x000b, 0x7); // management mode 627 bcm53xx_srab_write_4(0x0203, 0x0); // disable BRCM tag 628 bcm53xx_srab_write_4(0x0200, 0x80); // enable IMP=port8 629 } 630 631 static inline void 632 bcm53xx_srab_busywait(bus_space_tag_t bst, bus_space_handle_t bsh) 633 { 634 while (bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT) & SRA_GORDYN) { 635 delay(10); 636 } 637 } 638 639 uint32_t 640 bcm53xx_srab_read_4(u_int pageoffset) 641 { 642 bus_space_tag_t bst = bcm53xx_ioreg_bst; 643 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 644 uint32_t rv; 645 646 mutex_spin_enter(&srab_lock); 647 648 bcm53xx_srab_busywait(bst, bsh); 649 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT, 650 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_GORDYN); 651 bcm53xx_srab_busywait(bst, bsh); 652 rv = bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDL); 653 654 mutex_spin_exit(&srab_lock); 655 return rv; 656 } 657 658 uint64_t 659 bcm53xx_srab_read_8(u_int pageoffset) 660 { 661 bus_space_tag_t bst = bcm53xx_ioreg_bst; 662 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 663 uint64_t rv; 664 665 mutex_spin_enter(&srab_lock); 666 667 bcm53xx_srab_busywait(bst, bsh); 668 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT, 669 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_GORDYN); 670 bcm53xx_srab_busywait(bst, bsh); 671 rv = bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDH); 672 rv <<= 32; 673 rv |= bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDL); 674 675 mutex_spin_exit(&srab_lock); 676 return rv; 677 } 678 679 void 680 bcm53xx_srab_write_4(u_int pageoffset, uint32_t val) 681 { 682 bus_space_tag_t bst = bcm53xx_ioreg_bst; 683 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 684 685 mutex_spin_enter(&srab_lock); 686 687 bcm53xx_srab_busywait(bst, bsh); 688 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDL, val); 689 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT, 690 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_WRITE | SRA_GORDYN); 691 bcm53xx_srab_busywait(bst, bsh); 692 693 mutex_spin_exit(&srab_lock); 694 } 695 696 void 697 bcm53xx_srab_write_8(u_int pageoffset, uint64_t val) 698 { 699 bus_space_tag_t bst = bcm53xx_ioreg_bst; 700 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 701 702 mutex_spin_enter(&srab_lock); 703 704 bcm53xx_srab_busywait(bst, bsh); 705 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDL, val); 706 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDH, val >> 32); 707 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT, 708 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_WRITE | SRA_GORDYN); 709 bcm53xx_srab_busywait(bst, bsh); 710 mutex_spin_exit(&srab_lock); 711 } 712
Indexes created Mon Sep 29 21:09:56 GMT 2025