bcm53xx_board.c revision 1.8.4.3
1 /* $NetBSD: bcm53xx_board.c,v 1.8.4.3 2013/02/07 06:51:48 matt Exp $ */ 2 /*- 3 * Copyright (c) 2012 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas of 3am Software Foundry. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "opt_broadcom.h" 32 33 #define _ARM32_BUS_DMA_PRIVATE 34 35 #include <sys/cdefs.h> 36 37 __KERNEL_RCSID(1, "$NetBSD: bcm53xx_board.c,v 1.8.4.3 2013/02/07 06:51:48 matt Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/bus.h> 41 #include <sys/cpu.h> 42 #include <sys/device.h> 43 44 #include <prop/proplib.h> 45 46 #include <net/if.h> 47 #include <net/if_ether.h> 48 49 #define CRU_PRIVATE 50 #define DDR_PRIVATE 51 #define DMU_PRIVATE 52 #define ARMCORE_PRIVATE 53 #define SRAB_PRIVATE 54 55 #include <arm/cortex/a9tmr_var.h> 56 #include <arm/cortex/pl310_var.h> 57 #include <arm/mainbus/mainbus.h> 58 59 #include <arm/broadcom/bcm53xx_reg.h> 60 #include <arm/broadcom/bcm53xx_var.h> 61 62 bus_space_tag_t bcm53xx_ioreg_bst = &bcmgen_bs_tag; 63 bus_space_handle_t bcm53xx_ioreg_bsh; 64 bus_space_tag_t bcm53xx_armcore_bst = &bcmgen_bs_tag; 65 bus_space_handle_t bcm53xx_armcore_bsh; 66 67 static struct cpu_softc cpu_softc; 68 69 struct arm32_dma_range bcm53xx_dma_ranges[2] = { 70 [0] = { 71 .dr_sysbase = 0x80000000, 72 .dr_busbase = 0x80000000, 73 .dr_len = 0x10000000, 74 }, [1] = { 75 .dr_sysbase = 0x90000000, 76 .dr_busbase = 0x90000000, 77 }, 78 }; 79 80 struct arm32_bus_dma_tag bcm53xx_dma_tag = { 81 ._ranges = bcm53xx_dma_ranges, 82 ._nranges = __arraycount(bcm53xx_dma_ranges), 83 _BUS_DMAMAP_FUNCS, 84 _BUS_DMAMEM_FUNCS, 85 _BUS_DMATAG_FUNCS, 86 }; 87 88 struct arm32_dma_range bcm53xx_coherent_dma_ranges[2] = { 89 [0] = { 90 .dr_sysbase = 0x80000000, 91 .dr_busbase = 0x80000000, 92 .dr_len = 0x10000000, 93 .dr_flags = _BUS_DMAMAP_COHERENT, 94 }, [1] = { 95 .dr_sysbase = 0x90000000, 96 .dr_busbase = 0x90000000, 97 }, 98 }; 99 100 struct arm32_bus_dma_tag bcm53xx_coherent_dma_tag = { 101 ._ranges = bcm53xx_coherent_dma_ranges, 102 ._nranges = __arraycount(bcm53xx_coherent_dma_ranges), 103 _BUS_DMAMAP_FUNCS, 104 _BUS_DMAMEM_FUNCS, 105 _BUS_DMATAG_FUNCS, 106 }; 107 108 #ifdef BCM53XX_CONSOLE_EARLY 109 #include <dev/ic/ns16550reg.h> 110 #include <dev/ic/comreg.h> 111 #include <dev/cons.h> 112 113 static vaddr_t com_base; 114 115 static inline uint32_t 116 uart_read(bus_size_t o) 117 { 118 return *(volatile uint8_t *)(com_base + o); 119 } 120 121 static inline void 122 uart_write(bus_size_t o, uint32_t v) 123 { 124 *(volatile uint8_t *)(com_base + o) = v; 125 } 126 127 static int 128 bcm53xx_cngetc(dev_t dv) 129 { 130 if ((uart_read(com_lsr) & LSR_RXRDY) == 0) 131 return -1; 132 133 return uart_read(com_data) & 0xff; 134 } 135 136 static void 137 bcm53xx_cnputc(dev_t dv, int c) 138 { 139 int timo = 150000; 140 141 while ((uart_read(com_lsr) & LSR_TXRDY) == 0 && --timo > 0) 142 ; 143 144 uart_write(com_data, c); 145 146 timo = 150000; 147 while ((uart_read(com_lsr) & LSR_TSRE) == 0 && --timo > 0) 148 ; 149 } 150 151 static struct consdev bcm53xx_earlycons = { 152 .cn_putc = bcm53xx_cnputc, 153 .cn_getc = bcm53xx_cngetc, 154 .cn_pollc = nullcnpollc, 155 }; 156 #endif /* BCM53XX_CONSOLE_EARLY */ 157 158 psize_t 159 bcm53xx_memprobe(void) 160 { 161 bus_space_tag_t bst = bcm53xx_ioreg_bst; 162 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 163 164 /* 165 * First, let's read the magic DDR registers! 166 */ 167 const uint32_t v01 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_01); 168 const uint32_t v82 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_82); 169 const uint32_t v86 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_86); 170 const uint32_t v87 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_87); 171 172 /* 173 * Calculate chip parameters 174 * */ 175 const u_int rows = __SHIFTOUT(v01, CTL_01_MAX_ROW) 176 - __SHIFTOUT(v82, CTL_82_ROW_DIFF); 177 const u_int cols = __SHIFTOUT(v01, CTL_01_MAX_COL) 178 - __SHIFTOUT(v82, CTL_82_COL_DIFF); 179 const u_int banks_log2 = 3 - __SHIFTOUT(v82, CTL_82_BANK_DIFF); 180 181 /* 182 * For each chip select, increase the chip count if if is enabled. 183 */ 184 const u_int max_chips = __SHIFTOUT(v01, CTL_01_MAX_CHIP_SEL); 185 u_int cs_map = __SHIFTOUT(v86, CTL_86_CS_MAP); 186 u_int chips = 0; 187 188 for (u_int i = 0; cs_map != 0 && i < max_chips; i++, cs_map >>= 1) { 189 chips += (cs_map & 1); 190 } 191 192 /* get log2(ddr width) */ 193 194 const u_int ddr_width_log2 = (v87 & CTL_87_REDUC) ? 1 : 2; 195 196 /* 197 * Let's add up all the things that contribute to the size of a chip. 198 */ 199 const u_int chip_size_log2 = cols + rows + banks_log2 + ddr_width_log2; 200 201 /* 202 * Now our memory size is simply the number of chip shifted by the 203 * log2(chip_size). 204 */ 205 return (psize_t) chips << chip_size_log2; 206 } 207 208 static inline uint32_t 209 bcm53xx_freq_calc(struct bcm53xx_clock_info *clk, 210 uint32_t pdiv, uint32_t ndiv_int, uint32_t ndiv_frac) 211 { 212 if (ndiv_frac == 0 && pdiv == 1) 213 return ndiv_int * clk->clk_ref; 214 215 uint64_t freq64 = ((uint64_t)ndiv_int << 30) + ndiv_frac; 216 freq64 *= clk->clk_ref; 217 if (pdiv > 1) 218 freq64 /= pdiv; 219 return (uint32_t) (freq64 >> 30); 220 } 221 222 static uint32_t 223 bcm53xx_value_wrap(uint32_t value, uint32_t mask) 224 { 225 /* 226 * n is n except when n is 0 then n = mask + 1. 227 */ 228 return ((__SHIFTOUT(value, mask) - 1) & __SHIFTOUT(mask, mask)) + 1; 229 } 230 231 static void 232 bcm53xx_genpll_clock_init(struct bcm53xx_clock_info *clk, uint32_t control5, 233 uint32_t control6, uint32_t control7) 234 { 235 const uint32_t pdiv = bcm53xx_value_wrap(control6, 236 GENPLL_CONTROL6_PDIV); 237 const uint32_t ndiv_int = bcm53xx_value_wrap(control5, 238 GENPLL_CONTROL5_NDIV_INT); 239 const uint32_t ndiv_frac = __SHIFTOUT(control5, 240 GENPLL_CONTROL5_NDIV_FRAC); 241 242 clk->clk_genpll = bcm53xx_freq_calc(clk, pdiv, ndiv_int, ndiv_frac); 243 244 const uint32_t ch0_mdiv = bcm53xx_value_wrap(control6, 245 GENPLL_CONTROL6_CH0_MDIV); 246 const uint32_t ch1_mdiv = bcm53xx_value_wrap(control6, 247 GENPLL_CONTROL6_CH1_MDIV); 248 const uint32_t ch2_mdiv = bcm53xx_value_wrap(control6, 249 GENPLL_CONTROL6_CH2_MDIV); 250 const uint32_t ch3_mdiv = bcm53xx_value_wrap(control7, 251 GENPLL_CONTROL7_CH3_MDIV); 252 253 clk->clk_mac = clk->clk_genpll / ch0_mdiv; // GENPLL CH0 254 clk->clk_robo = clk->clk_genpll / ch1_mdiv; // GENPLL CH1 255 clk->clk_usb2 = clk->clk_genpll / ch2_mdiv; // GENPLL CH2 256 clk->clk_iproc = clk->clk_genpll / ch3_mdiv; // GENPLL CH3 257 } 258 259 static void 260 bcm53xx_lcpll_clock_init(struct bcm53xx_clock_info *clk, uint32_t control1, 261 uint32_t control2) 262 { 263 const uint32_t pdiv = bcm53xx_value_wrap(control1, 264 LCPLL_CONTROL1_PDIV); 265 const uint32_t ndiv_int = bcm53xx_value_wrap(control1, 266 LCPLL_CONTROL1_NDIV_INT); 267 const uint32_t ndiv_frac = __SHIFTOUT(control1, 268 LCPLL_CONTROL1_NDIV_FRAC); 269 270 clk->clk_lcpll = bcm53xx_freq_calc(clk, pdiv, ndiv_int, ndiv_frac); 271 272 const uint32_t ch0_mdiv = bcm53xx_value_wrap(control2, 273 LCPLL_CONTROL2_CH0_MDIV); 274 const uint32_t ch1_mdiv = bcm53xx_value_wrap(control2, 275 LCPLL_CONTROL2_CH1_MDIV); 276 const uint32_t ch2_mdiv = bcm53xx_value_wrap(control2, 277 LCPLL_CONTROL2_CH2_MDIV); 278 const uint32_t ch3_mdiv = bcm53xx_value_wrap(control2, 279 LCPLL_CONTROL2_CH3_MDIV); 280 281 clk->clk_pcie_ref = clk->clk_lcpll / ch0_mdiv; // LCPLL CH0 282 clk->clk_sdio = clk->clk_lcpll / ch1_mdiv; // LCPLL CH1 283 clk->clk_ddr_ref = clk->clk_lcpll / ch2_mdiv; // LCPLL CH2 284 clk->clk_axi = clk->clk_lcpll / ch3_mdiv; // LCPLL CH3 285 } 286 287 static void 288 bcm53xx_usb_clock_init(struct bcm53xx_clock_info *clk, uint32_t usb2_control) 289 { 290 const uint32_t pdiv = bcm53xx_value_wrap(usb2_control, 291 USB2_CONTROL_PDIV); 292 const uint32_t ndiv = bcm53xx_value_wrap(usb2_control, 293 USB2_CONTROL_NDIV_INT); 294 295 uint32_t usb_ref = (clk->clk_usb2 / pdiv) * ndiv; 296 if (usb_ref != USB2_REF_CLK) { 297 /* 298 * USB Reference Clock isn't 1.92GHz. So we need to modify 299 * USB2_CONTROL to produce it. 300 */ 301 uint32_t new_ndiv = (USB2_REF_CLK / clk->clk_usb2) * pdiv; 302 usb2_control &= ~USB2_CONTROL_NDIV_INT; 303 usb2_control |= __SHIFTIN(new_ndiv, USB2_CONTROL_NDIV_INT); 304 305 // Allow Clocks to be modified 306 bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh, 307 CRU_BASE + CRU_CLKSET_KEY, CRU_CLKSET_KEY_MAGIC); 308 309 // Update USB2 clock generator 310 bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh, 311 CRU_BASE + CRU_USB2_CONTROL, usb2_control); 312 313 // Prevent Clock modification 314 bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh, 315 CRU_BASE + CRU_CLKSET_KEY, 0); 316 317 usb_ref = (clk->clk_usb2 / pdiv) * new_ndiv; 318 } 319 320 clk->clk_usb_ref = usb_ref; 321 } 322 323 324 static void 325 bcm53xx_clock_init(struct bcm53xx_clock_info *clk) 326 { 327 clk->clk_ref = BCM53XX_REF_CLK; 328 clk->clk_sys = 8*clk->clk_ref; 329 } 330 331 /* 332 * F(ddr) = ((1 / pdiv) * ndiv * CH2) / (post_div * 2) 333 */ 334 static void 335 bcm53xx_get_ddr_freq(struct bcm53xx_clock_info *clk, uint32_t pll_status, 336 uint32_t pll_dividers) 337 { 338 const bool clocking_4x = (pll_status & PLL_STATUS_CLOCKING_4X) != 0; 339 u_int post_div = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_POST_DIV); 340 u_int pdiv = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_PDIV); 341 u_int ndiv = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_NDIV); 342 343 pdiv = ((pdiv - (clocking_4x ? 1 : 5)) & 7) + 1; 344 345 clk->clk_ddr_mhz = __SHIFTOUT(pll_status, PLL_STATUS_MHZ); 346 clk->clk_ddr = (clk->clk_ddr_ref / pdiv) * ndiv / (2 + post_div); 347 } 348 349 /* 350 * CPU_CLK = (1 / pdiv) * (ndiv_int + (ndiv_frac / 0x40000000)) x F(ref) 351 */ 352 static void 353 bcm53xx_get_cpu_freq(struct bcm53xx_clock_info *clk, 354 uint32_t pllarma, uint32_t pllarmb, uint32_t policy) 355 { 356 policy = __SHIFTOUT(policy, CLK_POLICY_FREQ_POLICY2); 357 358 if (policy == CLK_POLICY_REF_CLK) { 359 clk->clk_cpu = clk->clk_ref; 360 clk->clk_apb = clk->clk_cpu; 361 return; 362 } 363 364 if (policy == CLK_POLICY_SYS_CLK) { 365 clk->clk_cpu = clk->clk_sys; 366 clk->clk_apb = clk->clk_cpu / 4; 367 return; 368 } 369 370 const u_int pdiv = bcm53xx_value_wrap(pllarma, CLK_PLLARMA_PDIV); 371 const u_int ndiv_int = bcm53xx_value_wrap(pllarma, CLK_PLLARMA_NDIV_INT); 372 const u_int ndiv_frac = __SHIFTOUT(pllarmb, CLK_PLLARMB_NDIV_FRAC); 373 // const u_int apb_clk_div = __SHIFTOUT(apb_clk_div, CLK_APB_DIV_VALUE)+1; 374 375 const u_int cpu_div = (policy == CLK_POLICY_ARM_PLL_CH0) ? 4 : 2; 376 377 clk->clk_cpu = bcm53xx_freq_calc(clk, pdiv, ndiv_int, ndiv_frac) / cpu_div; 378 clk->clk_apb = clk->clk_cpu / 4; 379 } 380 381 struct bcm53xx_chip_state { 382 uint32_t bcs_lcpll_control1; 383 uint32_t bcs_lcpll_control2; 384 385 uint32_t bcs_genpll_control5; 386 uint32_t bcs_genpll_control6; 387 uint32_t bcs_genpll_control7; 388 389 uint32_t bcs_usb2_control; 390 391 uint32_t bcs_ddr_phy_ctl_pll_status; 392 uint32_t bcs_ddr_phy_ctl_pll_dividers; 393 394 uint32_t bcs_armcore_clk_policy; 395 uint32_t bcs_armcore_clk_pllarma; 396 uint32_t bcs_armcore_clk_pllarmb; 397 }; 398 399 static void 400 bcm53xx_get_chip_ioreg_state(struct bcm53xx_chip_state *bcs, 401 bus_space_tag_t bst, bus_space_handle_t bsh) 402 { 403 bcs->bcs_lcpll_control1 = bus_space_read_4(bst, bsh, 404 DMU_BASE + DMU_LCPLL_CONTROL1); 405 bcs->bcs_lcpll_control2 = bus_space_read_4(bst, bsh, 406 DMU_BASE + DMU_LCPLL_CONTROL2); 407 408 bcs->bcs_genpll_control5 = bus_space_read_4(bst, bsh, 409 CRU_BASE + CRU_GENPLL_CONTROL5); 410 bcs->bcs_genpll_control6 = bus_space_read_4(bst, bsh, 411 CRU_BASE + CRU_GENPLL_CONTROL6); 412 bcs->bcs_genpll_control7 = bus_space_read_4(bst, bsh, 413 CRU_BASE + CRU_GENPLL_CONTROL7); 414 415 bcs->bcs_usb2_control = bus_space_read_4(bst, bsh, 416 CRU_BASE + CRU_USB2_CONTROL); 417 418 bcs->bcs_ddr_phy_ctl_pll_status = bus_space_read_4(bst, bsh, 419 DDR_BASE + DDR_PHY_CTL_PLL_STATUS); 420 bcs->bcs_ddr_phy_ctl_pll_dividers = bus_space_read_4(bst, bsh, 421 DDR_BASE + DDR_PHY_CTL_PLL_DIVIDERS); 422 } 423 424 static void 425 bcm53xx_get_chip_armcore_state(struct bcm53xx_chip_state *bcs, 426 bus_space_tag_t bst, bus_space_handle_t bsh) 427 { 428 bcs->bcs_armcore_clk_policy = bus_space_read_4(bst, bsh, 429 ARMCORE_CLK_POLICY_FREQ); 430 bcs->bcs_armcore_clk_pllarma = bus_space_read_4(bst, bsh, 431 ARMCORE_CLK_PLLARMA); 432 bcs->bcs_armcore_clk_pllarmb = bus_space_read_4(bst, bsh, 433 ARMCORE_CLK_PLLARMB); 434 } 435 436 void 437 bcm53xx_cpu_softc_init(struct cpu_info *ci) 438 { 439 struct cpu_softc * const cpu = ci->ci_softc; 440 441 cpu->cpu_ioreg_bst = bcm53xx_ioreg_bst; 442 cpu->cpu_ioreg_bsh = bcm53xx_ioreg_bsh; 443 444 cpu->cpu_armcore_bst = bcm53xx_armcore_bst; 445 cpu->cpu_armcore_bsh = bcm53xx_armcore_bsh; 446 } 447 448 void 449 bcm53xx_print_clocks(void) 450 { 451 #if defined(VERBOSE_ARM_INIT) 452 const struct bcm53xx_clock_info * const clk = &cpu_softc.cpu_clk; 453 printf("ref clk = %u (%#x)\n", clk->clk_ref, clk->clk_ref); 454 printf("sys clk = %u (%#x)\n", clk->clk_sys, clk->clk_sys); 455 printf("lcpll clk = %u (%#x)\n", clk->clk_lcpll, clk->clk_lcpll); 456 printf("pcie ref clk = %u (%#x) [CH0]\n", clk->clk_pcie_ref, clk->clk_pcie_ref); 457 printf("sdio clk = %u (%#x) [CH1]\n", clk->clk_sdio, clk->clk_sdio); 458 printf("ddr ref clk = %u (%#x) [CH2]\n", clk->clk_ddr_ref, clk->clk_ddr_ref); 459 printf("axi clk = %u (%#x) [CH3]\n", clk->clk_axi, clk->clk_axi); 460 printf("genpll clk = %u (%#x)\n", clk->clk_genpll, clk->clk_genpll); 461 printf("mac clk = %u (%#x) [CH0]\n", clk->clk_mac, clk->clk_mac); 462 printf("robo clk = %u (%#x) [CH1]\n", clk->clk_robo, clk->clk_robo); 463 printf("usb2 clk = %u (%#x) [CH2]\n", clk->clk_usb2, clk->clk_usb2); 464 printf("iproc clk = %u (%#x) [CH3]\n", clk->clk_iproc, clk->clk_iproc); 465 printf("ddr clk = %u (%#x)\n", clk->clk_ddr, clk->clk_ddr); 466 printf("ddr mhz = %u (%#x)\n", clk->clk_ddr_mhz, clk->clk_ddr_mhz); 467 printf("cpu clk = %u (%#x)\n", clk->clk_cpu, clk->clk_cpu); 468 printf("apb clk = %u (%#x)\n", clk->clk_apb, clk->clk_apb); 469 printf("usb ref clk = %u (%#x)\n", clk->clk_usb_ref, clk->clk_usb_ref); 470 #endif 471 } 472 473 void 474 bcm53xx_bootstrap(vaddr_t iobase) 475 { 476 struct bcm53xx_chip_state bcs; 477 int error; 478 479 #ifdef BCM53XX_CONSOLE_EARLY 480 com_base = iobase + CCA_UART0_BASE; 481 cn_tab = &bcm53xx_earlycons; 482 #endif 483 484 bcm53xx_ioreg_bsh = (bus_space_handle_t) iobase; 485 error = bus_space_map(bcm53xx_ioreg_bst, BCM53XX_IOREG_PBASE, 486 BCM53XX_IOREG_SIZE, 0, &bcm53xx_ioreg_bsh); 487 if (error) 488 panic("%s: failed to map BCM53xx %s registers: %d", 489 __func__, "io", error); 490 491 bcm53xx_armcore_bsh = (bus_space_handle_t) iobase + BCM53XX_IOREG_SIZE; 492 error = bus_space_map(bcm53xx_armcore_bst, BCM53XX_ARMCORE_PBASE, 493 BCM53XX_ARMCORE_SIZE, 0, &bcm53xx_armcore_bsh); 494 if (error) 495 panic("%s: failed to map BCM53xx %s registers: %d", 496 __func__, "armcore", error); 497 498 curcpu()->ci_softc = &cpu_softc; 499 500 bcm53xx_get_chip_ioreg_state(&bcs, bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh); 501 bcm53xx_get_chip_armcore_state(&bcs, bcm53xx_armcore_bst, bcm53xx_armcore_bsh); 502 503 struct bcm53xx_clock_info * const clk = &cpu_softc.cpu_clk; 504 505 bcm53xx_clock_init(clk); 506 bcm53xx_lcpll_clock_init(clk, bcs.bcs_lcpll_control1, 507 bcs.bcs_lcpll_control2); 508 bcm53xx_genpll_clock_init(clk, bcs.bcs_genpll_control5, 509 bcs.bcs_genpll_control6, bcs.bcs_genpll_control7); 510 bcm53xx_usb_clock_init(clk, bcs.bcs_usb2_control); 511 bcm53xx_get_ddr_freq(clk, bcs.bcs_ddr_phy_ctl_pll_status, 512 bcs.bcs_ddr_phy_ctl_pll_dividers); 513 bcm53xx_get_cpu_freq(clk, bcs.bcs_armcore_clk_pllarma, 514 bcs.bcs_armcore_clk_pllarmb, bcs.bcs_armcore_clk_policy); 515 516 curcpu()->ci_data.cpu_cc_freq = clk->clk_cpu; 517 518 arml2cc_init(bcm53xx_armcore_bst, bcm53xx_armcore_bsh, ARMCORE_L2C_BASE); 519 } 520 521 void 522 bcm53xx_dma_bootstrap(psize_t memsize) 523 { 524 if (memsize > 256*1024*1024) { 525 /* 526 * By setting up two ranges, bus_dmamem_alloc will always 527 * try to allocate from range 0 first resulting in allocations 528 * below 256MB which for PCI and GMAC are coherent. 529 */ 530 bcm53xx_dma_ranges[1].dr_len = memsize - 0x10000000; 531 bcm53xx_coherent_dma_ranges[1].dr_len = memsize - 0x10000000; 532 } else { 533 bcm53xx_dma_ranges[0].dr_len = memsize; 534 bcm53xx_coherent_dma_ranges[0].dr_len = memsize; 535 bcm53xx_dma_tag._nranges = 1; 536 bcm53xx_coherent_dma_tag._nranges = 1; 537 } 538 KASSERT(bcm53xx_dma_tag._ranges[0].dr_flags == 0); 539 KASSERT(bcm53xx_coherent_dma_tag._ranges[0].dr_flags == _BUS_DMAMAP_COHERENT); 540 } 541 542 #ifdef MULTIPROCESSOR 543 void 544 bcm53xx_cpu_hatch(struct cpu_info *ci) 545 { 546 a9tmr_init_cpu_clock(ci); 547 } 548 #endif 549 550 void 551 bcm53xx_device_register(device_t self, void *aux) 552 { 553 prop_dictionary_t dict = device_properties(self); 554 555 if (device_is_a(self, "armperiph") 556 && device_is_a(device_parent(self), "mainbus")) { 557 /* 558 * XXX KLUDGE ALERT XXX 559 * The iot mainbus supplies is completely wrong since it scales 560 * addresses by 2. The simpliest remedy is to replace with our 561 * bus space used for the armcore regisers (which armperiph uses). 562 */ 563 struct mainbus_attach_args * const mb = aux; 564 mb->mb_iot = bcm53xx_armcore_bst; 565 return; 566 } 567 568 /* 569 * We need to tell the A9 Global/Watchdog Timer 570 * what frequency it runs at. 571 */ 572 if (device_is_a(self, "a9tmr") || device_is_a(self, "a9wdt")) { 573 /* 574 * This clock always runs at (arm_clk div 2) and only goes 575 * to timers that are part of the A9 MP core subsystem. 576 */ 577 prop_dictionary_set_uint32(dict, "frequency", 578 cpu_softc.cpu_clk.clk_cpu / 2); 579 return; 580 } 581 582 if (device_is_a(self, "bcmeth")) { 583 const struct bcmccb_attach_args * const ccbaa = aux; 584 const uint8_t enaddr[ETHER_ADDR_LEN] = { 585 0x00, 0x01, 0x02, 0x03, 0x04, 586 0x05 + 2 * ccbaa->ccbaa_loc.loc_port, 587 }; 588 prop_data_t pd = prop_data_create_data(enaddr, ETHER_ADDR_LEN); 589 KASSERT(pd != NULL); 590 if (prop_dictionary_set(device_properties(self), "mac-address", pd) == false) { 591 printf("WARNING: Unable to set mac-address property for %s\n", device_xname(self)); 592 } 593 prop_object_release(pd); 594 } 595 } 596 597 static kmutex_t srab_lock __cacheline_aligned; 598 599 void 600 bcm53xx_srab_init(void) 601 { 602 mutex_init(&srab_lock, MUTEX_DEFAULT, IPL_VM); 603 604 bcm53xx_srab_write_4(0x0079, 0x90); // reset switch 605 for (u_int port = 0; port < 8; port++) { 606 /* per port control: no stp */ 607 bcm53xx_srab_write_4(port, 0x00); 608 } 609 bcm53xx_srab_write_4(0x0008, 0x1c); // IMP port (enab UC/MC/BC) 610 bcm53xx_srab_write_4(0x000e, 0xbb); // IMP port force-link 1G 611 bcm53xx_srab_write_4(0x005d, 0x7b); // port5 force-link 1G 612 bcm53xx_srab_write_4(0x005f, 0x7b); // port7 force-link 1G 613 bcm53xx_srab_write_4(0x000b, 0x7); // management mode 614 bcm53xx_srab_write_4(0x0203, 0x0); // disable BRCM tag 615 bcm53xx_srab_write_4(0x0200, 0x80); // enable IMP=port8 616 } 617 618 static inline void 619 bcm53xx_srab_busywait(bus_space_tag_t bst, bus_space_handle_t bsh) 620 { 621 while (bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT) & SRA_GORDYN) { 622 delay(10); 623 } 624 } 625 626 uint32_t 627 bcm53xx_srab_read_4(u_int pageoffset) 628 { 629 bus_space_tag_t bst = bcm53xx_ioreg_bst; 630 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 631 uint32_t rv; 632 633 mutex_spin_enter(&srab_lock); 634 635 bcm53xx_srab_busywait(bst, bsh); 636 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT, 637 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_GORDYN); 638 bcm53xx_srab_busywait(bst, bsh); 639 rv = bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDL); 640 641 mutex_spin_exit(&srab_lock); 642 return rv; 643 } 644 645 uint64_t 646 bcm53xx_srab_read_8(u_int pageoffset) 647 { 648 bus_space_tag_t bst = bcm53xx_ioreg_bst; 649 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 650 uint64_t rv; 651 652 mutex_spin_enter(&srab_lock); 653 654 bcm53xx_srab_busywait(bst, bsh); 655 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT, 656 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_GORDYN); 657 bcm53xx_srab_busywait(bst, bsh); 658 rv = bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDH); 659 rv <<= 32; 660 rv |= bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDL); 661 662 mutex_spin_exit(&srab_lock); 663 return rv; 664 } 665 666 void 667 bcm53xx_srab_write_4(u_int pageoffset, uint32_t val) 668 { 669 bus_space_tag_t bst = bcm53xx_ioreg_bst; 670 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 671 672 mutex_spin_enter(&srab_lock); 673 674 bcm53xx_srab_busywait(bst, bsh); 675 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDL, val); 676 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT, 677 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_WRITE | SRA_GORDYN); 678 bcm53xx_srab_busywait(bst, bsh); 679 680 mutex_spin_exit(&srab_lock); 681 } 682 683 void 684 bcm53xx_srab_write_8(u_int pageoffset, uint64_t val) 685 { 686 bus_space_tag_t bst = bcm53xx_ioreg_bst; 687 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 688 689 mutex_spin_enter(&srab_lock); 690 691 bcm53xx_srab_busywait(bst, bsh); 692 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDL, val); 693 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDH, val >> 32); 694 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT, 695 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_WRITE | SRA_GORDYN); 696 bcm53xx_srab_busywait(bst, bsh); 697 mutex_spin_exit(&srab_lock); 698 } 699
Indexes created Fri Oct 17 00:09:41 GMT 2025