bcm53xx_board.c revision 1.8.4.5
1 /* $NetBSD: bcm53xx_board.c,v 1.8.4.5 2013/02/19 02:22:02 matt Exp $ */ 2 /*- 3 * Copyright (c) 2012 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas of 3am Software Foundry. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "opt_broadcom.h" 32 33 #define _ARM32_BUS_DMA_PRIVATE 34 35 #include <sys/cdefs.h> 36 37 __KERNEL_RCSID(1, "$NetBSD: bcm53xx_board.c,v 1.8.4.5 2013/02/19 02:22:02 matt Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/bus.h> 41 #include <sys/cpu.h> 42 #include <sys/device.h> 43 44 #include <prop/proplib.h> 45 46 #include <net/if.h> 47 #include <net/if_ether.h> 48 49 #define CRU_PRIVATE 50 #define DDR_PRIVATE 51 #define DMU_PRIVATE 52 #define ARMCORE_PRIVATE 53 #define SRAB_PRIVATE 54 55 #include <arm/cortex/a9tmr_var.h> 56 #include <arm/cortex/pl310_var.h> 57 #include <arm/mainbus/mainbus.h> 58 59 #include <arm/broadcom/bcm53xx_reg.h> 60 #include <arm/broadcom/bcm53xx_var.h> 61 62 bus_space_tag_t bcm53xx_ioreg_bst = &bcmgen_bs_tag; 63 bus_space_handle_t bcm53xx_ioreg_bsh; 64 bus_space_tag_t bcm53xx_armcore_bst = &bcmgen_bs_tag; 65 bus_space_handle_t bcm53xx_armcore_bsh; 66 67 static struct cpu_softc cpu_softc; 68 69 struct arm32_dma_range bcm53xx_dma_ranges[] = { 70 [0] = { 71 .dr_sysbase = 0x80000000, 72 .dr_busbase = 0x80000000, 73 .dr_len = 0x10000000, 74 }, [1] = { 75 .dr_sysbase = 0x90000000, 76 .dr_busbase = 0x90000000, 77 }, 78 }; 79 80 struct arm32_bus_dma_tag bcm53xx_dma_tag = { 81 ._ranges = bcm53xx_dma_ranges, 82 ._nranges = __arraycount(bcm53xx_dma_ranges), 83 _BUS_DMAMAP_FUNCS, 84 _BUS_DMAMEM_FUNCS, 85 _BUS_DMATAG_FUNCS, 86 }; 87 88 struct arm32_dma_range bcm53xx_coherent_dma_ranges[] = { 89 [0] = { 90 .dr_sysbase = 0x80000000, 91 .dr_busbase = 0x80000000, 92 .dr_len = 0x10000000, 93 .dr_flags = _BUS_DMAMAP_COHERENT, 94 }, [1] = { 95 .dr_sysbase = 0x90000000, 96 .dr_busbase = 0x90000000, 97 }, 98 }; 99 100 struct arm32_bus_dma_tag bcm53xx_coherent_dma_tag = { 101 ._ranges = bcm53xx_coherent_dma_ranges, 102 ._nranges = __arraycount(bcm53xx_coherent_dma_ranges), 103 _BUS_DMAMAP_FUNCS, 104 _BUS_DMAMEM_FUNCS, 105 _BUS_DMATAG_FUNCS, 106 }; 107 108 #ifdef _ARM32_NEED_BUS_DMA_BOUNCE 109 struct arm32_dma_range bcm53xx_bounce_dma_ranges[] = { 110 [0] = { 111 .dr_sysbase = 0x80000000, 112 .dr_busbase = 0x80000000, 113 .dr_len = 0x10000000, 114 .dr_flags = _BUS_DMAMAP_COHERENT, 115 }, 116 }; 117 118 struct arm32_bus_dma_tag bcm53xx_bounce_dma_tag = { 119 ._ranges = bcm53xx_bounce_dma_ranges, 120 ._nranges = __arraycount(bcm53xx_bounce_dma_ranges), 121 _BUS_DMAMAP_FUNCS, 122 _BUS_DMAMEM_FUNCS, 123 _BUS_DMATAG_FUNCS, 124 }; 125 #endif 126 127 #ifdef BCM53XX_CONSOLE_EARLY 128 #include <dev/ic/ns16550reg.h> 129 #include <dev/ic/comreg.h> 130 #include <dev/cons.h> 131 132 static vaddr_t com_base; 133 134 static inline uint32_t 135 uart_read(bus_size_t o) 136 { 137 return *(volatile uint8_t *)(com_base + o); 138 } 139 140 static inline void 141 uart_write(bus_size_t o, uint32_t v) 142 { 143 *(volatile uint8_t *)(com_base + o) = v; 144 } 145 146 static int 147 bcm53xx_cngetc(dev_t dv) 148 { 149 if ((uart_read(com_lsr) & LSR_RXRDY) == 0) 150 return -1; 151 152 return uart_read(com_data) & 0xff; 153 } 154 155 static void 156 bcm53xx_cnputc(dev_t dv, int c) 157 { 158 int timo = 150000; 159 160 while ((uart_read(com_lsr) & LSR_TXRDY) == 0 && --timo > 0) 161 ; 162 163 uart_write(com_data, c); 164 165 timo = 150000; 166 while ((uart_read(com_lsr) & LSR_TSRE) == 0 && --timo > 0) 167 ; 168 } 169 170 static struct consdev bcm53xx_earlycons = { 171 .cn_putc = bcm53xx_cnputc, 172 .cn_getc = bcm53xx_cngetc, 173 .cn_pollc = nullcnpollc, 174 }; 175 #endif /* BCM53XX_CONSOLE_EARLY */ 176 177 psize_t 178 bcm53xx_memprobe(void) 179 { 180 bus_space_tag_t bst = bcm53xx_ioreg_bst; 181 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 182 183 /* 184 * First, let's read the magic DDR registers! 185 */ 186 const uint32_t v01 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_01); 187 const uint32_t v82 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_82); 188 const uint32_t v86 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_86); 189 const uint32_t v87 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_87); 190 191 /* 192 * Calculate chip parameters 193 * */ 194 const u_int rows = __SHIFTOUT(v01, CTL_01_MAX_ROW) 195 - __SHIFTOUT(v82, CTL_82_ROW_DIFF); 196 const u_int cols = __SHIFTOUT(v01, CTL_01_MAX_COL) 197 - __SHIFTOUT(v82, CTL_82_COL_DIFF); 198 const u_int banks_log2 = 3 - __SHIFTOUT(v82, CTL_82_BANK_DIFF); 199 200 /* 201 * For each chip select, increase the chip count if if is enabled. 202 */ 203 const u_int max_chips = __SHIFTOUT(v01, CTL_01_MAX_CHIP_SEL); 204 u_int cs_map = __SHIFTOUT(v86, CTL_86_CS_MAP); 205 u_int chips = 0; 206 207 for (u_int i = 0; cs_map != 0 && i < max_chips; i++, cs_map >>= 1) { 208 chips += (cs_map & 1); 209 } 210 211 /* get log2(ddr width) */ 212 213 const u_int ddr_width_log2 = (v87 & CTL_87_REDUC) ? 1 : 2; 214 215 /* 216 * Let's add up all the things that contribute to the size of a chip. 217 */ 218 const u_int chip_size_log2 = cols + rows + banks_log2 + ddr_width_log2; 219 220 /* 221 * Now our memory size is simply the number of chip shifted by the 222 * log2(chip_size). 223 */ 224 return (psize_t) chips << chip_size_log2; 225 } 226 227 static inline uint32_t 228 bcm53xx_freq_calc(struct bcm53xx_clock_info *clk, 229 uint32_t pdiv, uint32_t ndiv_int, uint32_t ndiv_frac) 230 { 231 if (ndiv_frac == 0 && pdiv == 1) 232 return ndiv_int * clk->clk_ref; 233 234 uint64_t freq64 = ((uint64_t)ndiv_int << 30) + ndiv_frac; 235 freq64 *= clk->clk_ref; 236 if (pdiv > 1) 237 freq64 /= pdiv; 238 return (uint32_t) (freq64 >> 30); 239 } 240 241 static uint32_t 242 bcm53xx_value_wrap(uint32_t value, uint32_t mask) 243 { 244 /* 245 * n is n except when n is 0 then n = mask + 1. 246 */ 247 return ((__SHIFTOUT(value, mask) - 1) & __SHIFTOUT(mask, mask)) + 1; 248 } 249 250 static void 251 bcm53xx_genpll_clock_init(struct bcm53xx_clock_info *clk, uint32_t control5, 252 uint32_t control6, uint32_t control7) 253 { 254 const uint32_t pdiv = bcm53xx_value_wrap(control6, 255 GENPLL_CONTROL6_PDIV); 256 const uint32_t ndiv_int = bcm53xx_value_wrap(control5, 257 GENPLL_CONTROL5_NDIV_INT); 258 const uint32_t ndiv_frac = __SHIFTOUT(control5, 259 GENPLL_CONTROL5_NDIV_FRAC); 260 261 clk->clk_genpll = bcm53xx_freq_calc(clk, pdiv, ndiv_int, ndiv_frac); 262 263 const uint32_t ch0_mdiv = bcm53xx_value_wrap(control6, 264 GENPLL_CONTROL6_CH0_MDIV); 265 const uint32_t ch1_mdiv = bcm53xx_value_wrap(control6, 266 GENPLL_CONTROL6_CH1_MDIV); 267 const uint32_t ch2_mdiv = bcm53xx_value_wrap(control6, 268 GENPLL_CONTROL6_CH2_MDIV); 269 const uint32_t ch3_mdiv = bcm53xx_value_wrap(control7, 270 GENPLL_CONTROL7_CH3_MDIV); 271 272 clk->clk_mac = clk->clk_genpll / ch0_mdiv; // GENPLL CH0 273 clk->clk_robo = clk->clk_genpll / ch1_mdiv; // GENPLL CH1 274 clk->clk_usb2 = clk->clk_genpll / ch2_mdiv; // GENPLL CH2 275 clk->clk_iproc = clk->clk_genpll / ch3_mdiv; // GENPLL CH3 276 } 277 278 static void 279 bcm53xx_lcpll_clock_init(struct bcm53xx_clock_info *clk, uint32_t control1, 280 uint32_t control2) 281 { 282 const uint32_t pdiv = bcm53xx_value_wrap(control1, 283 LCPLL_CONTROL1_PDIV); 284 const uint32_t ndiv_int = bcm53xx_value_wrap(control1, 285 LCPLL_CONTROL1_NDIV_INT); 286 const uint32_t ndiv_frac = __SHIFTOUT(control1, 287 LCPLL_CONTROL1_NDIV_FRAC); 288 289 clk->clk_lcpll = bcm53xx_freq_calc(clk, pdiv, ndiv_int, ndiv_frac); 290 291 const uint32_t ch0_mdiv = bcm53xx_value_wrap(control2, 292 LCPLL_CONTROL2_CH0_MDIV); 293 const uint32_t ch1_mdiv = bcm53xx_value_wrap(control2, 294 LCPLL_CONTROL2_CH1_MDIV); 295 const uint32_t ch2_mdiv = bcm53xx_value_wrap(control2, 296 LCPLL_CONTROL2_CH2_MDIV); 297 const uint32_t ch3_mdiv = bcm53xx_value_wrap(control2, 298 LCPLL_CONTROL2_CH3_MDIV); 299 300 clk->clk_pcie_ref = clk->clk_lcpll / ch0_mdiv; // LCPLL CH0 301 clk->clk_sdio = clk->clk_lcpll / ch1_mdiv; // LCPLL CH1 302 clk->clk_ddr_ref = clk->clk_lcpll / ch2_mdiv; // LCPLL CH2 303 clk->clk_axi = clk->clk_lcpll / ch3_mdiv; // LCPLL CH3 304 } 305 306 static void 307 bcm53xx_usb_clock_init(struct bcm53xx_clock_info *clk, uint32_t usb2_control) 308 { 309 const uint32_t pdiv = bcm53xx_value_wrap(usb2_control, 310 USB2_CONTROL_PDIV); 311 const uint32_t ndiv = bcm53xx_value_wrap(usb2_control, 312 USB2_CONTROL_NDIV_INT); 313 314 uint32_t usb_ref = (clk->clk_usb2 / pdiv) * ndiv; 315 if (usb_ref != USB2_REF_CLK) { 316 /* 317 * USB Reference Clock isn't 1.92GHz. So we need to modify 318 * USB2_CONTROL to produce it. 319 */ 320 uint32_t new_ndiv = (USB2_REF_CLK / clk->clk_usb2) * pdiv; 321 usb2_control &= ~USB2_CONTROL_NDIV_INT; 322 usb2_control |= __SHIFTIN(new_ndiv, USB2_CONTROL_NDIV_INT); 323 324 // Allow Clocks to be modified 325 bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh, 326 CRU_BASE + CRU_CLKSET_KEY, CRU_CLKSET_KEY_MAGIC); 327 328 // Update USB2 clock generator 329 bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh, 330 CRU_BASE + CRU_USB2_CONTROL, usb2_control); 331 332 // Prevent Clock modification 333 bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh, 334 CRU_BASE + CRU_CLKSET_KEY, 0); 335 336 usb_ref = (clk->clk_usb2 / pdiv) * new_ndiv; 337 } 338 339 clk->clk_usb_ref = usb_ref; 340 } 341 342 343 static void 344 bcm53xx_clock_init(struct bcm53xx_clock_info *clk) 345 { 346 clk->clk_ref = BCM53XX_REF_CLK; 347 clk->clk_sys = 8*clk->clk_ref; 348 } 349 350 /* 351 * F(ddr) = ((1 / pdiv) * ndiv * CH2) / (post_div * 2) 352 */ 353 static void 354 bcm53xx_get_ddr_freq(struct bcm53xx_clock_info *clk, uint32_t pll_status, 355 uint32_t pll_dividers) 356 { 357 const bool clocking_4x = (pll_status & PLL_STATUS_CLOCKING_4X) != 0; 358 u_int post_div = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_POST_DIV); 359 u_int pdiv = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_PDIV); 360 u_int ndiv = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_NDIV); 361 362 pdiv = ((pdiv - (clocking_4x ? 1 : 5)) & 7) + 1; 363 364 clk->clk_ddr_mhz = __SHIFTOUT(pll_status, PLL_STATUS_MHZ); 365 clk->clk_ddr = (clk->clk_ddr_ref / pdiv) * ndiv / (2 + post_div); 366 } 367 368 /* 369 * CPU_CLK = (1 / pdiv) * (ndiv_int + (ndiv_frac / 0x40000000)) x F(ref) 370 */ 371 static void 372 bcm53xx_get_cpu_freq(struct bcm53xx_clock_info *clk, 373 uint32_t pllarma, uint32_t pllarmb, uint32_t policy) 374 { 375 policy = __SHIFTOUT(policy, CLK_POLICY_FREQ_POLICY2); 376 377 if (policy == CLK_POLICY_REF_CLK) { 378 clk->clk_cpu = clk->clk_ref; 379 clk->clk_apb = clk->clk_cpu; 380 return; 381 } 382 383 if (policy == CLK_POLICY_SYS_CLK) { 384 clk->clk_cpu = clk->clk_sys; 385 clk->clk_apb = clk->clk_cpu / 4; 386 return; 387 } 388 389 const u_int pdiv = bcm53xx_value_wrap(pllarma, CLK_PLLARMA_PDIV); 390 const u_int ndiv_int = bcm53xx_value_wrap(pllarma, CLK_PLLARMA_NDIV_INT); 391 const u_int ndiv_frac = __SHIFTOUT(pllarmb, CLK_PLLARMB_NDIV_FRAC); 392 // const u_int apb_clk_div = __SHIFTOUT(apb_clk_div, CLK_APB_DIV_VALUE)+1; 393 394 const u_int cpu_div = (policy == CLK_POLICY_ARM_PLL_CH0) ? 4 : 2; 395 396 clk->clk_cpu = bcm53xx_freq_calc(clk, pdiv, ndiv_int, ndiv_frac) / cpu_div; 397 clk->clk_apb = clk->clk_cpu / 4; 398 } 399 400 struct bcm53xx_chip_state { 401 uint32_t bcs_lcpll_control1; 402 uint32_t bcs_lcpll_control2; 403 404 uint32_t bcs_genpll_control5; 405 uint32_t bcs_genpll_control6; 406 uint32_t bcs_genpll_control7; 407 408 uint32_t bcs_usb2_control; 409 410 uint32_t bcs_ddr_phy_ctl_pll_status; 411 uint32_t bcs_ddr_phy_ctl_pll_dividers; 412 413 uint32_t bcs_armcore_clk_policy; 414 uint32_t bcs_armcore_clk_pllarma; 415 uint32_t bcs_armcore_clk_pllarmb; 416 }; 417 418 static void 419 bcm53xx_get_chip_ioreg_state(struct bcm53xx_chip_state *bcs, 420 bus_space_tag_t bst, bus_space_handle_t bsh) 421 { 422 bcs->bcs_lcpll_control1 = bus_space_read_4(bst, bsh, 423 DMU_BASE + DMU_LCPLL_CONTROL1); 424 bcs->bcs_lcpll_control2 = bus_space_read_4(bst, bsh, 425 DMU_BASE + DMU_LCPLL_CONTROL2); 426 427 bcs->bcs_genpll_control5 = bus_space_read_4(bst, bsh, 428 CRU_BASE + CRU_GENPLL_CONTROL5); 429 bcs->bcs_genpll_control6 = bus_space_read_4(bst, bsh, 430 CRU_BASE + CRU_GENPLL_CONTROL6); 431 bcs->bcs_genpll_control7 = bus_space_read_4(bst, bsh, 432 CRU_BASE + CRU_GENPLL_CONTROL7); 433 434 bcs->bcs_usb2_control = bus_space_read_4(bst, bsh, 435 CRU_BASE + CRU_USB2_CONTROL); 436 437 bcs->bcs_ddr_phy_ctl_pll_status = bus_space_read_4(bst, bsh, 438 DDR_BASE + DDR_PHY_CTL_PLL_STATUS); 439 bcs->bcs_ddr_phy_ctl_pll_dividers = bus_space_read_4(bst, bsh, 440 DDR_BASE + DDR_PHY_CTL_PLL_DIVIDERS); 441 } 442 443 static void 444 bcm53xx_get_chip_armcore_state(struct bcm53xx_chip_state *bcs, 445 bus_space_tag_t bst, bus_space_handle_t bsh) 446 { 447 bcs->bcs_armcore_clk_policy = bus_space_read_4(bst, bsh, 448 ARMCORE_CLK_POLICY_FREQ); 449 bcs->bcs_armcore_clk_pllarma = bus_space_read_4(bst, bsh, 450 ARMCORE_CLK_PLLARMA); 451 bcs->bcs_armcore_clk_pllarmb = bus_space_read_4(bst, bsh, 452 ARMCORE_CLK_PLLARMB); 453 } 454 455 void 456 bcm53xx_cpu_softc_init(struct cpu_info *ci) 457 { 458 struct cpu_softc * const cpu = ci->ci_softc; 459 460 cpu->cpu_ioreg_bst = bcm53xx_ioreg_bst; 461 cpu->cpu_ioreg_bsh = bcm53xx_ioreg_bsh; 462 463 cpu->cpu_armcore_bst = bcm53xx_armcore_bst; 464 cpu->cpu_armcore_bsh = bcm53xx_armcore_bsh; 465 } 466 467 void 468 bcm53xx_print_clocks(void) 469 { 470 #if defined(VERBOSE_ARM_INIT) 471 const struct bcm53xx_clock_info * const clk = &cpu_softc.cpu_clk; 472 printf("ref clk = %u (%#x)\n", clk->clk_ref, clk->clk_ref); 473 printf("sys clk = %u (%#x)\n", clk->clk_sys, clk->clk_sys); 474 printf("lcpll clk = %u (%#x)\n", clk->clk_lcpll, clk->clk_lcpll); 475 printf("pcie ref clk = %u (%#x) [CH0]\n", clk->clk_pcie_ref, clk->clk_pcie_ref); 476 printf("sdio clk = %u (%#x) [CH1]\n", clk->clk_sdio, clk->clk_sdio); 477 printf("ddr ref clk = %u (%#x) [CH2]\n", clk->clk_ddr_ref, clk->clk_ddr_ref); 478 printf("axi clk = %u (%#x) [CH3]\n", clk->clk_axi, clk->clk_axi); 479 printf("genpll clk = %u (%#x)\n", clk->clk_genpll, clk->clk_genpll); 480 printf("mac clk = %u (%#x) [CH0]\n", clk->clk_mac, clk->clk_mac); 481 printf("robo clk = %u (%#x) [CH1]\n", clk->clk_robo, clk->clk_robo); 482 printf("usb2 clk = %u (%#x) [CH2]\n", clk->clk_usb2, clk->clk_usb2); 483 printf("iproc clk = %u (%#x) [CH3]\n", clk->clk_iproc, clk->clk_iproc); 484 printf("ddr clk = %u (%#x)\n", clk->clk_ddr, clk->clk_ddr); 485 printf("ddr mhz = %u (%#x)\n", clk->clk_ddr_mhz, clk->clk_ddr_mhz); 486 printf("cpu clk = %u (%#x)\n", clk->clk_cpu, clk->clk_cpu); 487 printf("apb clk = %u (%#x)\n", clk->clk_apb, clk->clk_apb); 488 printf("usb ref clk = %u (%#x)\n", clk->clk_usb_ref, clk->clk_usb_ref); 489 #endif 490 } 491 492 void 493 bcm53xx_bootstrap(vaddr_t iobase) 494 { 495 struct bcm53xx_chip_state bcs; 496 int error; 497 498 #ifdef BCM53XX_CONSOLE_EARLY 499 com_base = iobase + CCA_UART0_BASE; 500 cn_tab = &bcm53xx_earlycons; 501 #endif 502 503 bcm53xx_ioreg_bsh = (bus_space_handle_t) iobase; 504 error = bus_space_map(bcm53xx_ioreg_bst, BCM53XX_IOREG_PBASE, 505 BCM53XX_IOREG_SIZE, 0, &bcm53xx_ioreg_bsh); 506 if (error) 507 panic("%s: failed to map BCM53xx %s registers: %d", 508 __func__, "io", error); 509 510 bcm53xx_armcore_bsh = (bus_space_handle_t) iobase + BCM53XX_IOREG_SIZE; 511 error = bus_space_map(bcm53xx_armcore_bst, BCM53XX_ARMCORE_PBASE, 512 BCM53XX_ARMCORE_SIZE, 0, &bcm53xx_armcore_bsh); 513 if (error) 514 panic("%s: failed to map BCM53xx %s registers: %d", 515 __func__, "armcore", error); 516 517 curcpu()->ci_softc = &cpu_softc; 518 519 bcm53xx_get_chip_ioreg_state(&bcs, bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh); 520 bcm53xx_get_chip_armcore_state(&bcs, bcm53xx_armcore_bst, bcm53xx_armcore_bsh); 521 522 struct bcm53xx_clock_info * const clk = &cpu_softc.cpu_clk; 523 524 bcm53xx_clock_init(clk); 525 bcm53xx_lcpll_clock_init(clk, bcs.bcs_lcpll_control1, 526 bcs.bcs_lcpll_control2); 527 bcm53xx_genpll_clock_init(clk, bcs.bcs_genpll_control5, 528 bcs.bcs_genpll_control6, bcs.bcs_genpll_control7); 529 bcm53xx_usb_clock_init(clk, bcs.bcs_usb2_control); 530 bcm53xx_get_ddr_freq(clk, bcs.bcs_ddr_phy_ctl_pll_status, 531 bcs.bcs_ddr_phy_ctl_pll_dividers); 532 bcm53xx_get_cpu_freq(clk, bcs.bcs_armcore_clk_pllarma, 533 bcs.bcs_armcore_clk_pllarmb, bcs.bcs_armcore_clk_policy); 534 535 curcpu()->ci_data.cpu_cc_freq = clk->clk_cpu; 536 537 arml2cc_init(bcm53xx_armcore_bst, bcm53xx_armcore_bsh, ARMCORE_L2C_BASE); 538 } 539 540 void 541 bcm53xx_dma_bootstrap(psize_t memsize) 542 { 543 if (memsize <= 256*1024*1024) { 544 bcm53xx_dma_ranges[0].dr_len = memsize; 545 bcm53xx_coherent_dma_ranges[0].dr_len = memsize; 546 bcm53xx_dma_tag._nranges = 1; 547 #ifndef _ARM32_NEED_BUS_DMA_BOUNCE 548 bcm53xx_coherent_dma_tag._nranges = 1; 549 #else 550 bcm53xx_bounce_dma_ranges[0].dr_len = memsize; 551 #endif 552 } else { 553 /* 554 * By setting up two ranges, bus_dmamem_alloc will always 555 * try to allocate from range 0 first resulting in allocations 556 * below 256MB which for PCI and GMAC are coherent. 557 */ 558 bcm53xx_dma_ranges[1].dr_len = memsize - 0x10000000; 559 bcm53xx_coherent_dma_ranges[1].dr_len = memsize - 0x10000000; 560 #ifdef _ARM32_NEED_BUS_DMA_BOUNCE 561 bcm53xx_bounce_dma_ranges[1].dr_len = memsize - 0x10000000; 562 #endif 563 } 564 KASSERT(bcm53xx_dma_tag._ranges[0].dr_flags == 0); 565 KASSERT(bcm53xx_coherent_dma_tag._ranges[0].dr_flags == _BUS_DMAMAP_COHERENT); 566 #ifdef _ARM32_NEED_BUS_DMA_BOUNCE 567 KASSERT(bcm53xx_bounce_dma_tag._ranges[0].dr_flags == _BUS_DMAMAP_COHERENT); 568 #endif 569 } 570 571 #ifdef MULTIPROCESSOR 572 void 573 bcm53xx_cpu_hatch(struct cpu_info *ci) 574 { 575 a9tmr_init_cpu_clock(ci); 576 } 577 #endif 578 579 void 580 bcm53xx_device_register(device_t self, void *aux) 581 { 582 prop_dictionary_t dict = device_properties(self); 583 584 if (device_is_a(self, "armperiph") 585 && device_is_a(device_parent(self), "mainbus")) { 586 /* 587 * XXX KLUDGE ALERT XXX 588 * The iot mainbus supplies is completely wrong since it scales 589 * addresses by 2. The simpliest remedy is to replace with our 590 * bus space used for the armcore regisers (which armperiph uses). 591 */ 592 struct mainbus_attach_args * const mb = aux; 593 mb->mb_iot = bcm53xx_armcore_bst; 594 return; 595 } 596 597 /* 598 * We need to tell the A9 Global/Watchdog Timer 599 * what frequency it runs at. 600 */ 601 if (device_is_a(self, "a9tmr") || device_is_a(self, "a9wdt")) { 602 /* 603 * This clock always runs at (arm_clk div 2) and only goes 604 * to timers that are part of the A9 MP core subsystem. 605 */ 606 prop_dictionary_set_uint32(dict, "frequency", 607 cpu_softc.cpu_clk.clk_cpu / 2); 608 return; 609 } 610 611 if (device_is_a(self, "bcmeth")) { 612 const struct bcmccb_attach_args * const ccbaa = aux; 613 const uint8_t enaddr[ETHER_ADDR_LEN] = { 614 0x00, 0x01, 0x02, 0x03, 0x04, 615 0x05 + 2 * ccbaa->ccbaa_loc.loc_port, 616 }; 617 prop_data_t pd = prop_data_create_data(enaddr, ETHER_ADDR_LEN); 618 KASSERT(pd != NULL); 619 if (prop_dictionary_set(device_properties(self), "mac-address", pd) == false) { 620 printf("WARNING: Unable to set mac-address property for %s\n", device_xname(self)); 621 } 622 prop_object_release(pd); 623 } 624 } 625 626 static kmutex_t srab_lock __cacheline_aligned; 627 628 void 629 bcm53xx_srab_init(void) 630 { 631 mutex_init(&srab_lock, MUTEX_DEFAULT, IPL_VM); 632 633 bcm53xx_srab_write_4(0x0079, 0x90); // reset switch 634 for (u_int port = 0; port < 8; port++) { 635 /* per port control: no stp */ 636 bcm53xx_srab_write_4(port, 0x00); 637 } 638 bcm53xx_srab_write_4(0x0008, 0x1c); // IMP port (enab UC/MC/BC) 639 bcm53xx_srab_write_4(0x000e, 0xbb); // IMP port force-link 1G 640 bcm53xx_srab_write_4(0x005d, 0x7b); // port5 force-link 1G 641 bcm53xx_srab_write_4(0x005f, 0x7b); // port7 force-link 1G 642 bcm53xx_srab_write_4(0x000b, 0x7); // management mode 643 bcm53xx_srab_write_4(0x0203, 0x0); // disable BRCM tag 644 bcm53xx_srab_write_4(0x0200, 0x80); // enable IMP=port8 645 } 646 647 static inline void 648 bcm53xx_srab_busywait(bus_space_tag_t bst, bus_space_handle_t bsh) 649 { 650 while (bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT) & SRA_GORDYN) { 651 delay(10); 652 } 653 } 654 655 uint32_t 656 bcm53xx_srab_read_4(u_int pageoffset) 657 { 658 bus_space_tag_t bst = bcm53xx_ioreg_bst; 659 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 660 uint32_t rv; 661 662 mutex_spin_enter(&srab_lock); 663 664 bcm53xx_srab_busywait(bst, bsh); 665 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT, 666 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_GORDYN); 667 bcm53xx_srab_busywait(bst, bsh); 668 rv = bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDL); 669 670 mutex_spin_exit(&srab_lock); 671 return rv; 672 } 673 674 uint64_t 675 bcm53xx_srab_read_8(u_int pageoffset) 676 { 677 bus_space_tag_t bst = bcm53xx_ioreg_bst; 678 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 679 uint64_t rv; 680 681 mutex_spin_enter(&srab_lock); 682 683 bcm53xx_srab_busywait(bst, bsh); 684 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT, 685 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_GORDYN); 686 bcm53xx_srab_busywait(bst, bsh); 687 rv = bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDH); 688 rv <<= 32; 689 rv |= bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDL); 690 691 mutex_spin_exit(&srab_lock); 692 return rv; 693 } 694 695 void 696 bcm53xx_srab_write_4(u_int pageoffset, uint32_t val) 697 { 698 bus_space_tag_t bst = bcm53xx_ioreg_bst; 699 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 700 701 mutex_spin_enter(&srab_lock); 702 703 bcm53xx_srab_busywait(bst, bsh); 704 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDL, val); 705 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT, 706 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_WRITE | SRA_GORDYN); 707 bcm53xx_srab_busywait(bst, bsh); 708 709 mutex_spin_exit(&srab_lock); 710 } 711 712 void 713 bcm53xx_srab_write_8(u_int pageoffset, uint64_t val) 714 { 715 bus_space_tag_t bst = bcm53xx_ioreg_bst; 716 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 717 718 mutex_spin_enter(&srab_lock); 719 720 bcm53xx_srab_busywait(bst, bsh); 721 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDL, val); 722 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDH, val >> 32); 723 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT, 724 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_WRITE | SRA_GORDYN); 725 bcm53xx_srab_busywait(bst, bsh); 726 mutex_spin_exit(&srab_lock); 727 } 728
Indexes created Tue Oct 21 08:09:48 GMT 2025