clps711xreg.h revision 1.1.4.2
1 /* $NetBSD: clps711xreg.h,v 1.1.4.2 2013/06/23 06:20:00 tls Exp $ */ 2 /* 3 * Copyright (c) 2013 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #define PS711X_PADR 0x000 /* Port A Data Register */ 29 #define PS711X_PBDR 0x001 /* Port B Data Register */ 30 #define PS711X_PCDR 0x002 /* Port C Data Register */ 31 #define PS711X_PDDR 0x003 /* Port D Data Register */ 32 #define PS711X_PADDR 0x040 /* Port A Data Direction Register */ 33 #define PS711X_PBDDR 0x041 /* Port B Data Direction Register */ 34 #define PS711X_PCDDR 0x042 /* Port C Data Direction Register */ 35 #define PS711X_PDDDR 0x043 /* Port D Data Direction Register */ 36 #define PS711X_PEDR 0x080 /* Port E Data Register */ 37 #define PS711X_PEDDR 0x0c0 /* Port E Data Direction Register */ 38 #define PS711X_SYSCON 0x100 /* System Control Register */ 39 #define SYSCON_IRTXM (1 << 20) 40 #define SYSCON_WAKEDIS (1 << 19) 41 #define SYSCON_EXCKEN (1 << 18) 42 #define SYSCON_ADCKSEL (0x3 << 16) 43 #define SYSCON_SIREN (1 << 15) 44 #define SYSCON_CDENRX (1 << 14) 45 #define SYSCON_CDENTX (1 << 13) 46 #define SYSCON_LCDEN (1 << 12) 47 #define SYSCON_DBGEN (1 << 11) 48 #define SYSCON_BZMOD (1 << 10) 49 #define SYSCON_BZTOG (1 << 9) 50 #define SYSCON_UARTEN (1 << 8) 51 #define SYSCON_TC2S (1 << 7) 52 #define SYSCON_TC2M (1 << 6) 53 #define SYSCON_TC1S (1 << 5) 54 #define SYSCON_TC1M (1 << 4) 55 #define SYSCON_KBDSCAN_MASK (0xf << 0) 56 #define PS711X_SYSFLG 0x140 /* System Status Flag Register (RO) */ 57 #define SYSFLG_VERID(x) (((x) >> 30) & 0x3) 58 #define SYSFLG_BOOT8BIT (1 << 27) 59 #define SYSFLG_SSIBUSY (1 << 26) 60 #define SYSFLG_CTXFF (1 << 25) 61 #define SYSFLG_CRXFE (1 << 24) 62 #define SYSFLG_UTXFF (1 << 23) 63 #define SYSFLG_URXFE (1 << 22) 64 #define SYSFLG_RTCDIV (0x3f << 16) 65 #define SYSFLG_CLDFLG (1 << 15) 66 #define SYSFLG_PFFLG (1 << 14) 67 #define SYSFLG_RSTFLG (1 << 13) 68 #define SYSFLG_NBFLG (1 << 12) 69 #define SYSFLG_UBUSY (1 << 11) 70 #define SYSFLG_DCD (1 << 10) 71 #define SYSFLG_DSR (1 << 9) 72 #define SYSFLG_CTS (1 << 8) 73 #define SYSFLG_DID (1 << 7) 74 #define SYSFLG_WUON (1 << 3) 75 #define SYSFLG_WUDR (1 << 2) 76 #define SYSFLG_DCDET (1 << 1) 77 #define SYSFLG_MCDR (1 << 0) 78 #define PS711X_MEMCFG1 0x180 /* Memory Configuration Register 1 */ 79 #define MEMCFG1_NCSCFG(n, x) ((x) << ((n) << 3)) 80 #define PS711X_MEMCFG2 0x1c0 /* Memory Configuration Register 2 */ 81 #define MEMCFG2_CSCFG(n, x) ((x) << ((n) << 3)) 82 #define CSCFG_CLKEN (1 << 7) 83 #define CSCFG_SQAEN (1 << 6) 84 #define CSCFG_SAWS_MASK (0x3 << 4) /* Sequential access wait state */ 85 #define CSCFG_RAWS_MASK (0x3 << 2) /* Random access wait state */ 86 #define CSCFG_BUSWIDTH_MASK (0x3 << 0) 87 #define PS711X_DRFPR 0x200 /* DRAM Refresh Period Register */ 88 #define DRFPR_RFSHEN (1 << 7) 89 #define DRFPR_RFDIV_MASK (0x7f << 0) 90 #define PS711X_INTSR 0x240 /* Interrupt Status Register (RO) */ 91 #define PS711X_INTMR 0x280 /* Interrupt Mask Register */ 92 #define PS711X_LCDCON 0x2c0 /* LCD Control Register */ 93 #define LCDCON_GSMD (1 << 31) /* Grayscale mode 0:2bpp/1:4bpp */ 94 #define LCDCON_GSEN (1 << 30) /* Grayscale enable */ 95 #define LCDCON_ACP_SFT 25 /* AC prescale */ 96 #define LCDCON_ACP_MSK 0x1f 97 #define LCDCON_ACP(b) ((((b) + 1) & LCDCON_ACP_MSK) << LCDCON_ACP_SFT) 98 #define LCDCON_PP_SFT 19 /* Pixel prescale */ 99 #define LCDCON_PP_MSK 0x3f 100 #define LCDCON_PP(b) (((526628 / (b) - 1) & LCDCON_PP_MSK) << LCDCON_PP_SFT) 101 #define LCDCON_LL_SFT 13 /* Line length */ 102 #define LCDCON_LL_MSK 0x3f 103 #define LCDCON_LL(b) ((((b) / 16 - 1) & LCDCON_LL_MSK) << LCDCON_LL_SFT) 104 #define LCDCON_VBS_SFT 0 /* Video buffer size */ 105 #define LCDCON_VBS_MSK 0x1fff 106 #define LCDCON_VBS(b) ((((b) / 128 - 1) & LCDCON_VBS_MSK) << LCDCON_VBS_SFT) 107 #define PS711X_TC1D 0x300 /* Read/Write data to TC1 */ 108 #define PS711X_TC2D 0x340 /* Read/Write data to TC2 */ 109 #define PS711X_RTCDR 0x380 /* Realtime Clock Data Register */ 110 #define PS711X_RTCMR 0x3c0 /* Realtime Clock Match Register */ 111 #define PS711X_PMPCON 0x400 /* DC-to-DC Pump Control Register */ 112 #define PS711X_CODR 0x440 /* Codec Data I/O Register */ 113 #define PS711X_UARTDR 0x480 /* UART FIFO Data Register */ 114 #define UARTDR_OVERR (1 << 10) 115 #define UARTDR_PARERR (1 << 9) 116 #define UARTDR_FRMERR (1 << 8) 117 #define UARTDR_RXDATA_MASK 0xff 118 #define PS711X_UBRLCR 0x4c0 /* UART Bit Rate and Line Control Register */ 119 #define UBRLCR_WRDLEN_MASK (0x3 << 17) 120 #define UBRLCR_WRDLEN_8B (0x3 << 17) 121 #define UBRLCR_WRDLEN_7B (0x2 << 17) 122 #define UBRLCR_WRDLEN_6B (0x1 << 17) 123 #define UBRLCR_WRDLEN_5B (0x0 << 17) 124 #define UBRLCR_FIFOEN (1 << 16) 125 #define UBRLCR_XSTOP (1 << 15) 126 #define UBRLCR_EVENPRT (1 << 14) 127 #define UBRLCR_PRTEN (1 << 13) 128 #define UBRLCR_BREAK (1 << 12) 129 #define UBRLCR_BRD_MASK (0xfff << 0) /* Bit rate divisor */ 130 #define PS711X_SYNCIO 0x500 /* Synchronous Serial I/O Data Register */ 131 #define PS711X_PALLSW 0x540 /* Least-significant 32b Word of LCD Palette */ 132 #define PS711X_PALMSW 0x580 /* Most-significant 32b Word of LCD Palette */ 133 #define PS711X_STFCLR 0x5c0 /* Write to clear all Start up reason flags */ 134 #define PS711X_BLEOI 0x600 /* Write to clear Battery Low Interrupt */ 135 #define PS711X_MCEOI 0x640 /* Write to clear Media Changed Interrupt */ 136 #define PS711X_TEOI 0x680 /* Write to clear Tick and Watchdog Interrupt */ 137 #define PS711X_TC1EOI 0x6c0 /* Write to clear TC1 Interrupt */ 138 #define PS711X_TC2EOI 0x700 /* Write to clear TC2 Interrupt */ 139 #define PS711X_RTCEOI 0x740 /* Write to clear RTC Match Interrupt */ 140 #define PS711X_UMSEOI 0x780 /* Write to clear UART Modem Stat Changed Int */ 141 #define PS711X_COEOI 0x7c0 /* Write to clear Codec Sound Interrupt */ 142 #define PS711X_HALT 0x800 /* Write to enter idle state */ 143 #define PS711X_STDBY 0x840 /* Write to enter standby state */ 144 145 #define IRQ_EXTFIQ 0 /* External fast interrupt */ 146 #define IRQ_BLINT 1 /* Battery low interrupt */ 147 #define IRQ_WEINT 2 /* Watch dog expired interrupt */ 148 #define IRQ_MCINT 3 /* Media changed interrupt */ 149 #define IRQ_CSINT 4 /* Codec sound interrupt */ 150 #define IRQ_EINT1 5 /* External interrupt 1 */ 151 #define IRQ_EINT2 6 /* External interrupt 2 */ 152 #define IRQ_EINT3 7 /* External interrupt 3 */ 153 #define IRQ_TC1DI 8 /* TC1 under-flow interrupt */ 154 #define IRQ_TC2DI 9 /* TC2 under-flow interrupt */ 155 #define IRQ_RTCMI 10 /* RTC compare match interrupt */ 156 #define IRQ_TINT 11 /* 64-Hz tick interrupt */ 157 #define IRQ_UTXINT 12 /* Internal UART transmit FIFO half-empty */ 158 #define IRQ_URXINT 13 /* Internal UART receive FIFO half-full */ 159 #define IRQ_UMSINT 14 /* Internal UART modem status changed */ 160 #define IRQ_SSEOTI 15 /* Synchronous serial interface end-of-transfer */ 161
Indexes created Wed Oct 29 12:09:47 GMT 2025