a9wdt.c revision 1.1
1 /* $NetBSD: a9wdt.c,v 1.1 2012/09/01 00:03:14 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: a9wdt.c,v 1.1 2012/09/01 00:03:14 matt Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/cpu.h> 38 #include <sys/device.h> 39 #include <sys/wdog.h> 40 41 #include <prop/proplib.h> 42 43 #include <dev/sysmon/sysmonvar.h> 44 45 #include <arm/cortex/a9tmr_reg.h> 46 47 #include <arm/cortex/mpcore_var.h> 48 49 static int a9wdt_match(device_t, cfdata_t, void *); 50 static void a9wdt_attach(device_t, device_t, void *); 51 52 struct a9wdt_softc { 53 struct sysmon_wdog sc_smw; 54 device_t sc_dev; 55 bus_space_tag_t sc_memt; 56 bus_space_handle_t sc_wdog_memh; 57 u_int sc_wdog_max_period; 58 u_int sc_wdog_period; 59 u_int sc_wdog_prescaler; 60 uint32_t sc_freq; 61 uint32_t sc_wdog_load; 62 uint32_t sc_wdog_ctl; 63 bool sc_wdog_armed; 64 }; 65 66 #ifndef A9WDT_PERIOD_DEFAULT 67 #define A9WDT_PERIOD_DEFAULT 12 68 #endif 69 70 CFATTACH_DECL_NEW(a9wdt, sizeof(struct a9wdt_softc), 71 a9wdt_match, a9wdt_attach, NULL, NULL); 72 73 static bool attached; 74 75 static inline uint32_t 76 a9wdt_wdog_read(struct a9wdt_softc *sc, bus_size_t o) 77 { 78 return bus_space_read_4(sc->sc_memt, sc->sc_wdog_memh, o); 79 } 80 81 static inline void 82 a9wdt_wdog_write(struct a9wdt_softc *sc, bus_size_t o, uint32_t v) 83 { 84 bus_space_write_4(sc->sc_memt, sc->sc_wdog_memh, o, v); 85 } 86 87 88 /* ARGSUSED */ 89 static int 90 a9wdt_match(device_t parent, cfdata_t cf, void *aux) 91 { 92 struct mpcore_attach_args * const mpcaa = aux; 93 94 if (attached) 95 return 0; 96 97 if (!CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid)) 98 return 0; 99 100 if (strcmp(mpcaa->mpcaa_name, cf->cf_name) != 0) 101 return 0; 102 103 /* 104 * This isn't present on UP A9s (since CBAR isn't present). 105 */ 106 uint32_t mpidr = armreg_mpidr_read(); 107 if (mpidr == 0 || (mpidr & MPIDR_U)) 108 return 0; 109 110 return 1; 111 } 112 113 static int 114 a9wdt_tickle(struct sysmon_wdog *smw) 115 { 116 struct a9wdt_softc * const sc = smw->smw_cookie; 117 118 /* 119 * Cause the WDOG to restart counting. 120 */ 121 a9wdt_wdog_write(sc, TMR_LOAD, sc->sc_wdog_load); 122 aprint_debug_dev(sc->sc_dev, "tickle\n"); 123 return 0; 124 } 125 126 static int 127 a9wdt_setmode(struct sysmon_wdog *smw) 128 { 129 struct a9wdt_softc * const sc = smw->smw_cookie; 130 131 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 132 /* 133 * Emit magic sequence to turn off WDOG 134 */ 135 a9wdt_wdog_write(sc, TMR_WDOGDIS, TMR_WDOG_DISABLE_MAGIC1); 136 a9wdt_wdog_write(sc, TMR_WDOGDIS, TMR_WDOG_DISABLE_MAGIC2); 137 delay(1); 138 sc->sc_wdog_ctl = a9wdt_wdog_read(sc, TMR_CTL); 139 KASSERT((sc->sc_wdog_ctl & TMR_CTL_WDOG_MODE) == 0); 140 aprint_debug_dev(sc->sc_dev, "setmode disable\n"); 141 return 0; 142 } 143 144 /* 145 * If no changes, just tickle it and return. 146 */ 147 if (sc->sc_wdog_armed && smw->smw_period == sc->sc_wdog_period) { 148 sc->sc_wdog_load = sc->sc_freq * sc->sc_wdog_period - 1; 149 sc->sc_wdog_ctl = TMR_CTL_ENABLE | TMR_CTL_WDOG_MODE 150 | __SHIFTIN(sc->sc_wdog_prescaler - 1, TMR_CTL_PRESCALER); 151 152 a9wdt_wdog_write(sc, TMR_LOAD, sc->sc_wdog_load); 153 a9wdt_wdog_write(sc, TMR_CTL, sc->sc_wdog_ctl); 154 aprint_debug_dev(sc->sc_dev, "setmode refresh\n"); 155 return 0; 156 } 157 158 if (smw->smw_period == WDOG_PERIOD_DEFAULT) { 159 sc->sc_wdog_period = A9WDT_PERIOD_DEFAULT; 160 smw->smw_period = A9WDT_PERIOD_DEFAULT; 161 } 162 163 /* 164 * Make sure we don't overflow the counter. 165 */ 166 if (smw->smw_period >= sc->sc_wdog_max_period) { 167 return EINVAL; 168 } 169 170 sc->sc_wdog_load = sc->sc_freq * sc->sc_wdog_period - 1; 171 sc->sc_wdog_ctl = TMR_CTL_ENABLE | TMR_CTL_WDOG_MODE 172 | __SHIFTIN(sc->sc_wdog_prescaler - 1, TMR_CTL_PRESCALER); 173 174 a9wdt_wdog_write(sc, TMR_LOAD, sc->sc_wdog_load); 175 a9wdt_wdog_write(sc, TMR_CTL, sc->sc_wdog_load); 176 177 aprint_debug_dev(sc->sc_dev, "setmode enable\n"); 178 return 0; 179 } 180 181 182 static void 183 a9wdt_attach(device_t parent, device_t self, void *aux) 184 { 185 struct a9wdt_softc * const sc = device_private(self); 186 struct mpcore_attach_args * const mpcaa = aux; 187 prop_dictionary_t dict = device_properties(self); 188 189 sc->sc_dev = self; 190 sc->sc_memt = mpcaa->mpcaa_memt; 191 192 bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh, 193 TMR_WDOG_BASE, TMR_WDOG_SIZE, &sc->sc_wdog_memh); 194 195 /* 196 * This runs at the ARM PERIPHCLOCK which should be 1/2 of the 197 * CPU clock. The MD code should have setup our frequency for us. 198 */ 199 prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq); 200 201 sc->sc_wdog_ctl = a9wdt_wdog_read(sc, TMR_CTL); 202 sc->sc_wdog_armed = (sc->sc_wdog_ctl & TMR_CTL_WDOG_MODE) != 0; 203 if (sc->sc_wdog_armed) { 204 sc->sc_wdog_prescaler = 205 __SHIFTOUT(sc->sc_wdog_ctl, TMR_CTL_PRESCALER) + 1; 206 sc->sc_freq /= sc->sc_wdog_prescaler; 207 sc->sc_wdog_load = a9wdt_wdog_read(sc, TMR_LOAD); 208 sc->sc_wdog_period = (sc->sc_wdog_load + 1) / sc->sc_freq; 209 } else { 210 sc->sc_wdog_period = A9WDT_PERIOD_DEFAULT; 211 sc->sc_wdog_prescaler = 1; 212 /* 213 * Let's hope the timer frequency isn't prime. 214 */ 215 for (size_t div = 256; div >= 2; div++) { 216 if (sc->sc_freq % div == 0) { 217 sc->sc_wdog_prescaler = div; 218 break; 219 } 220 } 221 sc->sc_freq /= sc->sc_wdog_prescaler; 222 } 223 sc->sc_wdog_max_period = UINT32_MAX / sc->sc_freq; 224 225 /* 226 * Does the config file tell us to turn on the watchdog? 227 */ 228 if (device_cfdata(self)->cf_flags & 1) 229 sc->sc_wdog_armed = true; 230 231 aprint_naive("\n"); 232 aprint_normal(": A9 Watchdog Timer, default period is %u seconds%s\n", 233 sc->sc_wdog_period, 234 sc->sc_wdog_armed ? " (armed)" : ""); 235 236 sc->sc_smw.smw_name = device_xname(self); 237 sc->sc_smw.smw_cookie = sc; 238 sc->sc_smw.smw_setmode = a9wdt_setmode; 239 sc->sc_smw.smw_tickle = a9wdt_tickle; 240 sc->sc_smw.smw_period = sc->sc_wdog_period; 241 242 if (sc->sc_wdog_armed) { 243 int error = sysmon_wdog_setmode(&sc->sc_smw, WDOG_MODE_KTICKLE, 244 sc->sc_wdog_period); 245 if (error) 246 aprint_error_dev(self, 247 "failed to start kernel tickler: %d\n", error); 248 } 249 } 250
Indexes created Wed Sep 24 15:09:51 GMT 2025