armperiph.c revision 1.14 1 1.1 matt /*-
2 1.1 matt * Copyright (c) 2012 The NetBSD Foundation, Inc.
3 1.1 matt * All rights reserved.
4 1.1 matt *
5 1.1 matt * This code is derived from software contributed to The NetBSD Foundation
6 1.1 matt * by Matt Thomas of 3am Software Foundry.
7 1.1 matt *
8 1.1 matt * Redistribution and use in source and binary forms, with or without
9 1.1 matt * modification, are permitted provided that the following conditions
10 1.1 matt * are met:
11 1.1 matt * 1. Redistributions of source code must retain the above copyright
12 1.1 matt * notice, this list of conditions and the following disclaimer.
13 1.1 matt * 2. Redistributions in binary form must reproduce the above copyright
14 1.1 matt * notice, this list of conditions and the following disclaimer in the
15 1.1 matt * documentation and/or other materials provided with the distribution.
16 1.1 matt *
17 1.1 matt * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
18 1.1 matt * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
19 1.1 matt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 1.1 matt * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
21 1.1 matt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 1.1 matt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 1.1 matt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 1.1 matt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 1.1 matt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 1.1 matt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 1.1 matt * POSSIBILITY OF SUCH DAMAGE.
28 1.1 matt */
29 1.1 matt
30 1.1 matt #include "locators.h"
31 1.14 skrll #include "opt_cputypes.h"
32 1.1 matt
33 1.1 matt #include <sys/cdefs.h>
34 1.1 matt
35 1.14 skrll __KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.14 2018/08/15 06:00:02 skrll Exp $");
36 1.1 matt
37 1.1 matt #include <sys/param.h>
38 1.1 matt #include <sys/device.h>
39 1.10 matt #include <sys/lwp.h>
40 1.1 matt
41 1.1 matt #include "ioconf.h"
42 1.1 matt
43 1.1 matt #include <arm/mainbus/mainbus.h>
44 1.1 matt #include <arm/cortex/mpcore_var.h>
45 1.9 skrll #include <arm/cortex/gtmr_intr.h>
46 1.1 matt
47 1.1 matt static int armperiph_match(device_t, cfdata_t, void *);
48 1.1 matt static void armperiph_attach(device_t, device_t, void *);
49 1.1 matt
50 1.1 matt static bool attached;
51 1.1 matt
52 1.1 matt struct armperiph_softc {
53 1.1 matt device_t sc_dev;
54 1.1 matt bus_space_tag_t sc_memt;
55 1.1 matt bus_space_handle_t sc_memh;
56 1.1 matt };
57 1.1 matt
58 1.4 matt struct armperiph_info {
59 1.4 matt const char pi_name[12];
60 1.4 matt bus_size_t pi_off1;
61 1.4 matt bus_size_t pi_off2;
62 1.4 matt };
63 1.4 matt
64 1.2 matt #ifdef CPU_CORTEXA5
65 1.4 matt static const struct armperiph_info a5_devices[] = {
66 1.13 hkenken { "armscu", 0x0000, 0 },
67 1.13 hkenken { "armgic", 0x1000, 0x0100 },
68 1.13 hkenken { "arma9tmr", 0x0200, 0 },
69 1.13 hkenken { "a9wdt", 0x0600, 0 },
70 1.13 hkenken { "arml2cc", 0, 0 }, /* external; needs "offset" property */
71 1.4 matt { "", 0, 0 },
72 1.1 matt };
73 1.1 matt #endif
74 1.1 matt
75 1.1 matt #ifdef CPU_CORTEXA7
76 1.4 matt static const struct armperiph_info a7_devices[] = {
77 1.4 matt { "armgic", 0x1000, 0x2000 },
78 1.4 matt { "armgtmr", 0, 0 },
79 1.4 matt { "", 0, 0 },
80 1.1 matt };
81 1.1 matt #endif
82 1.1 matt
83 1.1 matt #ifdef CPU_CORTEXA9
84 1.4 matt static const struct armperiph_info a9_devices[] = {
85 1.13 hkenken { "armscu", 0x0000, 0 },
86 1.13 hkenken { "arml2cc", 0x2000, 0 },
87 1.13 hkenken { "armgic", 0x1000, 0x0100 },
88 1.13 hkenken { "arma9tmr", 0x0200, 0 },
89 1.13 hkenken { "a9wdt", 0x0600, 0 },
90 1.4 matt { "", 0, 0 },
91 1.1 matt };
92 1.1 matt #endif
93 1.1 matt
94 1.3 matt #ifdef CPU_CORTEXA15
95 1.4 matt static const struct armperiph_info a15_devices[] = {
96 1.4 matt { "armgic", 0x1000, 0x2000 },
97 1.4 matt { "armgtmr", 0, 0 },
98 1.4 matt { "", 0, 0 },
99 1.3 matt };
100 1.3 matt #endif
101 1.3 matt
102 1.10 matt #ifdef CPU_CORTEXA17
103 1.10 matt static const struct armperiph_info a17_devices[] = {
104 1.10 matt { "armgic", 0x1000, 0x2000 },
105 1.10 matt { "armgtmr", 0, 0 },
106 1.10 matt { "", 0, 0 },
107 1.10 matt };
108 1.10 matt #endif
109 1.10 matt
110 1.11 jmcneill #ifdef CPU_CORTEXA57
111 1.11 jmcneill static const struct armperiph_info a57_devices[] = {
112 1.11 jmcneill { "armgic", 0x1000, 0x2000 },
113 1.11 jmcneill { "armgtmr", 0, 0 },
114 1.11 jmcneill { "", 0, 0 },
115 1.11 jmcneill };
116 1.11 jmcneill #endif
117 1.11 jmcneill
118 1.3 matt
119 1.1 matt static const struct mpcore_config {
120 1.4 matt const struct armperiph_info *cfg_devices;
121 1.1 matt uint32_t cfg_cpuid;
122 1.1 matt uint32_t cfg_cbar_size;
123 1.1 matt } configs[] = {
124 1.1 matt #ifdef CPU_CORTEXA5
125 1.4 matt { a5_devices, 0x410fc050, 2*4096 },
126 1.1 matt #endif
127 1.1 matt #ifdef CPU_CORTEXA7
128 1.4 matt { a7_devices, 0x410fc070, 8*4096 },
129 1.1 matt #endif
130 1.1 matt #ifdef CPU_CORTEXA9
131 1.2 matt { a9_devices, 0x410fc090, 3*4096 },
132 1.1 matt #endif
133 1.1 matt #ifdef CPU_CORTEXA15
134 1.3 matt { a15_devices, 0x410fc0f0, 8*4096 },
135 1.1 matt #endif
136 1.10 matt #ifdef CPU_CORTEXA17
137 1.10 matt { a17_devices, 0x410fc0e0, 8*4096 },
138 1.10 matt #endif
139 1.11 jmcneill #ifdef CPU_CORTEXA57
140 1.11 jmcneill { a57_devices, 0x410fd070, 8*4096 },
141 1.11 jmcneill #endif
142 1.1 matt };
143 1.1 matt
144 1.1 matt static const struct mpcore_config *
145 1.1 matt armperiph_find_config(void)
146 1.1 matt {
147 1.1 matt const uint32_t arm_cpuid = curcpu()->ci_arm_cpuid & 0xff0ff0f0;
148 1.1 matt for (size_t i = 0; i < __arraycount(configs); i++) {
149 1.1 matt if (arm_cpuid == configs[i].cfg_cpuid) {
150 1.1 matt return configs + i;
151 1.1 matt }
152 1.1 matt }
153 1.1 matt
154 1.1 matt return NULL;
155 1.1 matt }
156 1.1 matt
157 1.1 matt CFATTACH_DECL_NEW(armperiph, sizeof(struct armperiph_softc),
158 1.1 matt armperiph_match, armperiph_attach, NULL, NULL);
159 1.1 matt
160 1.1 matt static int
161 1.1 matt armperiph_match(device_t parent, cfdata_t cf, void *aux)
162 1.1 matt {
163 1.1 matt struct mainbus_attach_args * const mb = aux;
164 1.1 matt const int base = cf->cf_loc[MAINBUSCF_BASE];
165 1.1 matt const int size = cf->cf_loc[MAINBUSCF_SIZE];
166 1.1 matt const int dack = cf->cf_loc[MAINBUSCF_DACK];
167 1.1 matt const int irq = cf->cf_loc[MAINBUSCF_IRQ];
168 1.1 matt const int intrbase = cf->cf_loc[MAINBUSCF_INTRBASE];
169 1.1 matt
170 1.1 matt if (attached)
171 1.1 matt return 0;
172 1.1 matt
173 1.1 matt if (base != MAINBUSCF_BASE_DEFAULT || base != mb->mb_iobase
174 1.1 matt || size != MAINBUSCF_SIZE_DEFAULT || size != mb->mb_iosize
175 1.1 matt || dack != MAINBUSCF_DACK_DEFAULT || dack != mb->mb_drq
176 1.1 matt || irq != MAINBUSCF_IRQ_DEFAULT || irq != mb->mb_irq
177 1.1 matt || intrbase != MAINBUSCF_INTRBASE_DEFAULT
178 1.1 matt || intrbase != mb->mb_intrbase)
179 1.1 matt return 0;
180 1.1 matt
181 1.1 matt if (!CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid))
182 1.1 matt return 0;
183 1.1 matt
184 1.1 matt if (armreg_cbar_read() == 0)
185 1.1 matt return 0;
186 1.1 matt
187 1.1 matt if (armperiph_find_config() == NULL)
188 1.1 matt return 0;
189 1.1 matt
190 1.1 matt return 1;
191 1.1 matt }
192 1.1 matt
193 1.1 matt static void
194 1.1 matt armperiph_attach(device_t parent, device_t self, void *aux)
195 1.1 matt {
196 1.1 matt struct armperiph_softc * const sc = device_private(self);
197 1.1 matt struct mainbus_attach_args * const mb = aux;
198 1.1 matt bus_addr_t cbar = armreg_cbar_read();
199 1.1 matt const struct mpcore_config * const cfg = armperiph_find_config();
200 1.5 jmcneill prop_dictionary_t prop = device_properties(self);
201 1.5 jmcneill uint32_t cbar_override;
202 1.5 jmcneill
203 1.5 jmcneill if (prop_dictionary_get_uint32(prop, "cbar", &cbar_override))
204 1.5 jmcneill cbar = (bus_addr_t)cbar_override;
205 1.1 matt
206 1.1 matt /*
207 1.1 matt * The normal mainbus bus space will not work for us so the port's
208 1.1 matt * device_register must have replaced it with one that will work.
209 1.1 matt */
210 1.1 matt sc->sc_dev = self;
211 1.1 matt sc->sc_memt = mb->mb_iot;
212 1.1 matt
213 1.1 matt int error = bus_space_map(sc->sc_memt, cbar, cfg->cfg_cbar_size, 0,
214 1.1 matt &sc->sc_memh);
215 1.1 matt if (error) {
216 1.1 matt aprint_normal(": error mapping registers at %#lx: %d\n",
217 1.1 matt cbar, error);
218 1.1 matt return;
219 1.1 matt }
220 1.1 matt aprint_normal("\n");
221 1.1 matt
222 1.1 matt /*
223 1.1 matt * Let's try to attach any children we may have.
224 1.1 matt */
225 1.4 matt for (size_t i = 0; cfg->cfg_devices[i].pi_name[0] != 0; i++) {
226 1.1 matt struct mpcore_attach_args mpcaa = {
227 1.4 matt .mpcaa_name = cfg->cfg_devices[i].pi_name,
228 1.1 matt .mpcaa_memt = sc->sc_memt,
229 1.1 matt .mpcaa_memh = sc->sc_memh,
230 1.4 matt .mpcaa_off1 = cfg->cfg_devices[i].pi_off1,
231 1.4 matt .mpcaa_off2 = cfg->cfg_devices[i].pi_off2,
232 1.1 matt };
233 1.13 hkenken #if defined(CPU_CORTEXA9)
234 1.13 hkenken if (strcmp(mpcaa.mpcaa_name, "arma9tmr") == 0)
235 1.13 hkenken mpcaa.mpcaa_irq = IRQ_A9TMR_PPI_GTIMER;
236 1.13 hkenken #endif
237 1.11 jmcneill #if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15) || defined(CPU_CORTEXA57)
238 1.8 skrll if (strcmp(mpcaa.mpcaa_name, "armgtmr") == 0) {
239 1.8 skrll mpcaa.mpcaa_irq = IRQ_GTMR_PPI_VTIMER;
240 1.8 skrll }
241 1.9 skrll #endif
242 1.1 matt
243 1.1 matt config_found(self, &mpcaa, NULL);
244 1.1 matt }
245 1.12 skrll attached = true;
246 1.1 matt }
247