armperiph.c revision 1.14
1 /*- 2 * Copyright (c) 2012 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas of 3am Software Foundry. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include "locators.h" 31 #include "opt_cputypes.h" 32 33 #include <sys/cdefs.h> 34 35 __KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.14 2018/08/15 06:00:02 skrll Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/device.h> 39 #include <sys/lwp.h> 40 41 #include "ioconf.h" 42 43 #include <arm/mainbus/mainbus.h> 44 #include <arm/cortex/mpcore_var.h> 45 #include <arm/cortex/gtmr_intr.h> 46 47 static int armperiph_match(device_t, cfdata_t, void *); 48 static void armperiph_attach(device_t, device_t, void *); 49 50 static bool attached; 51 52 struct armperiph_softc { 53 device_t sc_dev; 54 bus_space_tag_t sc_memt; 55 bus_space_handle_t sc_memh; 56 }; 57 58 struct armperiph_info { 59 const char pi_name[12]; 60 bus_size_t pi_off1; 61 bus_size_t pi_off2; 62 }; 63 64 #ifdef CPU_CORTEXA5 65 static const struct armperiph_info a5_devices[] = { 66 { "armscu", 0x0000, 0 }, 67 { "armgic", 0x1000, 0x0100 }, 68 { "arma9tmr", 0x0200, 0 }, 69 { "a9wdt", 0x0600, 0 }, 70 { "arml2cc", 0, 0 }, /* external; needs "offset" property */ 71 { "", 0, 0 }, 72 }; 73 #endif 74 75 #ifdef CPU_CORTEXA7 76 static const struct armperiph_info a7_devices[] = { 77 { "armgic", 0x1000, 0x2000 }, 78 { "armgtmr", 0, 0 }, 79 { "", 0, 0 }, 80 }; 81 #endif 82 83 #ifdef CPU_CORTEXA9 84 static const struct armperiph_info a9_devices[] = { 85 { "armscu", 0x0000, 0 }, 86 { "arml2cc", 0x2000, 0 }, 87 { "armgic", 0x1000, 0x0100 }, 88 { "arma9tmr", 0x0200, 0 }, 89 { "a9wdt", 0x0600, 0 }, 90 { "", 0, 0 }, 91 }; 92 #endif 93 94 #ifdef CPU_CORTEXA15 95 static const struct armperiph_info a15_devices[] = { 96 { "armgic", 0x1000, 0x2000 }, 97 { "armgtmr", 0, 0 }, 98 { "", 0, 0 }, 99 }; 100 #endif 101 102 #ifdef CPU_CORTEXA17 103 static const struct armperiph_info a17_devices[] = { 104 { "armgic", 0x1000, 0x2000 }, 105 { "armgtmr", 0, 0 }, 106 { "", 0, 0 }, 107 }; 108 #endif 109 110 #ifdef CPU_CORTEXA57 111 static const struct armperiph_info a57_devices[] = { 112 { "armgic", 0x1000, 0x2000 }, 113 { "armgtmr", 0, 0 }, 114 { "", 0, 0 }, 115 }; 116 #endif 117 118 119 static const struct mpcore_config { 120 const struct armperiph_info *cfg_devices; 121 uint32_t cfg_cpuid; 122 uint32_t cfg_cbar_size; 123 } configs[] = { 124 #ifdef CPU_CORTEXA5 125 { a5_devices, 0x410fc050, 2*4096 }, 126 #endif 127 #ifdef CPU_CORTEXA7 128 { a7_devices, 0x410fc070, 8*4096 }, 129 #endif 130 #ifdef CPU_CORTEXA9 131 { a9_devices, 0x410fc090, 3*4096 }, 132 #endif 133 #ifdef CPU_CORTEXA15 134 { a15_devices, 0x410fc0f0, 8*4096 }, 135 #endif 136 #ifdef CPU_CORTEXA17 137 { a17_devices, 0x410fc0e0, 8*4096 }, 138 #endif 139 #ifdef CPU_CORTEXA57 140 { a57_devices, 0x410fd070, 8*4096 }, 141 #endif 142 }; 143 144 static const struct mpcore_config * 145 armperiph_find_config(void) 146 { 147 const uint32_t arm_cpuid = curcpu()->ci_arm_cpuid & 0xff0ff0f0; 148 for (size_t i = 0; i < __arraycount(configs); i++) { 149 if (arm_cpuid == configs[i].cfg_cpuid) { 150 return configs + i; 151 } 152 } 153 154 return NULL; 155 } 156 157 CFATTACH_DECL_NEW(armperiph, sizeof(struct armperiph_softc), 158 armperiph_match, armperiph_attach, NULL, NULL); 159 160 static int 161 armperiph_match(device_t parent, cfdata_t cf, void *aux) 162 { 163 struct mainbus_attach_args * const mb = aux; 164 const int base = cf->cf_loc[MAINBUSCF_BASE]; 165 const int size = cf->cf_loc[MAINBUSCF_SIZE]; 166 const int dack = cf->cf_loc[MAINBUSCF_DACK]; 167 const int irq = cf->cf_loc[MAINBUSCF_IRQ]; 168 const int intrbase = cf->cf_loc[MAINBUSCF_INTRBASE]; 169 170 if (attached) 171 return 0; 172 173 if (base != MAINBUSCF_BASE_DEFAULT || base != mb->mb_iobase 174 || size != MAINBUSCF_SIZE_DEFAULT || size != mb->mb_iosize 175 || dack != MAINBUSCF_DACK_DEFAULT || dack != mb->mb_drq 176 || irq != MAINBUSCF_IRQ_DEFAULT || irq != mb->mb_irq 177 || intrbase != MAINBUSCF_INTRBASE_DEFAULT 178 || intrbase != mb->mb_intrbase) 179 return 0; 180 181 if (!CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid)) 182 return 0; 183 184 if (armreg_cbar_read() == 0) 185 return 0; 186 187 if (armperiph_find_config() == NULL) 188 return 0; 189 190 return 1; 191 } 192 193 static void 194 armperiph_attach(device_t parent, device_t self, void *aux) 195 { 196 struct armperiph_softc * const sc = device_private(self); 197 struct mainbus_attach_args * const mb = aux; 198 bus_addr_t cbar = armreg_cbar_read(); 199 const struct mpcore_config * const cfg = armperiph_find_config(); 200 prop_dictionary_t prop = device_properties(self); 201 uint32_t cbar_override; 202 203 if (prop_dictionary_get_uint32(prop, "cbar", &cbar_override)) 204 cbar = (bus_addr_t)cbar_override; 205 206 /* 207 * The normal mainbus bus space will not work for us so the port's 208 * device_register must have replaced it with one that will work. 209 */ 210 sc->sc_dev = self; 211 sc->sc_memt = mb->mb_iot; 212 213 int error = bus_space_map(sc->sc_memt, cbar, cfg->cfg_cbar_size, 0, 214 &sc->sc_memh); 215 if (error) { 216 aprint_normal(": error mapping registers at %#lx: %d\n", 217 cbar, error); 218 return; 219 } 220 aprint_normal("\n"); 221 222 /* 223 * Let's try to attach any children we may have. 224 */ 225 for (size_t i = 0; cfg->cfg_devices[i].pi_name[0] != 0; i++) { 226 struct mpcore_attach_args mpcaa = { 227 .mpcaa_name = cfg->cfg_devices[i].pi_name, 228 .mpcaa_memt = sc->sc_memt, 229 .mpcaa_memh = sc->sc_memh, 230 .mpcaa_off1 = cfg->cfg_devices[i].pi_off1, 231 .mpcaa_off2 = cfg->cfg_devices[i].pi_off2, 232 }; 233 #if defined(CPU_CORTEXA9) 234 if (strcmp(mpcaa.mpcaa_name, "arma9tmr") == 0) 235 mpcaa.mpcaa_irq = IRQ_A9TMR_PPI_GTIMER; 236 #endif 237 #if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15) || defined(CPU_CORTEXA57) 238 if (strcmp(mpcaa.mpcaa_name, "armgtmr") == 0) { 239 mpcaa.mpcaa_irq = IRQ_GTMR_PPI_VTIMER; 240 } 241 #endif 242 243 config_found(self, &mpcaa, NULL); 244 } 245 attached = true; 246 } 247
Indexes created Tue Sep 23 14:10:03 GMT 2025