armperiph.c revision 1.2
1 /*- 2 * Copyright (c) 2012 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas of 3am Software Foundry. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include "locators.h" 31 32 #include <sys/cdefs.h> 33 34 __KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.2 2012/09/02 16:55:10 matt Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/device.h> 38 39 #include "ioconf.h" 40 41 #include <arm/mainbus/mainbus.h> 42 #include <arm/cortex/mpcore_var.h> 43 44 static int armperiph_match(device_t, cfdata_t, void *); 45 static void armperiph_attach(device_t, device_t, void *); 46 47 static bool attached; 48 49 struct armperiph_softc { 50 device_t sc_dev; 51 bus_space_tag_t sc_memt; 52 bus_space_handle_t sc_memh; 53 }; 54 55 #ifdef CPU_CORTEXA5 56 static const char * const a5_devices[] = { 57 "armscu", "armgic", NULL 58 }; 59 #endif 60 61 #ifdef CPU_CORTEXA7 62 static const char * const a7_devices[] = { 63 "armgic", NULL 64 }; 65 #endif 66 67 #ifdef CPU_CORTEXA9 68 static const char * const a9_devices[] = { 69 "armscu", "arml2cc", "armgic", "a9tmr", "a9wdt", NULL 70 }; 71 #endif 72 73 static const struct mpcore_config { 74 const char * const *cfg_devices; 75 uint32_t cfg_cpuid; 76 uint32_t cfg_cbar_size; 77 } configs[] = { 78 #ifdef CPU_CORTEXA5 79 { a5_devices, 0x410fc050, 8192 }, 80 #endif 81 #ifdef CPU_CORTEXA7 82 { a7_devices, 0x410fc070, 32768 }, 83 #endif 84 #ifdef CPU_CORTEXA9 85 { a9_devices, 0x410fc090, 3*4096 }, 86 #endif 87 #ifdef CPU_CORTEXA15 88 { a15_devices, 0x410fc0f0, 32768 }, 89 #endif 90 }; 91 92 static const struct mpcore_config * 93 armperiph_find_config(void) 94 { 95 const uint32_t arm_cpuid = curcpu()->ci_arm_cpuid & 0xff0ff0f0; 96 for (size_t i = 0; i < __arraycount(configs); i++) { 97 if (arm_cpuid == configs[i].cfg_cpuid) { 98 return configs + i; 99 } 100 } 101 102 return NULL; 103 } 104 105 CFATTACH_DECL_NEW(armperiph, sizeof(struct armperiph_softc), 106 armperiph_match, armperiph_attach, NULL, NULL); 107 108 static int 109 armperiph_match(device_t parent, cfdata_t cf, void *aux) 110 { 111 struct mainbus_attach_args * const mb = aux; 112 const int base = cf->cf_loc[MAINBUSCF_BASE]; 113 const int size = cf->cf_loc[MAINBUSCF_SIZE]; 114 const int dack = cf->cf_loc[MAINBUSCF_DACK]; 115 const int irq = cf->cf_loc[MAINBUSCF_IRQ]; 116 const int intrbase = cf->cf_loc[MAINBUSCF_INTRBASE]; 117 118 if (attached) 119 return 0; 120 121 if (base != MAINBUSCF_BASE_DEFAULT || base != mb->mb_iobase 122 || size != MAINBUSCF_SIZE_DEFAULT || size != mb->mb_iosize 123 || dack != MAINBUSCF_DACK_DEFAULT || dack != mb->mb_drq 124 || irq != MAINBUSCF_IRQ_DEFAULT || irq != mb->mb_irq 125 || intrbase != MAINBUSCF_INTRBASE_DEFAULT 126 || intrbase != mb->mb_intrbase) 127 return 0; 128 129 if (!CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid)) 130 return 0; 131 132 if (armreg_cbar_read() == 0) 133 return 0; 134 135 if (armperiph_find_config() == NULL) 136 return 0; 137 138 return 1; 139 } 140 141 static void 142 armperiph_attach(device_t parent, device_t self, void *aux) 143 { 144 struct armperiph_softc * const sc = device_private(self); 145 struct mainbus_attach_args * const mb = aux; 146 bus_addr_t cbar = armreg_cbar_read(); 147 const struct mpcore_config * const cfg = armperiph_find_config(); 148 149 /* 150 * The normal mainbus bus space will not work for us so the port's 151 * device_register must have replaced it with one that will work. 152 */ 153 sc->sc_dev = self; 154 sc->sc_memt = mb->mb_iot; 155 156 int error = bus_space_map(sc->sc_memt, cbar, cfg->cfg_cbar_size, 0, 157 &sc->sc_memh); 158 if (error) { 159 aprint_normal(": error mapping registers at %#lx: %d\n", 160 cbar, error); 161 return; 162 } 163 aprint_normal("\n"); 164 165 /* 166 * Let's try to attach any children we may have. 167 */ 168 for (size_t i = 0; cfg->cfg_devices[i] != NULL; i++) { 169 struct mpcore_attach_args mpcaa = { 170 .mpcaa_name = cfg->cfg_devices[i], 171 .mpcaa_memt = sc->sc_memt, 172 .mpcaa_memh = sc->sc_memh, 173 }; 174 175 config_found(self, &mpcaa, NULL); 176 } 177 } 178
Indexes created Tue Sep 23 07:09:52 GMT 2025