gic_v2m.c revision 1.6
1 /* $NetBSD: gic_v2m.c,v 1.6 2019/06/17 00:49:55 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jared McNeill <jmcneill (at) invisible.ca>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #define _INTR_PRIVATE 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.6 2019/06/17 00:49:55 jmcneill Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/kmem.h> 39 #include <sys/bitops.h> 40 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 44 #include <arm/pic/picvar.h> 45 #include <arm/cortex/gic_v2m.h> 46 47 static int 48 gic_v2m_msi_alloc_spi(struct gic_v2m_frame *frame, int count, 49 const struct pci_attach_args *pa) 50 { 51 int spi, n; 52 53 for (spi = frame->frame_base; 54 spi < frame->frame_base + frame->frame_count; ) { 55 if (frame->frame_pa[spi] == NULL) { 56 for (n = 1; n < count; n++) 57 if (frame->frame_pa[spi + n] != NULL) 58 goto next_spi; 59 60 for (n = 0; n < count; n++) 61 frame->frame_pa[spi + n] = pa; 62 63 return spi; 64 } 65 next_spi: 66 spi += count; 67 } 68 69 return -1; 70 } 71 72 static void 73 gic_v2m_msi_free_spi(struct gic_v2m_frame *frame, int spi) 74 { 75 frame->frame_pa[spi] = NULL; 76 } 77 78 static int 79 gic_v2m_msi_available_spi(struct gic_v2m_frame *frame) 80 { 81 int spi, n; 82 83 for (spi = frame->frame_base, n = 0; 84 spi < frame->frame_base + frame->frame_count; 85 spi++) { 86 if (frame->frame_pa[spi] == NULL) 87 n++; 88 } 89 90 return n; 91 } 92 93 static void 94 gic_v2m_msi_enable(struct gic_v2m_frame *frame, int spi, int count) 95 { 96 const struct pci_attach_args *pa = frame->frame_pa[spi]; 97 pci_chipset_tag_t pc = pa->pa_pc; 98 pcitag_t tag = pa->pa_tag; 99 pcireg_t ctl; 100 int off; 101 102 if (!pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL)) 103 panic("gic_v2m_msi_enable: device is not MSI-capable"); 104 105 ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 106 ctl &= ~PCI_MSI_CTL_MSI_ENABLE; 107 pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl); 108 109 ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 110 ctl &= ~PCI_MSI_CTL_MME_MASK; 111 ctl |= __SHIFTIN(ilog2(count), PCI_MSI_CTL_MME_MASK); 112 pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl); 113 114 const uint64_t addr = frame->frame_reg + GIC_MSI_SETSPI; 115 ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 116 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 117 pci_conf_write(pc, tag, off + PCI_MSI_MADDR64_LO, 118 addr & 0xffffffff); 119 pci_conf_write(pc, tag, off + PCI_MSI_MADDR64_HI, 120 (addr >> 32) & 0xffffffff); 121 pci_conf_write(pc, tag, off + PCI_MSI_MDATA64, spi); 122 } else { 123 pci_conf_write(pc, tag, off + PCI_MSI_MADDR, 124 addr & 0xffffffff); 125 pci_conf_write(pc, tag, off + PCI_MSI_MDATA, spi); 126 } 127 ctl |= PCI_MSI_CTL_MSI_ENABLE; 128 pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl); 129 } 130 131 static void 132 gic_v2m_msi_disable(struct gic_v2m_frame *frame, int spi) 133 { 134 const struct pci_attach_args *pa = frame->frame_pa[spi]; 135 pci_chipset_tag_t pc = pa->pa_pc; 136 pcitag_t tag = pa->pa_tag; 137 pcireg_t ctl; 138 int off; 139 140 if (!pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL)) 141 panic("gic_v2m_msi_disable: device is not MSI-capable"); 142 143 ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 144 ctl &= ~PCI_MSI_CTL_MSI_ENABLE; 145 pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl); 146 } 147 148 static void 149 gic_v2m_msix_enable(struct gic_v2m_frame *frame, int spi, int msix_vec, 150 bus_space_tag_t bst, bus_space_handle_t bsh) 151 { 152 const struct pci_attach_args *pa = frame->frame_pa[spi]; 153 pci_chipset_tag_t pc = pa->pa_pc; 154 pcitag_t tag = pa->pa_tag; 155 pcireg_t ctl; 156 int off; 157 158 if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL)) 159 panic("gic_v2m_msix_enable: device is not MSI-X-capable"); 160 161 ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); 162 ctl &= ~PCI_MSIX_CTL_ENABLE; 163 pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl); 164 165 const uint64_t addr = frame->frame_reg + GIC_MSI_SETSPI; 166 const uint64_t entry_base = PCI_MSIX_TABLE_ENTRY_SIZE * msix_vec; 167 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO, (uint32_t)addr); 168 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_HI, (uint32_t)(addr >> 32)); 169 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_DATA, spi); 170 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, 0); 171 172 ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); 173 ctl |= PCI_MSIX_CTL_ENABLE; 174 pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl); 175 } 176 177 static void 178 gic_v2m_msix_disable(struct gic_v2m_frame *frame, int spi) 179 { 180 const struct pci_attach_args *pa = frame->frame_pa[spi]; 181 pci_chipset_tag_t pc = pa->pa_pc; 182 pcitag_t tag = pa->pa_tag; 183 pcireg_t ctl; 184 int off; 185 186 if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL)) 187 panic("gic_v2m_msix_disable: device is not MSI-X-capable"); 188 189 ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); 190 ctl &= ~PCI_MSIX_CTL_ENABLE; 191 pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl); 192 } 193 194 static pci_intr_handle_t * 195 gic_v2m_msi_alloc(struct arm_pci_msi *msi, int *count, 196 const struct pci_attach_args *pa, bool exact) 197 { 198 struct gic_v2m_frame * const frame = msi->msi_priv; 199 pci_intr_handle_t *vectors; 200 int n, off; 201 202 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI, &off, NULL)) 203 return NULL; 204 205 const int avail = gic_v2m_msi_available_spi(frame); 206 if (exact && *count > avail) 207 return NULL; 208 209 while (*count > avail) { 210 if (avail < *count) 211 (*count) >>= 1; 212 } 213 if (*count == 0) 214 return NULL; 215 216 const int spi_base = gic_v2m_msi_alloc_spi(frame, *count, pa); 217 if (spi_base == -1) 218 return NULL; 219 220 vectors = kmem_alloc(sizeof(*vectors) * *count, KM_SLEEP); 221 for (n = 0; n < *count; n++) { 222 const int spi = spi_base + n; 223 vectors[n] = ARM_PCI_INTR_MSI | 224 __SHIFTIN(spi, ARM_PCI_INTR_IRQ) | 225 __SHIFTIN(n, ARM_PCI_INTR_MSI_VEC) | 226 __SHIFTIN(msi->msi_id, ARM_PCI_INTR_FRAME); 227 } 228 229 gic_v2m_msi_enable(frame, spi_base, *count); 230 231 return vectors; 232 } 233 234 static pci_intr_handle_t * 235 gic_v2m_msix_alloc(struct arm_pci_msi *msi, u_int *table_indexes, int *count, 236 const struct pci_attach_args *pa, bool exact) 237 { 238 struct gic_v2m_frame * const frame = msi->msi_priv; 239 pci_intr_handle_t *vectors; 240 bus_space_tag_t bst; 241 bus_space_handle_t bsh; 242 bus_size_t bsz; 243 uint32_t table_offset, table_size; 244 int n, off, bar, error; 245 pcireg_t tbl; 246 247 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, &off, NULL)) 248 return NULL; 249 250 const int avail = gic_v2m_msi_available_spi(frame); 251 if (exact && *count > avail) 252 return NULL; 253 254 while (*count > avail) { 255 if (avail < *count) 256 (*count) >>= 1; 257 } 258 if (*count == 0) 259 return NULL; 260 261 tbl = pci_conf_read(pa->pa_pc, pa->pa_tag, off + PCI_MSIX_TBLOFFSET); 262 bar = PCI_BAR0 + (4 * (tbl & PCI_MSIX_PBABIR_MASK)); 263 table_offset = tbl & PCI_MSIX_TBLOFFSET_MASK; 264 table_size = pci_msix_count(pa->pa_pc, pa->pa_tag) * PCI_MSIX_TABLE_ENTRY_SIZE; 265 if (table_size == 0) 266 return NULL; 267 268 error = pci_mapreg_submap(pa, bar, pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar), 269 BUS_SPACE_MAP_LINEAR, roundup(table_size, PAGE_SIZE), table_offset, 270 &bst, &bsh, NULL, &bsz); 271 if (error) 272 return NULL; 273 274 const int spi_base = gic_v2m_msi_alloc_spi(frame, *count, pa); 275 if (spi_base == -1) { 276 bus_space_unmap(bst, bsh, bsz); 277 return NULL; 278 } 279 280 vectors = kmem_alloc(sizeof(*vectors) * *count, KM_SLEEP); 281 for (n = 0; n < *count; n++) { 282 const int spi = spi_base + n; 283 const int msix_vec = table_indexes ? table_indexes[n] : n; 284 vectors[msix_vec] = ARM_PCI_INTR_MSIX | 285 __SHIFTIN(spi, ARM_PCI_INTR_IRQ) | 286 __SHIFTIN(msix_vec, ARM_PCI_INTR_MSI_VEC) | 287 __SHIFTIN(msi->msi_id, ARM_PCI_INTR_FRAME); 288 289 gic_v2m_msix_enable(frame, spi, msix_vec, bst, bsh); 290 } 291 292 bus_space_unmap(bst, bsh, bsz); 293 294 return vectors; 295 } 296 297 static void * 298 gic_v2m_msi_intr_establish(struct arm_pci_msi *msi, 299 pci_intr_handle_t ih, int ipl, int (*func)(void *), void *arg, const char *xname) 300 { 301 struct gic_v2m_frame * const frame = msi->msi_priv; 302 303 const int spi = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ); 304 const int mpsafe = (ih & ARM_PCI_INTR_MPSAFE) ? IST_MPSAFE : 0; 305 306 return pic_establish_intr(frame->frame_pic, spi, ipl, 307 IST_EDGE | mpsafe, func, arg, xname); 308 } 309 310 static void 311 gic_v2m_msi_intr_release(struct arm_pci_msi *msi, pci_intr_handle_t *pih, 312 int count) 313 { 314 struct gic_v2m_frame * const frame = msi->msi_priv; 315 int n; 316 317 for (n = 0; n < count; n++) { 318 const int spi = __SHIFTOUT(pih[n], ARM_PCI_INTR_IRQ); 319 if (pih[n] & ARM_PCI_INTR_MSIX) 320 gic_v2m_msix_disable(frame, spi); 321 if (pih[n] & ARM_PCI_INTR_MSI) 322 gic_v2m_msi_disable(frame, spi); 323 gic_v2m_msi_free_spi(frame, spi); 324 struct intrsource * const is = 325 frame->frame_pic->pic_sources[spi]; 326 if (is != NULL) 327 pic_disestablish_source(is); 328 } 329 } 330 331 int 332 gic_v2m_init(struct gic_v2m_frame *frame, device_t dev, uint32_t frame_id) 333 { 334 struct arm_pci_msi *msi = &frame->frame_msi; 335 336 msi->msi_dev = dev; 337 msi->msi_priv = frame; 338 msi->msi_alloc = gic_v2m_msi_alloc; 339 msi->msix_alloc = gic_v2m_msix_alloc; 340 msi->msi_intr_establish = gic_v2m_msi_intr_establish; 341 msi->msi_intr_release = gic_v2m_msi_intr_release; 342 343 return arm_pci_msi_add(msi); 344 } 345
Indexes created Tue Oct 07 21:09:53 GMT 2025