gicv3.c revision 1.2.2.2
1 1.2.2.2 pgoyette /* $NetBSD: gicv3.c,v 1.2.2.2 2018/09/06 06:55:26 pgoyette Exp $ */ 2 1.2.2.2 pgoyette 3 1.2.2.2 pgoyette /*- 4 1.2.2.2 pgoyette * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 1.2.2.2 pgoyette * All rights reserved. 6 1.2.2.2 pgoyette * 7 1.2.2.2 pgoyette * Redistribution and use in source and binary forms, with or without 8 1.2.2.2 pgoyette * modification, are permitted provided that the following conditions 9 1.2.2.2 pgoyette * are met: 10 1.2.2.2 pgoyette * 1. Redistributions of source code must retain the above copyright 11 1.2.2.2 pgoyette * notice, this list of conditions and the following disclaimer. 12 1.2.2.2 pgoyette * 2. Redistributions in binary form must reproduce the above copyright 13 1.2.2.2 pgoyette * notice, this list of conditions and the following disclaimer in the 14 1.2.2.2 pgoyette * documentation and/or other materials provided with the distribution. 15 1.2.2.2 pgoyette * 16 1.2.2.2 pgoyette * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.2.2.2 pgoyette * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.2.2.2 pgoyette * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.2.2.2 pgoyette * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.2.2.2 pgoyette * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.2.2.2 pgoyette * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.2.2.2 pgoyette * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.2.2.2 pgoyette * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.2.2.2 pgoyette * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.2.2.2 pgoyette * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.2.2.2 pgoyette * SUCH DAMAGE. 27 1.2.2.2 pgoyette */ 28 1.2.2.2 pgoyette 29 1.2.2.2 pgoyette #include "opt_multiprocessor.h" 30 1.2.2.2 pgoyette 31 1.2.2.2 pgoyette #define _INTR_PRIVATE 32 1.2.2.2 pgoyette 33 1.2.2.2 pgoyette #include <sys/cdefs.h> 34 1.2.2.2 pgoyette __KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.2.2.2 2018/09/06 06:55:26 pgoyette Exp $"); 35 1.2.2.2 pgoyette 36 1.2.2.2 pgoyette #include <sys/param.h> 37 1.2.2.2 pgoyette #include <sys/kernel.h> 38 1.2.2.2 pgoyette #include <sys/bus.h> 39 1.2.2.2 pgoyette #include <sys/device.h> 40 1.2.2.2 pgoyette #include <sys/intr.h> 41 1.2.2.2 pgoyette #include <sys/systm.h> 42 1.2.2.2 pgoyette #include <sys/cpu.h> 43 1.2.2.2 pgoyette 44 1.2.2.2 pgoyette #include <arm/locore.h> 45 1.2.2.2 pgoyette #include <arm/armreg.h> 46 1.2.2.2 pgoyette 47 1.2.2.2 pgoyette #include <arm/cortex/gicv3.h> 48 1.2.2.2 pgoyette #include <arm/cortex/gic_reg.h> 49 1.2.2.2 pgoyette 50 1.2.2.2 pgoyette #define PICTOSOFTC(pic) \ 51 1.2.2.2 pgoyette ((void *)((uintptr_t)(pic) - offsetof(struct gicv3_softc, sc_pic))) 52 1.2.2.2 pgoyette 53 1.2.2.2 pgoyette #define IPL_TO_PRIORITY(ipl) ((IPL_HIGH - (ipl)) << 4) 54 1.2.2.2 pgoyette 55 1.2.2.2 pgoyette static struct gicv3_softc *gicv3_softc; 56 1.2.2.2 pgoyette 57 1.2.2.2 pgoyette static inline uint32_t 58 1.2.2.2 pgoyette gicd_read_4(struct gicv3_softc *sc, bus_size_t reg) 59 1.2.2.2 pgoyette { 60 1.2.2.2 pgoyette return bus_space_read_4(sc->sc_bst, sc->sc_bsh_d, reg); 61 1.2.2.2 pgoyette } 62 1.2.2.2 pgoyette 63 1.2.2.2 pgoyette static inline void 64 1.2.2.2 pgoyette gicd_write_4(struct gicv3_softc *sc, bus_size_t reg, uint32_t val) 65 1.2.2.2 pgoyette { 66 1.2.2.2 pgoyette bus_space_write_4(sc->sc_bst, sc->sc_bsh_d, reg, val); 67 1.2.2.2 pgoyette } 68 1.2.2.2 pgoyette 69 1.2.2.2 pgoyette static inline void 70 1.2.2.2 pgoyette gicd_write_8(struct gicv3_softc *sc, bus_size_t reg, uint64_t val) 71 1.2.2.2 pgoyette { 72 1.2.2.2 pgoyette bus_space_write_8(sc->sc_bst, sc->sc_bsh_d, reg, val); 73 1.2.2.2 pgoyette } 74 1.2.2.2 pgoyette 75 1.2.2.2 pgoyette static inline uint32_t 76 1.2.2.2 pgoyette gicr_read_4(struct gicv3_softc *sc, u_int index, bus_size_t reg) 77 1.2.2.2 pgoyette { 78 1.2.2.2 pgoyette KASSERT(index < sc->sc_bsh_r_count); 79 1.2.2.2 pgoyette return bus_space_read_4(sc->sc_bst, sc->sc_bsh_r[index], reg); 80 1.2.2.2 pgoyette } 81 1.2.2.2 pgoyette 82 1.2.2.2 pgoyette static inline void 83 1.2.2.2 pgoyette gicr_write_4(struct gicv3_softc *sc, u_int index, bus_size_t reg, uint32_t val) 84 1.2.2.2 pgoyette { 85 1.2.2.2 pgoyette KASSERT(index < sc->sc_bsh_r_count); 86 1.2.2.2 pgoyette bus_space_write_4(sc->sc_bst, sc->sc_bsh_r[index], reg, val); 87 1.2.2.2 pgoyette } 88 1.2.2.2 pgoyette 89 1.2.2.2 pgoyette static inline uint64_t 90 1.2.2.2 pgoyette gicr_read_8(struct gicv3_softc *sc, u_int index, bus_size_t reg) 91 1.2.2.2 pgoyette { 92 1.2.2.2 pgoyette KASSERT(index < sc->sc_bsh_r_count); 93 1.2.2.2 pgoyette return bus_space_read_8(sc->sc_bst, sc->sc_bsh_r[index], reg); 94 1.2.2.2 pgoyette } 95 1.2.2.2 pgoyette 96 1.2.2.2 pgoyette static inline void 97 1.2.2.2 pgoyette gicr_write_8(struct gicv3_softc *sc, u_int index, bus_size_t reg, uint64_t val) 98 1.2.2.2 pgoyette { 99 1.2.2.2 pgoyette KASSERT(index < sc->sc_bsh_r_count); 100 1.2.2.2 pgoyette bus_space_write_8(sc->sc_bst, sc->sc_bsh_r[index], reg, val); 101 1.2.2.2 pgoyette } 102 1.2.2.2 pgoyette 103 1.2.2.2 pgoyette static void 104 1.2.2.2 pgoyette gicv3_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t mask) 105 1.2.2.2 pgoyette { 106 1.2.2.2 pgoyette struct gicv3_softc * const sc = PICTOSOFTC(pic); 107 1.2.2.2 pgoyette struct cpu_info * const ci = curcpu(); 108 1.2.2.2 pgoyette const u_int group = irqbase / 32; 109 1.2.2.2 pgoyette 110 1.2.2.2 pgoyette if (group == 0) { 111 1.2.2.2 pgoyette sc->sc_enabled_sgippi |= mask; 112 1.2.2.2 pgoyette gicr_write_4(sc, ci->ci_gic_redist, GICR_ISENABLER0, mask); 113 1.2.2.2 pgoyette while (gicr_read_4(sc, ci->ci_gic_redist, GICR_CTRL) & GICR_CTRL_RWP) 114 1.2.2.2 pgoyette ; 115 1.2.2.2 pgoyette } else { 116 1.2.2.2 pgoyette gicd_write_4(sc, GICD_ISENABLERn(group), mask); 117 1.2.2.2 pgoyette while (gicd_read_4(sc, GICD_CTRL) & GICD_CTRL_RWP) 118 1.2.2.2 pgoyette ; 119 1.2.2.2 pgoyette } 120 1.2.2.2 pgoyette } 121 1.2.2.2 pgoyette 122 1.2.2.2 pgoyette static void 123 1.2.2.2 pgoyette gicv3_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t mask) 124 1.2.2.2 pgoyette { 125 1.2.2.2 pgoyette struct gicv3_softc * const sc = PICTOSOFTC(pic); 126 1.2.2.2 pgoyette struct cpu_info * const ci = curcpu(); 127 1.2.2.2 pgoyette const u_int group = irqbase / 32; 128 1.2.2.2 pgoyette 129 1.2.2.2 pgoyette if (group == 0) { 130 1.2.2.2 pgoyette sc->sc_enabled_sgippi &= ~mask; 131 1.2.2.2 pgoyette gicr_write_4(sc, ci->ci_gic_redist, GICR_ICENABLER0, mask); 132 1.2.2.2 pgoyette while (gicr_read_4(sc, ci->ci_gic_redist, GICR_CTRL) & GICR_CTRL_RWP) 133 1.2.2.2 pgoyette ; 134 1.2.2.2 pgoyette } else { 135 1.2.2.2 pgoyette gicd_write_4(sc, GICD_ICENABLERn(group), mask); 136 1.2.2.2 pgoyette while (gicd_read_4(sc, GICD_CTRL) & GICD_CTRL_RWP) 137 1.2.2.2 pgoyette ; 138 1.2.2.2 pgoyette } 139 1.2.2.2 pgoyette } 140 1.2.2.2 pgoyette 141 1.2.2.2 pgoyette static void 142 1.2.2.2 pgoyette gicv3_establish_irq(struct pic_softc *pic, struct intrsource *is) 143 1.2.2.2 pgoyette { 144 1.2.2.2 pgoyette struct gicv3_softc * const sc = PICTOSOFTC(pic); 145 1.2.2.2 pgoyette const u_int group = is->is_irq / 32; 146 1.2.2.2 pgoyette uint32_t ipriority, icfg; 147 1.2.2.2 pgoyette uint64_t irouter; 148 1.2.2.2 pgoyette u_int n; 149 1.2.2.2 pgoyette 150 1.2.2.2 pgoyette const u_int ipriority_val = 0x80 | IPL_TO_PRIORITY(is->is_ipl); 151 1.2.2.2 pgoyette const u_int ipriority_shift = (is->is_irq & 0x3) * 8; 152 1.2.2.2 pgoyette const u_int icfg_shift = (is->is_irq & 0xf) * 2; 153 1.2.2.2 pgoyette 154 1.2.2.2 pgoyette if (group == 0) { 155 1.2.2.2 pgoyette /* SGIs and PPIs are always MP-safe */ 156 1.2.2.2 pgoyette is->is_mpsafe = true; 157 1.2.2.2 pgoyette 158 1.2.2.2 pgoyette /* Update interrupt configuration and priority on all redistributors */ 159 1.2.2.2 pgoyette for (n = 0; n < sc->sc_bsh_r_count; n++) { 160 1.2.2.2 pgoyette icfg = gicr_read_4(sc, n, GICR_ICFGRn(is->is_irq / 16)); 161 1.2.2.2 pgoyette if (is->is_type == IST_LEVEL) 162 1.2.2.2 pgoyette icfg &= ~(0x2 << icfg_shift); 163 1.2.2.2 pgoyette if (is->is_type == IST_EDGE) 164 1.2.2.2 pgoyette icfg |= (0x2 << icfg_shift); 165 1.2.2.2 pgoyette gicr_write_4(sc, n, GICR_ICFGRn(is->is_irq / 16), icfg); 166 1.2.2.2 pgoyette 167 1.2.2.2 pgoyette ipriority = gicr_read_4(sc, n, GICR_IPRIORITYRn(is->is_irq / 4)); 168 1.2.2.2 pgoyette ipriority &= ~(0xff << ipriority_shift); 169 1.2.2.2 pgoyette ipriority |= (ipriority_val << ipriority_shift); 170 1.2.2.2 pgoyette gicr_write_4(sc, n, GICR_IPRIORITYRn(is->is_irq / 4), ipriority); 171 1.2.2.2 pgoyette } 172 1.2.2.2 pgoyette } else { 173 1.2.2.2 pgoyette if (is->is_mpsafe) { 174 1.2.2.2 pgoyette /* Route MP-safe interrupts to all participating PEs */ 175 1.2.2.2 pgoyette irouter = GICD_IROUTER_Interrupt_Routing_mode; 176 1.2.2.2 pgoyette } else { 177 1.2.2.2 pgoyette /* Route non-MP-safe interrupts to the primary PE only */ 178 1.2.2.2 pgoyette irouter = sc->sc_default_irouter; 179 1.2.2.2 pgoyette } 180 1.2.2.2 pgoyette gicd_write_8(sc, GICD_IROUTER(is->is_irq), irouter); 181 1.2.2.2 pgoyette 182 1.2.2.2 pgoyette /* Update interrupt configuration */ 183 1.2.2.2 pgoyette icfg = gicd_read_4(sc, GICD_ICFGRn(is->is_irq / 16)); 184 1.2.2.2 pgoyette if (is->is_type == IST_LEVEL) 185 1.2.2.2 pgoyette icfg &= ~(0x2 << icfg_shift); 186 1.2.2.2 pgoyette if (is->is_type == IST_EDGE) 187 1.2.2.2 pgoyette icfg |= (0x2 << icfg_shift); 188 1.2.2.2 pgoyette gicd_write_4(sc, GICD_ICFGRn(is->is_irq / 16), icfg); 189 1.2.2.2 pgoyette 190 1.2.2.2 pgoyette /* Update interrupt priority */ 191 1.2.2.2 pgoyette ipriority = gicd_read_4(sc, GICD_IPRIORITYRn(is->is_irq / 4)); 192 1.2.2.2 pgoyette ipriority &= ~(0xff << ipriority_shift); 193 1.2.2.2 pgoyette ipriority |= (ipriority_val << ipriority_shift); 194 1.2.2.2 pgoyette gicd_write_4(sc, GICD_IPRIORITYRn(is->is_irq / 4), ipriority); 195 1.2.2.2 pgoyette } 196 1.2.2.2 pgoyette } 197 1.2.2.2 pgoyette 198 1.2.2.2 pgoyette static void 199 1.2.2.2 pgoyette gicv3_set_priority(struct pic_softc *pic, int ipl) 200 1.2.2.2 pgoyette { 201 1.2.2.2 pgoyette icc_pmr_write(IPL_TO_PRIORITY(ipl)); 202 1.2.2.2 pgoyette } 203 1.2.2.2 pgoyette 204 1.2.2.2 pgoyette static void 205 1.2.2.2 pgoyette gicv3_dist_enable(struct gicv3_softc *sc) 206 1.2.2.2 pgoyette { 207 1.2.2.2 pgoyette uint32_t gicd_ctrl; 208 1.2.2.2 pgoyette u_int n; 209 1.2.2.2 pgoyette 210 1.2.2.2 pgoyette /* Disable the distributor */ 211 1.2.2.2 pgoyette gicd_write_4(sc, GICD_CTRL, 0); 212 1.2.2.2 pgoyette 213 1.2.2.2 pgoyette /* Wait for register write to complete */ 214 1.2.2.2 pgoyette while (gicd_read_4(sc, GICD_CTRL) & GICD_CTRL_RWP) 215 1.2.2.2 pgoyette ; 216 1.2.2.2 pgoyette 217 1.2.2.2 pgoyette /* Clear all INTID enable bits */ 218 1.2.2.2 pgoyette for (n = 32; n < sc->sc_pic.pic_maxsources; n += 32) 219 1.2.2.2 pgoyette gicd_write_4(sc, GICD_ICENABLERn(n / 32), ~0); 220 1.2.2.2 pgoyette 221 1.2.2.2 pgoyette /* Set default priorities to lowest */ 222 1.2.2.2 pgoyette for (n = 32; n < sc->sc_pic.pic_maxsources; n += 4) 223 1.2.2.2 pgoyette gicd_write_4(sc, GICD_IPRIORITYRn(n / 4), ~0); 224 1.2.2.2 pgoyette 225 1.2.2.2 pgoyette /* Set all interrupts to G1NS */ 226 1.2.2.2 pgoyette for (n = 32; n < sc->sc_pic.pic_maxsources; n += 32) { 227 1.2.2.2 pgoyette gicd_write_4(sc, GICD_IGROUPRn(n / 32), ~0); 228 1.2.2.2 pgoyette gicd_write_4(sc, GICD_IGRPMODRn(n / 32), 0); 229 1.2.2.2 pgoyette } 230 1.2.2.2 pgoyette 231 1.2.2.2 pgoyette /* Set all interrupts level-sensitive by default */ 232 1.2.2.2 pgoyette for (n = 32; n < sc->sc_pic.pic_maxsources; n += 16) 233 1.2.2.2 pgoyette gicd_write_4(sc, GICD_ICFGRn(n / 16), 0); 234 1.2.2.2 pgoyette 235 1.2.2.2 pgoyette /* Wait for register writes to complete */ 236 1.2.2.2 pgoyette while (gicd_read_4(sc, GICD_CTRL) & GICD_CTRL_RWP) 237 1.2.2.2 pgoyette ; 238 1.2.2.2 pgoyette 239 1.2.2.2 pgoyette /* Enable Affinity routing and G1NS interrupts */ 240 1.2.2.2 pgoyette gicd_ctrl = GICD_CTRL_EnableGrp1NS | GICD_CTRL_Enable | GICD_CTRL_ARE_NS; 241 1.2.2.2 pgoyette gicd_write_4(sc, GICD_CTRL, gicd_ctrl); 242 1.2.2.2 pgoyette } 243 1.2.2.2 pgoyette 244 1.2.2.2 pgoyette static void 245 1.2.2.2 pgoyette gicv3_redist_enable(struct gicv3_softc *sc, struct cpu_info *ci) 246 1.2.2.2 pgoyette { 247 1.2.2.2 pgoyette uint32_t icfg; 248 1.2.2.2 pgoyette u_int n, o; 249 1.2.2.2 pgoyette 250 1.2.2.2 pgoyette /* Clear INTID enable bits */ 251 1.2.2.2 pgoyette gicr_write_4(sc, ci->ci_gic_redist, GICR_ICENABLER0, ~0); 252 1.2.2.2 pgoyette 253 1.2.2.2 pgoyette /* Wait for register write to complete */ 254 1.2.2.2 pgoyette while (gicr_read_4(sc, ci->ci_gic_redist, GICR_CTRL) & GICR_CTRL_RWP) 255 1.2.2.2 pgoyette ; 256 1.2.2.2 pgoyette 257 1.2.2.2 pgoyette /* Set default priorities */ 258 1.2.2.2 pgoyette for (n = 0; n < 32; n += 4) { 259 1.2.2.2 pgoyette uint32_t priority = 0; 260 1.2.2.2 pgoyette size_t byte_shift = 0; 261 1.2.2.2 pgoyette for (o = 0; o < 4; o++, byte_shift += 8) { 262 1.2.2.2 pgoyette struct intrsource * const is = sc->sc_pic.pic_sources[n + o]; 263 1.2.2.2 pgoyette if (is == NULL) 264 1.2.2.2 pgoyette priority |= 0xff << byte_shift; 265 1.2.2.2 pgoyette else { 266 1.2.2.2 pgoyette const u_int ipriority_val = 0x80 | IPL_TO_PRIORITY(is->is_ipl); 267 1.2.2.2 pgoyette priority |= ipriority_val << byte_shift; 268 1.2.2.2 pgoyette } 269 1.2.2.2 pgoyette } 270 1.2.2.2 pgoyette gicr_write_4(sc, ci->ci_gic_redist, GICR_IPRIORITYRn(n / 4), priority); 271 1.2.2.2 pgoyette } 272 1.2.2.2 pgoyette 273 1.2.2.2 pgoyette /* Set all interrupts to G1NS */ 274 1.2.2.2 pgoyette gicr_write_4(sc, ci->ci_gic_redist, GICR_IGROUPR0, ~0); 275 1.2.2.2 pgoyette gicr_write_4(sc, ci->ci_gic_redist, GICR_IGRPMODR0, 0); 276 1.2.2.2 pgoyette 277 1.2.2.2 pgoyette /* Restore PPI configs */ 278 1.2.2.2 pgoyette for (n = 0, icfg = 0; n < 16; n++) { 279 1.2.2.2 pgoyette struct intrsource * const is = sc->sc_pic.pic_sources[16 + n]; 280 1.2.2.2 pgoyette if (is != NULL && is->is_type == IST_EDGE) 281 1.2.2.2 pgoyette icfg |= (0x2 << (n * 2)); 282 1.2.2.2 pgoyette } 283 1.2.2.2 pgoyette gicr_write_4(sc, ci->ci_gic_redist, GICR_ICFGRn(1), icfg); 284 1.2.2.2 pgoyette 285 1.2.2.2 pgoyette /* Restore current enable bits */ 286 1.2.2.2 pgoyette gicr_write_4(sc, ci->ci_gic_redist, GICR_ISENABLER0, sc->sc_enabled_sgippi); 287 1.2.2.2 pgoyette 288 1.2.2.2 pgoyette /* Wait for register write to complete */ 289 1.2.2.2 pgoyette while (gicr_read_4(sc, ci->ci_gic_redist, GICR_CTRL) & GICR_CTRL_RWP) 290 1.2.2.2 pgoyette ; 291 1.2.2.2 pgoyette } 292 1.2.2.2 pgoyette 293 1.2.2.2 pgoyette static uint64_t 294 1.2.2.2 pgoyette gicv3_cpu_identity(void) 295 1.2.2.2 pgoyette { 296 1.2.2.2 pgoyette u_int aff3, aff2, aff1, aff0; 297 1.2.2.2 pgoyette 298 1.2.2.2 pgoyette #ifdef __aarch64__ 299 1.2.2.2 pgoyette const register_t mpidr = reg_mpidr_el1_read(); 300 1.2.2.2 pgoyette aff0 = __SHIFTOUT(mpidr, MPIDR_AFF0); 301 1.2.2.2 pgoyette aff1 = __SHIFTOUT(mpidr, MPIDR_AFF1); 302 1.2.2.2 pgoyette aff2 = __SHIFTOUT(mpidr, MPIDR_AFF2); 303 1.2.2.2 pgoyette aff3 = __SHIFTOUT(mpidr, MPIDR_AFF3); 304 1.2.2.2 pgoyette #else 305 1.2.2.2 pgoyette const register_t mpidr = armreg_mpidr_read(); 306 1.2.2.2 pgoyette aff0 = __SHIFTOUT(mpidr, MPIDR_AFF0); 307 1.2.2.2 pgoyette aff1 = __SHIFTOUT(mpidr, MPIDR_AFF1); 308 1.2.2.2 pgoyette aff2 = __SHIFTOUT(mpidr, MPIDR_AFF2); 309 1.2.2.2 pgoyette aff3 = 0; 310 1.2.2.2 pgoyette #endif 311 1.2.2.2 pgoyette 312 1.2.2.2 pgoyette return __SHIFTIN(aff0, GICR_TYPER_Affinity_Value_Aff0) | 313 1.2.2.2 pgoyette __SHIFTIN(aff1, GICR_TYPER_Affinity_Value_Aff1) | 314 1.2.2.2 pgoyette __SHIFTIN(aff2, GICR_TYPER_Affinity_Value_Aff2) | 315 1.2.2.2 pgoyette __SHIFTIN(aff3, GICR_TYPER_Affinity_Value_Aff3); 316 1.2.2.2 pgoyette } 317 1.2.2.2 pgoyette 318 1.2.2.2 pgoyette static u_int 319 1.2.2.2 pgoyette gicv3_find_redist(struct gicv3_softc *sc) 320 1.2.2.2 pgoyette { 321 1.2.2.2 pgoyette uint64_t gicr_typer; 322 1.2.2.2 pgoyette u_int n; 323 1.2.2.2 pgoyette 324 1.2.2.2 pgoyette const uint64_t cpu_identity = gicv3_cpu_identity(); 325 1.2.2.2 pgoyette 326 1.2.2.2 pgoyette for (n = 0; n < sc->sc_bsh_r_count; n++) { 327 1.2.2.2 pgoyette gicr_typer = gicr_read_8(sc, n, GICR_TYPER); 328 1.2.2.2 pgoyette if ((gicr_typer & GICR_TYPER_Affinity_Value) == cpu_identity) 329 1.2.2.2 pgoyette return n; 330 1.2.2.2 pgoyette } 331 1.2.2.2 pgoyette 332 1.2.2.2 pgoyette const u_int aff0 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff0); 333 1.2.2.2 pgoyette const u_int aff1 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff1); 334 1.2.2.2 pgoyette const u_int aff2 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff2); 335 1.2.2.2 pgoyette const u_int aff3 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff3); 336 1.2.2.2 pgoyette 337 1.2.2.2 pgoyette panic("%s: could not find GICv3 redistributor for cpu %d.%d.%d.%d", 338 1.2.2.2 pgoyette cpu_name(curcpu()), aff3, aff2, aff1, aff0); 339 1.2.2.2 pgoyette } 340 1.2.2.2 pgoyette 341 1.2.2.2 pgoyette static uint64_t 342 1.2.2.2 pgoyette gicv3_sgir(struct gicv3_softc *sc) 343 1.2.2.2 pgoyette { 344 1.2.2.2 pgoyette const uint64_t cpu_identity = gicv3_cpu_identity(); 345 1.2.2.2 pgoyette 346 1.2.2.2 pgoyette const u_int aff0 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff0); 347 1.2.2.2 pgoyette const u_int aff1 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff1); 348 1.2.2.2 pgoyette const u_int aff2 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff2); 349 1.2.2.2 pgoyette const u_int aff3 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff3); 350 1.2.2.2 pgoyette 351 1.2.2.2 pgoyette return __SHIFTIN(__BIT(aff0), ICC_SGIR_EL1_TargetList) | 352 1.2.2.2 pgoyette __SHIFTIN(aff1, ICC_SGIR_EL1_Aff1) | 353 1.2.2.2 pgoyette __SHIFTIN(aff2, ICC_SGIR_EL1_Aff2) | 354 1.2.2.2 pgoyette __SHIFTIN(aff3, ICC_SGIR_EL1_Aff3); 355 1.2.2.2 pgoyette } 356 1.2.2.2 pgoyette 357 1.2.2.2 pgoyette static void 358 1.2.2.2 pgoyette gicv3_cpu_init(struct pic_softc *pic, struct cpu_info *ci) 359 1.2.2.2 pgoyette { 360 1.2.2.2 pgoyette struct gicv3_softc * const sc = PICTOSOFTC(pic); 361 1.2.2.2 pgoyette uint32_t icc_sre, icc_ctlr, gicr_waker; 362 1.2.2.2 pgoyette 363 1.2.2.2 pgoyette ci->ci_gic_redist = gicv3_find_redist(sc); 364 1.2.2.2 pgoyette ci->ci_gic_sgir = gicv3_sgir(sc); 365 1.2.2.2 pgoyette 366 1.2.2.2 pgoyette if (CPU_IS_PRIMARY(ci)) { 367 1.2.2.2 pgoyette /* Store route to primary CPU for non-MPSAFE SPIs */ 368 1.2.2.2 pgoyette const uint64_t cpu_identity = gicv3_cpu_identity(); 369 1.2.2.2 pgoyette const u_int aff0 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff0); 370 1.2.2.2 pgoyette const u_int aff1 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff1); 371 1.2.2.2 pgoyette const u_int aff2 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff2); 372 1.2.2.2 pgoyette const u_int aff3 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff3); 373 1.2.2.2 pgoyette sc->sc_default_irouter = 374 1.2.2.2 pgoyette __SHIFTIN(aff0, GICD_IROUTER_Aff0) | 375 1.2.2.2 pgoyette __SHIFTIN(aff1, GICD_IROUTER_Aff1) | 376 1.2.2.2 pgoyette __SHIFTIN(aff2, GICD_IROUTER_Aff2) | 377 1.2.2.2 pgoyette __SHIFTIN(aff3, GICD_IROUTER_Aff3); 378 1.2.2.2 pgoyette } 379 1.2.2.2 pgoyette 380 1.2.2.2 pgoyette /* Enable System register access and disable IRQ/FIQ bypass */ 381 1.2.2.2 pgoyette icc_sre = ICC_SRE_EL1_SRE | ICC_SRE_EL1_DFB | ICC_SRE_EL1_DIB; 382 1.2.2.2 pgoyette icc_sre_write(icc_sre); 383 1.2.2.2 pgoyette 384 1.2.2.2 pgoyette /* Mark the connected PE as being awake */ 385 1.2.2.2 pgoyette gicr_waker = gicr_read_4(sc, ci->ci_gic_redist, GICR_WAKER); 386 1.2.2.2 pgoyette gicr_waker &= ~GICR_WAKER_ProcessorSleep; 387 1.2.2.2 pgoyette gicr_write_4(sc, ci->ci_gic_redist, GICR_WAKER, gicr_waker); 388 1.2.2.2 pgoyette while (gicr_read_4(sc, ci->ci_gic_redist, GICR_WAKER) & GICR_WAKER_ChildrenAsleep) 389 1.2.2.2 pgoyette ; 390 1.2.2.2 pgoyette 391 1.2.2.2 pgoyette /* Set initial priority mask */ 392 1.2.2.2 pgoyette icc_pmr_write(IPL_TO_PRIORITY(IPL_HIGH)); 393 1.2.2.2 pgoyette 394 1.2.2.2 pgoyette /* Disable preemption */ 395 1.2.2.2 pgoyette const uint32_t icc_bpr = __SHIFTIN(0x7, ICC_BPR_EL1_BinaryPoint); 396 1.2.2.2 pgoyette icc_bpr1_write(icc_bpr); 397 1.2.2.2 pgoyette 398 1.2.2.2 pgoyette /* Enable group 1 interrupt signaling */ 399 1.2.2.2 pgoyette icc_igrpen1_write(ICC_IGRPEN_EL1_Enable); 400 1.2.2.2 pgoyette 401 1.2.2.2 pgoyette /* Set EOI mode */ 402 1.2.2.2 pgoyette icc_ctlr = icc_ctlr_read(); 403 1.2.2.2 pgoyette icc_ctlr &= ~ICC_CTLR_EL1_EOImode; 404 1.2.2.2 pgoyette icc_ctlr_write(icc_ctlr); 405 1.2.2.2 pgoyette 406 1.2.2.2 pgoyette /* Enable redistributor */ 407 1.2.2.2 pgoyette gicv3_redist_enable(sc, ci); 408 1.2.2.2 pgoyette 409 1.2.2.2 pgoyette /* Allow IRQ exceptions */ 410 1.2.2.2 pgoyette cpsie(I32_bit); 411 1.2.2.2 pgoyette } 412 1.2.2.2 pgoyette 413 1.2.2.2 pgoyette #ifdef MULTIPROCESSOR 414 1.2.2.2 pgoyette static void 415 1.2.2.2 pgoyette gicv3_ipi_send(struct pic_softc *pic, const kcpuset_t *kcp, u_long ipi) 416 1.2.2.2 pgoyette { 417 1.2.2.2 pgoyette CPU_INFO_ITERATOR cii; 418 1.2.2.2 pgoyette struct cpu_info *ci; 419 1.2.2.2 pgoyette uint64_t intid, aff, targets; 420 1.2.2.2 pgoyette 421 1.2.2.2 pgoyette intid = __SHIFTIN(ipi, ICC_SGIR_EL1_INTID); 422 1.2.2.2 pgoyette if (kcp == NULL) { 423 1.2.2.2 pgoyette /* Interrupts routed to all PEs, excluding "self" */ 424 1.2.2.2 pgoyette if (ncpu == 1) 425 1.2.2.2 pgoyette return; 426 1.2.2.2 pgoyette icc_sgi1r_write(intid | ICC_SGIR_EL1_IRM); 427 1.2.2.2 pgoyette } else { 428 1.2.2.2 pgoyette /* Interrupts routed to specific PEs */ 429 1.2.2.2 pgoyette aff = 0; 430 1.2.2.2 pgoyette targets = 0; 431 1.2.2.2 pgoyette for (CPU_INFO_FOREACH(cii, ci)) { 432 1.2.2.2 pgoyette if (!kcpuset_isset(kcp, cpu_index(ci))) 433 1.2.2.2 pgoyette continue; 434 1.2.2.2 pgoyette if ((ci->ci_gic_sgir & ICC_SGIR_EL1_Aff) != aff) { 435 1.2.2.2 pgoyette if (targets != 0) { 436 1.2.2.2 pgoyette icc_sgi1r_write(intid | aff | targets); 437 1.2.2.2 pgoyette targets = 0; 438 1.2.2.2 pgoyette } 439 1.2.2.2 pgoyette aff = (ci->ci_gic_sgir & ICC_SGIR_EL1_Aff); 440 1.2.2.2 pgoyette } 441 1.2.2.2 pgoyette targets |= (ci->ci_gic_sgir & ICC_SGIR_EL1_TargetList); 442 1.2.2.2 pgoyette } 443 1.2.2.2 pgoyette if (targets != 0) 444 1.2.2.2 pgoyette icc_sgi1r_write(intid | aff | targets); 445 1.2.2.2 pgoyette } 446 1.2.2.2 pgoyette } 447 1.2.2.2 pgoyette #endif 448 1.2.2.2 pgoyette 449 1.2.2.2 pgoyette static const struct pic_ops gicv3_picops = { 450 1.2.2.2 pgoyette .pic_unblock_irqs = gicv3_unblock_irqs, 451 1.2.2.2 pgoyette .pic_block_irqs = gicv3_block_irqs, 452 1.2.2.2 pgoyette .pic_establish_irq = gicv3_establish_irq, 453 1.2.2.2 pgoyette .pic_set_priority = gicv3_set_priority, 454 1.2.2.2 pgoyette #ifdef MULTIPROCESSOR 455 1.2.2.2 pgoyette .pic_cpu_init = gicv3_cpu_init, 456 1.2.2.2 pgoyette .pic_ipi_send = gicv3_ipi_send, 457 1.2.2.2 pgoyette #endif 458 1.2.2.2 pgoyette }; 459 1.2.2.2 pgoyette 460 1.2.2.2 pgoyette void 461 1.2.2.2 pgoyette gicv3_irq_handler(void *frame) 462 1.2.2.2 pgoyette { 463 1.2.2.2 pgoyette struct cpu_info * const ci = curcpu(); 464 1.2.2.2 pgoyette struct gicv3_softc * const sc = gicv3_softc; 465 1.2.2.2 pgoyette const int oldipl = ci->ci_cpl; 466 1.2.2.2 pgoyette 467 1.2.2.2 pgoyette ci->ci_data.cpu_nintr++; 468 1.2.2.2 pgoyette 469 1.2.2.2 pgoyette for (;;) { 470 1.2.2.2 pgoyette const uint32_t iar = icc_iar1_read(); 471 1.2.2.2 pgoyette const uint32_t irq = __SHIFTOUT(iar, ICC_IAR_INTID); 472 1.2.2.2 pgoyette if (irq == ICC_IAR_INTID_SPURIOUS) 473 1.2.2.2 pgoyette break; 474 1.2.2.2 pgoyette 475 1.2.2.2 pgoyette if (irq >= sc->sc_pic.pic_maxsources) 476 1.2.2.2 pgoyette continue; 477 1.2.2.2 pgoyette 478 1.2.2.2 pgoyette struct intrsource * const is = sc->sc_pic.pic_sources[irq]; 479 1.2.2.2 pgoyette KASSERT(is != NULL); 480 1.2.2.2 pgoyette 481 1.2.2.2 pgoyette const int ipl = is->is_ipl; 482 1.2.2.2 pgoyette if (ci->ci_cpl < ipl) 483 1.2.2.2 pgoyette pic_set_priority(ci, ipl); 484 1.2.2.2 pgoyette 485 1.2.2.2 pgoyette cpsie(I32_bit); 486 1.2.2.2 pgoyette pic_dispatch(is, frame); 487 1.2.2.2 pgoyette cpsid(I32_bit); 488 1.2.2.2 pgoyette 489 1.2.2.2 pgoyette icc_eoi1r_write(iar); 490 1.2.2.2 pgoyette } 491 1.2.2.2 pgoyette 492 1.2.2.2 pgoyette if (ci->ci_cpl != oldipl) 493 1.2.2.2 pgoyette pic_set_priority(ci, oldipl); 494 1.2.2.2 pgoyette } 495 1.2.2.2 pgoyette 496 1.2.2.2 pgoyette int 497 1.2.2.2 pgoyette gicv3_init(struct gicv3_softc *sc) 498 1.2.2.2 pgoyette { 499 1.2.2.2 pgoyette const uint32_t gicd_typer = gicd_read_4(sc, GICD_TYPER); 500 1.2.2.2 pgoyette 501 1.2.2.2 pgoyette KASSERT(CPU_IS_PRIMARY(curcpu())); 502 1.2.2.2 pgoyette 503 1.2.2.2 pgoyette sc->sc_pic.pic_ops = &gicv3_picops; 504 1.2.2.2 pgoyette sc->sc_pic.pic_maxsources = GICD_TYPER_LINES(gicd_typer); 505 1.2.2.2 pgoyette snprintf(sc->sc_pic.pic_name, sizeof(sc->sc_pic.pic_name), "gicv3"); 506 1.2.2.2 pgoyette #ifdef MULTIPROCESSOR 507 1.2.2.2 pgoyette sc->sc_pic.pic_cpus = kcpuset_running; 508 1.2.2.2 pgoyette #endif 509 1.2.2.2 pgoyette pic_add(&sc->sc_pic, 0); 510 1.2.2.2 pgoyette 511 1.2.2.2 pgoyette KASSERT(gicv3_softc == NULL); 512 1.2.2.2 pgoyette gicv3_softc = sc; 513 1.2.2.2 pgoyette 514 1.2.2.2 pgoyette for (int i = 0; i < sc->sc_bsh_r_count; i++) { 515 1.2.2.2 pgoyette const uint64_t gicr_typer = gicr_read_8(sc, i, GICR_TYPER); 516 1.2.2.2 pgoyette const u_int aff0 = __SHIFTOUT(gicr_typer, GICR_TYPER_Affinity_Value_Aff0); 517 1.2.2.2 pgoyette const u_int aff1 = __SHIFTOUT(gicr_typer, GICR_TYPER_Affinity_Value_Aff1); 518 1.2.2.2 pgoyette const u_int aff2 = __SHIFTOUT(gicr_typer, GICR_TYPER_Affinity_Value_Aff2); 519 1.2.2.2 pgoyette const u_int aff3 = __SHIFTOUT(gicr_typer, GICR_TYPER_Affinity_Value_Aff3); 520 1.2.2.2 pgoyette 521 1.2.2.2 pgoyette aprint_debug_dev(sc->sc_dev, "redist %d: cpu %d.%d.%d.%d\n", 522 1.2.2.2 pgoyette i, aff3, aff2, aff1, aff0); 523 1.2.2.2 pgoyette } 524 1.2.2.2 pgoyette 525 1.2.2.2 pgoyette gicv3_dist_enable(sc); 526 1.2.2.2 pgoyette 527 1.2.2.2 pgoyette gicv3_cpu_init(&sc->sc_pic, curcpu()); 528 1.2.2.2 pgoyette 529 1.2.2.2 pgoyette #ifdef __HAVE_PIC_FAST_SOFTINTS 530 1.2.2.2 pgoyette intr_establish(SOFTINT_BIO, IPL_SOFTBIO, IST_MPSAFE | IST_EDGE, pic_handle_softint, (void *)SOFTINT_BIO); 531 1.2.2.2 pgoyette intr_establish(SOFTINT_CLOCK, IPL_SOFTCLOCK, IST_MPSAFE | IST_EDGE, pic_handle_softint, (void *)SOFTINT_CLOCK); 532 1.2.2.2 pgoyette intr_establish(SOFTINT_NET, IPL_SOFTNET, IST_MPSAFE | IST_EDGE, pic_handle_softint, (void *)SOFTINT_NET); 533 1.2.2.2 pgoyette intr_establish(SOFTINT_SERIAL, IPL_SOFTSERIAL, IST_MPSAFE | IST_EDGE, pic_handle_softint, (void *)SOFTINT_SERIAL); 534 1.2.2.2 pgoyette #endif 535 1.2.2.2 pgoyette 536 1.2.2.2 pgoyette #ifdef MULTIPROCESSOR 537 1.2.2.2 pgoyette intr_establish(IPI_AST, IPL_VM, IST_MPSAFE | IST_EDGE, pic_ipi_ast, (void *)-1); 538 1.2.2.2 pgoyette intr_establish(IPI_XCALL, IPL_HIGH, IST_MPSAFE | IST_EDGE, pic_ipi_xcall, (void *)-1); 539 1.2.2.2 pgoyette intr_establish(IPI_GENERIC, IPL_HIGH, IST_MPSAFE | IST_EDGE, pic_ipi_generic, (void *)-1); 540 1.2.2.2 pgoyette intr_establish(IPI_NOP, IPL_VM, IST_MPSAFE | IST_EDGE, pic_ipi_nop, (void *)-1); 541 1.2.2.2 pgoyette intr_establish(IPI_SHOOTDOWN, IPL_SCHED, IST_MPSAFE | IST_EDGE, pic_ipi_shootdown, (void *)-1); 542 1.2.2.2 pgoyette #ifdef DDB 543 1.2.2.2 pgoyette intr_establish(IPI_DDB, IPL_HIGH, IST_MPSAFE | IST_EDGE, pic_ipi_ddb, NULL); 544 1.2.2.2 pgoyette #endif 545 1.2.2.2 pgoyette #ifdef __HAVE_PREEMPTION 546 1.2.2.2 pgoyette intr_establish(IPI_KPREEMPT, IPL_VM, IST_MPSAFE | IST_EDGE, pic_ipi_kpreempt, (void *)-1); 547 1.2.2.2 pgoyette #endif 548 1.2.2.2 pgoyette #endif 549 1.2.2.2 pgoyette 550 1.2.2.2 pgoyette return 0; 551 1.2.2.2 pgoyette } 552
Indexes created Thu Oct 02 14:10:14 GMT 2025