gicv3.h revision 1.2
1 1.2 jmcneill /* $NetBSD: gicv3.h,v 1.2 2018/11/09 23:36:24 jmcneill Exp $ */ 2 1.1 jmcneill 3 1.1 jmcneill /*- 4 1.1 jmcneill * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 1.1 jmcneill * All rights reserved. 6 1.1 jmcneill * 7 1.1 jmcneill * Redistribution and use in source and binary forms, with or without 8 1.1 jmcneill * modification, are permitted provided that the following conditions 9 1.1 jmcneill * are met: 10 1.1 jmcneill * 1. Redistributions of source code must retain the above copyright 11 1.1 jmcneill * notice, this list of conditions and the following disclaimer. 12 1.1 jmcneill * 2. Redistributions in binary form must reproduce the above copyright 13 1.1 jmcneill * notice, this list of conditions and the following disclaimer in the 14 1.1 jmcneill * documentation and/or other materials provided with the distribution. 15 1.1 jmcneill * 16 1.1 jmcneill * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.1 jmcneill * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.1 jmcneill * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.1 jmcneill * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.1 jmcneill * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.1 jmcneill * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.1 jmcneill * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.1 jmcneill * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.1 jmcneill * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.1 jmcneill * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.1 jmcneill * SUCH DAMAGE. 27 1.1 jmcneill */ 28 1.1 jmcneill 29 1.1 jmcneill #ifndef _ARM_CORTEX_GICV3_H 30 1.1 jmcneill #define _ARM_CORTEX_GICV3_H 31 1.1 jmcneill 32 1.1 jmcneill #include <sys/intr.h> 33 1.1 jmcneill 34 1.2 jmcneill struct gicv3_dma { 35 1.2 jmcneill bus_dma_segment_t segs[1]; 36 1.2 jmcneill bus_dmamap_t map; 37 1.2 jmcneill uint8_t *base; 38 1.2 jmcneill bus_size_t len; 39 1.2 jmcneill }; 40 1.2 jmcneill 41 1.2 jmcneill struct gicv3_cpu_init { 42 1.2 jmcneill void (*func)(void *, struct cpu_info *ci); 43 1.2 jmcneill void *arg; 44 1.2 jmcneill 45 1.2 jmcneill LIST_ENTRY(gicv3_cpu_init) list; 46 1.2 jmcneill }; 47 1.2 jmcneill 48 1.1 jmcneill struct gicv3_softc { 49 1.2 jmcneill struct pic_softc sc_pic; /* SGI/PPI/SGIs */ 50 1.2 jmcneill struct pic_softc sc_lpi; /* LPIs */ 51 1.1 jmcneill device_t sc_dev; 52 1.1 jmcneill 53 1.1 jmcneill bus_space_tag_t sc_bst; 54 1.2 jmcneill bus_dma_tag_t sc_dmat; 55 1.1 jmcneill 56 1.1 jmcneill bus_space_handle_t sc_bsh_d; /* GICD */ 57 1.1 jmcneill bus_space_handle_t *sc_bsh_r; /* GICR */ 58 1.1 jmcneill u_int sc_bsh_r_count; 59 1.1 jmcneill 60 1.1 jmcneill uint32_t sc_enabled_sgippi; 61 1.1 jmcneill uint64_t sc_default_irouter; 62 1.2 jmcneill 63 1.2 jmcneill /* LPI configuration table */ 64 1.2 jmcneill struct gicv3_dma sc_lpiconf; 65 1.2 jmcneill 66 1.2 jmcneill /* LPI pending tables */ 67 1.2 jmcneill struct gicv3_dma sc_lpipend[MAXCPUS]; 68 1.2 jmcneill 69 1.2 jmcneill /* Unique identifier for PEs */ 70 1.2 jmcneill u_int sc_processor_id[MAXCPUS]; 71 1.2 jmcneill 72 1.2 jmcneill /* CPU init callbacks */ 73 1.2 jmcneill LIST_HEAD(, gicv3_cpu_init) sc_cpu_init; 74 1.1 jmcneill }; 75 1.1 jmcneill 76 1.1 jmcneill int gicv3_init(struct gicv3_softc *); 77 1.2 jmcneill void gicv3_dma_alloc(struct gicv3_softc *, struct gicv3_dma *, bus_size_t, bus_size_t); 78 1.1 jmcneill void gicv3_irq_handler(void *); 79 1.1 jmcneill 80 1.1 jmcneill #endif /* _ARM_CORTEX_GICV3_H */ 81
Indexes created Tue Sep 23 14:10:03 GMT 2025