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gicv3.h revision 1.2 
      1 /* $NetBSD: gicv3.h,v 1.2 2018/11/09 23:36:24 jmcneill Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #ifndef _ARM_CORTEX_GICV3_H
     30 #define _ARM_CORTEX_GICV3_H
     31 
     32 #include <sys/intr.h>
     33 
     34 struct gicv3_dma {
     35 	bus_dma_segment_t	segs[1];
     36 	bus_dmamap_t		map;
     37 	uint8_t			*base;
     38 	bus_size_t		len;
     39 };
     40 
     41 struct gicv3_cpu_init {
     42 	void			(*func)(void *, struct cpu_info *ci);
     43 	void			*arg;
     44 
     45 	LIST_ENTRY(gicv3_cpu_init) list;
     46 };
     47 
     48 struct gicv3_softc {
     49 	struct pic_softc	sc_pic;		/* SGI/PPI/SGIs */
     50 	struct pic_softc	sc_lpi;		/* LPIs */
     51 	device_t		sc_dev;
     52 
     53 	bus_space_tag_t		sc_bst;
     54 	bus_dma_tag_t		sc_dmat;
     55 
     56 	bus_space_handle_t	sc_bsh_d;	/* GICD */
     57 	bus_space_handle_t	*sc_bsh_r;	/* GICR */
     58 	u_int			sc_bsh_r_count;
     59 
     60 	uint32_t		sc_enabled_sgippi;
     61 	uint64_t		sc_default_irouter;
     62 
     63 	/* LPI configuration table */
     64 	struct gicv3_dma	sc_lpiconf;
     65 
     66 	/* LPI pending tables */
     67 	struct gicv3_dma	sc_lpipend[MAXCPUS];
     68 
     69 	/* Unique identifier for PEs */
     70 	u_int			sc_processor_id[MAXCPUS];
     71 
     72 	/* CPU init callbacks */
     73 	LIST_HEAD(, gicv3_cpu_init) sc_cpu_init;
     74 };
     75 
     76 int	gicv3_init(struct gicv3_softc *);
     77 void	gicv3_dma_alloc(struct gicv3_softc *, struct gicv3_dma *, bus_size_t, bus_size_t);
     78 void	gicv3_irq_handler(void *);
     79 
     80 #endif /* _ARM_CORTEX_GICV3_H */
     81