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gicv3_its.h revision 1.2 
      1 /* $NetBSD: gicv3_its.h,v 1.2 2018/11/10 11:46:31 jmcneill Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2018 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Jared McNeill <jmcneill (at) invisible.ca>.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #ifndef _ARM_CORTEX_GICV3_ITS_H
     33 #define _ARM_CORTEX_GICV3_ITS_H
     34 
     35 #include <arm/pci/pci_msi_machdep.h>
     36 #include <arm/cortex/gic_reg.h>
     37 #include <arm/cortex/gicv3.h>
     38 
     39 struct gicv3_its_device {
     40 	uint32_t		dev_id;
     41 	struct gicv3_dma	dev_itt;
     42 
     43 	LIST_ENTRY(gicv3_its_device) dev_list;
     44 };
     45 
     46 struct gicv3_its {
     47 	bus_space_tag_t		its_bst;
     48 	bus_space_handle_t	its_bsh;
     49 	bus_dma_tag_t		its_dmat;
     50 	uint32_t		its_id;
     51 	uint64_t		its_base;
     52 	uint64_t		its_rdbase[MAXCPUS];
     53 
     54 	struct gicv3_softc	*its_gic;
     55 	struct gicv3_lpi_callback its_cb;
     56 
     57 	struct pic_softc	*its_pic;
     58 	const struct pci_attach_args **its_pa;
     59 	struct cpu_info		**its_targets;
     60 
     61 	LIST_HEAD(, gicv3_its_device) its_devices;
     62 
     63 	struct gicv3_dma	its_cmd;		/* Command queue */
     64 	struct gicv3_dma	its_tab[8];		/* ITS tables */
     65 
     66 	struct arm_pci_msi	its_msi;
     67 };
     68 
     69 int	gicv3_its_init(struct gicv3_softc *, bus_space_handle_t, uint64_t, uint32_t);
     70 
     71 #endif /* !_ARM_CORTEX_GICV3_ITS_H */
     72