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scu_reg.h revision 1.1.26.1 
      1 /* $NetBSD: scu_reg.h,v 1.1.26.1 2016/11/04 14:48:58 pgoyette Exp $ */
      2 /*-
      3  * Copyright (c) 2012 The NetBSD Foundation, Inc.
      4  * All rights reserved.
      5  *
      6  * This code is derived from software contributed to The NetBSD Foundation
      7  * by Matt Thomas of 3am Software Foundry.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  * 1. Redistributions of source code must retain the above copyright
     13  *    notice, this list of conditions and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  *
     18  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     19  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     20  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     21  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     28  * POSSIBILITY OF SUCH DAMAGE.
     29  */
     30 
     31 #ifndef _ARM_CORTEX_SCUREG_H_
     32 #define _ARM_CORTEX_SCUREG_H_
     33 
     34 /*
     35  * ARM Snoop Control Unit Definitions
     36  * Used by Cortex-A5 and Cortex-A9
     37  */
     38 
     39 #define	SCU_SIZE		0x100
     40 
     41 #define	SCU_CTL			0x00	// SCU Control Register
     42 #define	SCU_CFG			0x04	// SCU Configuration Register
     43 #define	SCU_CPU_PWR_STS		0x08	// SCU CPU Power Status
     44 #define	SCU_INV_ALL_REG		0x0c	// SCU Invalidate All Registers in Secure State
     45 #define	SCU_FILTER_START	0x40	// Filtering Start Address
     46 #define	SCU_FILTER_END		0x44	// Filtering End Address
     47 #define	SCU_ACCESS_CONTROL	0x50	// SCU Access Control
     48 #define	SCU_NS_ACCESS_CONTROL	0x54	// SCU Non-Secure Access Control
     49 
     50 #define	SCU_CTL_IC_STANDBY_ENA			__BIT(6)
     51 #define	SCU_CTL_SCU_STANDBY_ENA			__BIT(5)
     52 #define	SCU_CTL_FORCE_PORT0_ENA			__BIT(4)
     53 #define	SCU_CTL_SPECULATIVE_LINEFILL_ENA	__BIT(3)
     54 #define	SCU_CTL_SCU_RAM_PARITY_ENA		__BIT(2)
     55 #define	SCU_CTL_ADDR_FILTER_ENA			__BIT(1)
     56 #define	SCU_CTL_SCU_ENA				__BIT(0)
     57 
     58 #define	SCU_CFG_TAG_RAM_SIZE_CPUn(n)	__BITS(9+2*(n),8+2*(n))
     59 #define	SCU_CFG_TAG_RAM_SIZE_CPU3	__BITS(15,14)
     60 #define	SCU_CFG_TAG_RAM_SIZE_CPU2	__BITS(13,12)
     61 #define	SCU_CFG_TAG_RAM_SIZE_CPU1	__BITS(11,10)
     62 #define	SCU_CFG_TAG_RAM_SIZE_CPU0	__BITS(9,8)
     63 #define	SCU_CFG_TAG_RAM_SIZE_16KB	0
     64 #define	SCU_CFG_TAG_RAM_SIZE_32KB	1
     65 #define	SCU_CFG_TAG_RAM_SIZE_64KB	2
     66 #define	SCU_CFG_CPUn_SMP(n)		__BIT(4+(n))
     67 #define	SCU_CFG_CPU3_SMP		__BIT(7)
     68 #define	SCU_CFG_CPU2_SMP		__BIT(6)
     69 #define	SCU_CFG_CPU1_SMP		__BIT(5)
     70 #define	SCU_CFG_CPU0_SMP		__BIT(4)
     71 #define	SCU_CFG_CPUMAX			__BITS(0,1)	// # of CPU - 1
     72 
     73 #endif /* _ARM_CORTEX_SCUREG_H_ */
     74