meson8b.dtsi revision 1.3 
1/* $NetBSD: meson8b.dtsi,v 1.3 2019/01/20 00:44:01 jmcneill Exp $ */
2
3/*-
4 * Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#define	CLKID_PERIPH	126
30
31/ {
32	timer@c4300200 {
33		compatible = "arm,cortex-a5-global-timer";
34		reg = <0xc4300200 0x20>;
35		interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
36		clocks = <&clkc CLKID_PERIPH>;
37	};
38
39	genfb: fb@c8006000 {
40		compatible = "amlogic,meson8b-fb";
41		reg = <0xc8006000 0x400>,	/* DMC */
42		      <0xd0040000 0x10000>,	/* HDMI */
43		      <0xd0100000 0x100000>;	/* VPU */
44		status = "disabled";
45	};
46};
47
48&pinctrl_cbus {
49	sdxc_c_pins: sdxc-c {
50		mux {
51			groups = "sdxc_d0_c", "sdxc_d13_c", "sdxc_d47_c", "sdxc_clk_c", "sdxc_cmd_c";
52			function = "sdxc_c";
53		};
54	};
55};
56
57&cbus {
58	sdhc: mmc@8e00 {
59		compatible = "amlogic,meson8b-sdhc";
60		reg = <0x8e00 0x30>;
61		interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
62		clocks = <&clkc CLKID_SDHC>, <&clkc CLKID_FCLK_DIV3>;
63		clock-names = "core", "clkin";
64		#address-cells = <1>;
65		#size-cells = <0>;
66		status = "disabled";
67	};
68};
69