meson8b.dtsi revision 1.4 
1/* $NetBSD: meson8b.dtsi,v 1.4 2019/01/20 17:29:04 jmcneill Exp $ */
2
3/*-
4 * Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#define	CLKID_PERIPH	126
30
31/ {
32	timer@c4300200 {
33		compatible = "arm,cortex-a5-global-timer";
34		reg = <0xc4300200 0x20>;
35		interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
36		clocks = <&clkc CLKID_PERIPH>;
37	};
38
39	genfb: fb@c8006000 {
40		compatible = "amlogic,meson8b-fb";
41		reg = <0xc8006000 0x400>,	/* DMC */
42		      <0xd0040000 0x10000>,	/* HDMI */
43		      <0xd0100000 0x100000>;	/* VPU */
44		status = "disabled";
45	};
46
47	cpu_opp_table: opp-table {
48		compatible = "operating-points-v2";
49		opp-shared;
50
51		opp-96000000 {
52			opp-hz = /bits/ 64 <96000000>;
53			opp-microvolt = <860000>;
54		};
55		opp-192000000 {
56			opp-hz = /bits/ 64 <192000000>;
57			opp-microvolt = <860000>;
58		};
59		opp-312000000 {
60			opp-hz = /bits/ 64 <312000000>;
61			opp-microvolt = <860000>;
62		};
63		opp-408000000 {
64			opp-hz = /bits/ 64 <408000000>;
65			opp-microvolt = <860000>;
66		};
67		opp-504000000 {
68			opp-hz = /bits/ 64 <504000000>;
69			opp-microvolt = <860000>;
70		};
71		opp-600000000 {
72			opp-hz = /bits/ 64 <600000000>;
73			opp-microvolt = <860000>;
74		};
75		opp-720000000 {
76			opp-hz = /bits/ 64 <720000000>;
77			opp-microvolt = <860000>;
78		};
79		opp-816000000 {
80			opp-hz = /bits/ 64 <816000000>;
81			opp-microvolt = <900000>;
82		};
83		opp-1008000000 {
84			opp-hz = /bits/ 64 <1008000000>;
85			opp-microvolt = <1140000>;
86		};
87		opp-1200000000 {
88			opp-hz = /bits/ 64 <1200000000>;
89			opp-microvolt = <1140000>;
90		};
91		opp-1320000000 {
92			opp-hz = /bits/ 64 <1320000000>;
93			opp-microvolt = <1140000>;
94		};
95		opp-1488000000 {
96			opp-hz = /bits/ 64 <1488000000>;
97			opp-microvolt = <1140000>;
98		};
99		opp-1536000000 {
100			opp-hz = /bits/ 64 <1536000000>;
101			opp-microvolt = <1140000>;
102		};
103	};
104};
105
106&cpu0 {
107	operating-points-v2 = <&cpu_opp_table>;
108	clocks = <&clkc CLKID_CPUCLK>;
109};
110
111&cpu1 {
112	operating-points-v2 = <&cpu_opp_table>;
113	clocks = <&clkc CLKID_CPUCLK>;
114};
115
116&cpu2 {
117	operating-points-v2 = <&cpu_opp_table>;
118	clocks = <&clkc CLKID_CPUCLK>;
119};
120
121&cpu3 {
122	operating-points-v2 = <&cpu_opp_table>;
123	clocks = <&clkc CLKID_CPUCLK>;
124};
125
126&pinctrl_cbus {
127	sdxc_c_pins: sdxc-c {
128		mux {
129			groups = "sdxc_d0_c", "sdxc_d13_c", "sdxc_d47_c", "sdxc_clk_c", "sdxc_cmd_c";
130			function = "sdxc_c";
131		};
132	};
133};
134
135&cbus {
136	sdhc: mmc@8e00 {
137		compatible = "amlogic,meson8b-sdhc";
138		reg = <0x8e00 0x30>;
139		interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
140		clocks = <&clkc CLKID_SDHC>, <&clkc CLKID_FCLK_DIV3>;
141		clock-names = "core", "clkin";
142		#address-cells = <1>;
143		#size-cells = <0>;
144		status = "disabled";
145	};
146};
147