meson8b.dtsi revision 1.6 
1/* $NetBSD: meson8b.dtsi,v 1.6 2019/08/13 09:56:08 skrll Exp $ */
2
3/*-
4 * Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#define	CLKID_PERIPH	126
30
31/ {
32	genfb: fb@c8006000 {
33		compatible = "amlogic,meson8b-fb";
34		reg = <0xc8006000 0x400>,	/* DMC */
35		      <0xd0040000 0x10000>,	/* HDMI */
36		      <0xd0100000 0x100000>;	/* VPU */
37		status = "disabled";
38	};
39
40	cpu_opp_table: opp-table {
41		compatible = "operating-points-v2";
42		opp-shared;
43
44		opp-96000000 {
45			opp-hz = /bits/ 64 <96000000>;
46			opp-microvolt = <860000>;
47		};
48		opp-192000000 {
49			opp-hz = /bits/ 64 <192000000>;
50			opp-microvolt = <860000>;
51		};
52		opp-312000000 {
53			opp-hz = /bits/ 64 <312000000>;
54			opp-microvolt = <860000>;
55		};
56		opp-408000000 {
57			opp-hz = /bits/ 64 <408000000>;
58			opp-microvolt = <860000>;
59		};
60		opp-504000000 {
61			opp-hz = /bits/ 64 <504000000>;
62			opp-microvolt = <860000>;
63		};
64		opp-600000000 {
65			opp-hz = /bits/ 64 <600000000>;
66			opp-microvolt = <860000>;
67		};
68		opp-720000000 {
69			opp-hz = /bits/ 64 <720000000>;
70			opp-microvolt = <860000>;
71		};
72		opp-816000000 {
73			opp-hz = /bits/ 64 <816000000>;
74			opp-microvolt = <900000>;
75		};
76		opp-1008000000 {
77			opp-hz = /bits/ 64 <1008000000>;
78			opp-microvolt = <1140000>;
79		};
80		opp-1200000000 {
81			opp-hz = /bits/ 64 <1200000000>;
82			opp-microvolt = <1140000>;
83		};
84		opp-1320000000 {
85			opp-hz = /bits/ 64 <1320000000>;
86			opp-microvolt = <1140000>;
87		};
88		opp-1488000000 {
89			opp-hz = /bits/ 64 <1488000000>;
90			opp-microvolt = <1140000>;
91		};
92		opp-1536000000 {
93			opp-hz = /bits/ 64 <1536000000>;
94			opp-microvolt = <1140000>;
95		};
96	};
97};
98
99&cpu0 {
100	operating-points-v2 = <&cpu_opp_table>;
101	clocks = <&clkc CLKID_CPUCLK>;
102};
103
104&cpu1 {
105	operating-points-v2 = <&cpu_opp_table>;
106	clocks = <&clkc CLKID_CPUCLK>;
107};
108
109&cpu2 {
110	operating-points-v2 = <&cpu_opp_table>;
111	clocks = <&clkc CLKID_CPUCLK>;
112};
113
114&cpu3 {
115	operating-points-v2 = <&cpu_opp_table>;
116	clocks = <&clkc CLKID_CPUCLK>;
117};
118
119&pinctrl_cbus {
120	sdxc_c_pins: sdxc-c {
121		mux {
122			groups = "sdxc_d0_c", "sdxc_d13_c", "sdxc_d47_c", "sdxc_clk_c", "sdxc_cmd_c";
123			function = "sdxc_c";
124		};
125	};
126};
127
128&cbus {
129	sdhc: mmc@8e00 {
130		compatible = "amlogic,meson8b-sdhc";
131		reg = <0x8e00 0x30>;
132		interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
133		clocks = <&clkc CLKID_SDHC>, <&clkc CLKID_FCLK_DIV3>;
134		clock-names = "core", "clkin";
135		#address-cells = <1>;
136		#size-cells = <0>;
137		status = "disabled";
138	};
139};
140
141&aobus {
142	rtc: rtc@740 {
143		compatible = "amlogic,meson8b-rtc";
144		reg = <0x740 0x14>;
145		interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
146	};
147};
148