rk3399-rockpro64.dts revision 1.11 1 1.11 riastrad /* $NetBSD: rk3399-rockpro64.dts,v 1.11 2020/05/17 19:57:25 riastradh Exp $ */
2 1.5 jmcneill
3 1.5 jmcneill /*-
4 1.5 jmcneill * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca>
5 1.5 jmcneill * All rights reserved.
6 1.5 jmcneill *
7 1.5 jmcneill * Redistribution and use in source and binary forms, with or without
8 1.5 jmcneill * modification, are permitted provided that the following conditions
9 1.5 jmcneill * are met:
10 1.5 jmcneill * 1. Redistributions of source code must retain the above copyright
11 1.5 jmcneill * notice, this list of conditions and the following disclaimer.
12 1.5 jmcneill * 2. Redistributions in binary form must reproduce the above copyright
13 1.5 jmcneill * notice, this list of conditions and the following disclaimer in the
14 1.5 jmcneill * documentation and/or other materials provided with the distribution.
15 1.5 jmcneill *
16 1.5 jmcneill * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 1.5 jmcneill * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 1.5 jmcneill * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 1.5 jmcneill * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 1.5 jmcneill * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 1.5 jmcneill * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 1.5 jmcneill * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 1.5 jmcneill * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 1.5 jmcneill * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 1.5 jmcneill * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 1.5 jmcneill * SUCH DAMAGE.
27 1.1 jmcneill */
28 1.1 jmcneill
29 1.5 jmcneill #include "../../../external/gpl2/dts/dist/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts"
30 1.11 riastrad #include "rk3399-crypto.dtsi"
31 1.1 jmcneill
32 1.1 jmcneill / {
33 1.5 jmcneill pwm-fan {
34 1.1 jmcneill compatible = "pwm-fan";
35 1.1 jmcneill status = "okay";
36 1.5 jmcneill pwms = <&pwm1 0 40000 0>;
37 1.5 jmcneill cooling-levels = <0 150 195 240>;
38 1.1 jmcneill };
39 1.6 jmcneill
40 1.6 jmcneill vcc3v3_pcie: vcc3v3-pcie-regulator {
41 1.6 jmcneill compatible = "regulator-fixed";
42 1.6 jmcneill regulator-min-microvolt = <3300000>;
43 1.6 jmcneill regulator-max-microvolt = <3300000>;
44 1.6 jmcneill enable-active-high;
45 1.6 jmcneill gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
46 1.6 jmcneill pinctrl-names = "default";
47 1.6 jmcneill pinctrl-0 = <&pcie_pwr_en>;
48 1.6 jmcneill regulator-name = "vcc3v3_pcie";
49 1.6 jmcneill };
50 1.10 jakllsch
51 1.10 jakllsch backlight: lcd-backlight {
52 1.10 jakllsch compatible = "pwm-backlight";
53 1.10 jakllsch pwms = <&pwm0 0 25000 0>;
54 1.10 jakllsch brightness-levels = <
55 1.10 jakllsch 0 1 2 3 4 5 6 7
56 1.10 jakllsch 8 9 10 11 12 13 14 15
57 1.10 jakllsch 16 17 18 19 20 21 22 23
58 1.10 jakllsch 24 25 26 27 28 29 30 31
59 1.10 jakllsch 32 33 34 35 36 37 38 39
60 1.10 jakllsch 40 41 42 43 44 45 46 47
61 1.10 jakllsch 48 49 50 51 52 53 54 55
62 1.10 jakllsch 56 57 58 59 60 61 62 63
63 1.10 jakllsch 64 65 66 67 68 69 70 71
64 1.10 jakllsch 72 73 74 75 76 77 78 79
65 1.10 jakllsch 80 81 82 83 84 85 86 87
66 1.10 jakllsch 88 89 90 91 92 93 94 95
67 1.10 jakllsch 96 97 98 99 100 101 102 103
68 1.10 jakllsch 104 105 106 107 108 109 110 111
69 1.10 jakllsch 112 113 114 115 116 117 118 119
70 1.10 jakllsch 120 121 122 123 124 125 126 127
71 1.10 jakllsch 128 129 130 131 132 133 134 135
72 1.10 jakllsch 136 137 138 139 140 141 142 143
73 1.10 jakllsch 144 145 146 147 148 149 150 151
74 1.10 jakllsch 152 153 154 155 156 157 158 159
75 1.10 jakllsch 160 161 162 163 164 165 166 167
76 1.10 jakllsch 168 169 170 171 172 173 174 175
77 1.10 jakllsch 176 177 178 179 180 181 182 183
78 1.10 jakllsch 184 185 186 187 188 189 190 191
79 1.10 jakllsch 192 193 194 195 196 197 198 199
80 1.10 jakllsch 200 201 202 203 204 205 206 207
81 1.10 jakllsch 208 209 210 211 212 213 214 215
82 1.10 jakllsch 216 217 218 219 220 221 222 223
83 1.10 jakllsch 224 225 226 227 228 229 230 231
84 1.10 jakllsch 232 233 234 235 236 237 238 239
85 1.10 jakllsch 240 241 242 243 244 245 246 247
86 1.10 jakllsch 248 249 250 251 252 253 254 255>;
87 1.10 jakllsch default-brightness-level = <200>;
88 1.10 jakllsch status = "disabled";
89 1.10 jakllsch };
90 1.10 jakllsch
91 1.10 jakllsch edp_panel: edp-panel {
92 1.10 jakllsch compatible = "simple-panel";
93 1.10 jakllsch backlight = <&backlight>;
94 1.10 jakllsch power-supply = <&vcc3v3_s0>;
95 1.10 jakllsch pinctrl-names = "default";
96 1.10 jakllsch pinctrl-0 = <&edp_panel_en>;
97 1.10 jakllsch enable-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
98 1.10 jakllsch prepare-delay-ms = <20>;
99 1.10 jakllsch enable-delay-ms = <20>;
100 1.10 jakllsch status = "disabled";
101 1.10 jakllsch
102 1.10 jakllsch ports {
103 1.10 jakllsch #address-cells = <1>;
104 1.10 jakllsch #size-cells = <0>;
105 1.10 jakllsch
106 1.10 jakllsch port@0 {
107 1.10 jakllsch reg = <0>;
108 1.10 jakllsch #address-cells = <1>;
109 1.10 jakllsch #size-cells = <0>;
110 1.10 jakllsch
111 1.10 jakllsch panel_in_edp: endpoint@0 {
112 1.10 jakllsch reg = <0>;
113 1.10 jakllsch remote-endpoint = <&edp_out_panel>;
114 1.10 jakllsch };
115 1.10 jakllsch };
116 1.10 jakllsch };
117 1.10 jakllsch };
118 1.10 jakllsch
119 1.10 jakllsch edp@ff970000 {
120 1.10 jakllsch ports {
121 1.10 jakllsch edp_out: port@1 {
122 1.10 jakllsch reg = <1>;
123 1.10 jakllsch #address-cells = <1>;
124 1.10 jakllsch #size-cells = <0>;
125 1.10 jakllsch
126 1.10 jakllsch edp_out_panel: endpoint@0 {
127 1.10 jakllsch reg = <0>;
128 1.10 jakllsch remote-endpoint = <&panel_in_edp>;
129 1.10 jakllsch };
130 1.10 jakllsch };
131 1.10 jakllsch };
132 1.10 jakllsch };
133 1.10 jakllsch
134 1.10 jakllsch #if 0
135 1.10 jakllsch edp@ff970000 {
136 1.10 jakllsch status = "okay";
137 1.10 jakllsch };
138 1.10 jakllsch
139 1.10 jakllsch edp-panel {
140 1.10 jakllsch status = "okay";
141 1.10 jakllsch };
142 1.10 jakllsch
143 1.10 jakllsch pwm@ff420000 {
144 1.10 jakllsch status = "okay";
145 1.10 jakllsch };
146 1.10 jakllsch
147 1.10 jakllsch lcd-backlight {
148 1.10 jakllsch status = "okay";
149 1.10 jakllsch };
150 1.10 jakllsch #endif
151 1.6 jmcneill };
152 1.6 jmcneill
153 1.6 jmcneill &pinctrl {
154 1.10 jakllsch lcd_panel {
155 1.10 jakllsch edp_panel_en: edp-panel-en {
156 1.10 jakllsch rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
157 1.10 jakllsch };
158 1.10 jakllsch };
159 1.10 jakllsch
160 1.6 jmcneill pcie {
161 1.6 jmcneill pcie_pwr_en: pcie-pwr-en {
162 1.6 jmcneill rockchip,pins =
163 1.6 jmcneill <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
164 1.6 jmcneill };
165 1.6 jmcneill
166 1.6 jmcneill pcie_clkreqn: pci-clkreqn {
167 1.6 jmcneill rockchip,pins =
168 1.6 jmcneill <2 RK_PD2 RK_FUNC_2 &pcfg_pull_none>;
169 1.6 jmcneill };
170 1.6 jmcneill };
171 1.1 jmcneill };
172 1.1 jmcneill
173 1.1 jmcneill &pwm1 {
174 1.1 jmcneill status = "okay";
175 1.1 jmcneill };
176 1.6 jmcneill
177 1.6 jmcneill &pcie_phy {
178 1.6 jmcneill status = "okay";
179 1.6 jmcneill };
180 1.6 jmcneill
181 1.6 jmcneill &pcie0 {
182 1.6 jmcneill ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
183 1.6 jmcneill num-lanes = <4>;
184 1.7 jmcneill max-link-speed = <2>;
185 1.6 jmcneill pinctrl-names = "default";
186 1.6 jmcneill pinctrl-0 = <&pcie_clkreqn>;
187 1.6 jmcneill vpcie3v3-supply = <&vcc3v3_pcie>;
188 1.6 jmcneill status = "okay";
189 1.6 jmcneill };
190 1.8 tnn
191 1.8 tnn &spi1 {
192 1.8 tnn status = "okay";
193 1.8 tnn spiflash {
194 1.8 tnn compatible = "jedec,spi-nor";
195 1.8 tnn reg = <0>;
196 1.8 tnn status = "okay";
197 1.8 tnn };
198 1.8 tnn };
199 1.9 jmcneill
200 1.9 jmcneill &hdmi_sound {
201 1.9 jmcneill status = "okay";
202 1.9 jmcneill };
203