xref: /src/sys/arch/arm/dts/rk3399-rockpro64.dts

/* $NetBSD: rk3399-rockpro64.dts,v 1.6 2019/06/12 10:13:44 jmcneill Exp $ */

/*-
 * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#include "../../../external/gpl2/dts/dist/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts"

/ {
	pwm-fan {
		compatible = "pwm-fan";
		status = "okay";
		pwms = <&pwm1 0 40000 0>;
		cooling-levels = <0 150 195 240>;
	};

	vcc3v3_pcie: vcc3v3-pcie-regulator {
		compatible = "regulator-fixed";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		enable-active-high;
		gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&pcie_pwr_en>;
		regulator-name = "vcc3v3_pcie";
	};
};

&pinctrl {
	pcie {
		pcie_pwr_en: pcie-pwr-en {
			rockchip,pins =
				<1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		pcie_clkreqn: pci-clkreqn {
			rockchip,pins =
				<2 RK_PD2 RK_FUNC_2 &pcfg_pull_none>;
		};
	};
};

&pwm1 {
	status = "okay";
};

&pcie_phy {
	status = "okay";
};

&pcie0 {
	assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
	assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
	assigned-clock-rates = <100000000>;

	ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
	num-lanes = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pcie_clkreqn>;
	vpcie3v3-supply = <&vcc3v3_pcie>;
	status = "okay";
};