rk3399-rockpro64.dts revision 1.10 1 /* $NetBSD: rk3399-rockpro64.dts,v 1.10 2019/12/19 00:52:29 jakllsch Exp $ */
2
3 /*-
4 * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include "../../../external/gpl2/dts/dist/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts"
30
31 / {
32 pwm-fan {
33 compatible = "pwm-fan";
34 status = "okay";
35 pwms = <&pwm1 0 40000 0>;
36 cooling-levels = <0 150 195 240>;
37 };
38
39 vcc3v3_pcie: vcc3v3-pcie-regulator {
40 compatible = "regulator-fixed";
41 regulator-min-microvolt = <3300000>;
42 regulator-max-microvolt = <3300000>;
43 enable-active-high;
44 gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
45 pinctrl-names = "default";
46 pinctrl-0 = <&pcie_pwr_en>;
47 regulator-name = "vcc3v3_pcie";
48 };
49
50 backlight: lcd-backlight {
51 compatible = "pwm-backlight";
52 pwms = <&pwm0 0 25000 0>;
53 brightness-levels = <
54 0 1 2 3 4 5 6 7
55 8 9 10 11 12 13 14 15
56 16 17 18 19 20 21 22 23
57 24 25 26 27 28 29 30 31
58 32 33 34 35 36 37 38 39
59 40 41 42 43 44 45 46 47
60 48 49 50 51 52 53 54 55
61 56 57 58 59 60 61 62 63
62 64 65 66 67 68 69 70 71
63 72 73 74 75 76 77 78 79
64 80 81 82 83 84 85 86 87
65 88 89 90 91 92 93 94 95
66 96 97 98 99 100 101 102 103
67 104 105 106 107 108 109 110 111
68 112 113 114 115 116 117 118 119
69 120 121 122 123 124 125 126 127
70 128 129 130 131 132 133 134 135
71 136 137 138 139 140 141 142 143
72 144 145 146 147 148 149 150 151
73 152 153 154 155 156 157 158 159
74 160 161 162 163 164 165 166 167
75 168 169 170 171 172 173 174 175
76 176 177 178 179 180 181 182 183
77 184 185 186 187 188 189 190 191
78 192 193 194 195 196 197 198 199
79 200 201 202 203 204 205 206 207
80 208 209 210 211 212 213 214 215
81 216 217 218 219 220 221 222 223
82 224 225 226 227 228 229 230 231
83 232 233 234 235 236 237 238 239
84 240 241 242 243 244 245 246 247
85 248 249 250 251 252 253 254 255>;
86 default-brightness-level = <200>;
87 status = "disabled";
88 };
89
90 edp_panel: edp-panel {
91 compatible = "simple-panel";
92 backlight = <&backlight>;
93 power-supply = <&vcc3v3_s0>;
94 pinctrl-names = "default";
95 pinctrl-0 = <&edp_panel_en>;
96 enable-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
97 prepare-delay-ms = <20>;
98 enable-delay-ms = <20>;
99 status = "disabled";
100
101 ports {
102 #address-cells = <1>;
103 #size-cells = <0>;
104
105 port@0 {
106 reg = <0>;
107 #address-cells = <1>;
108 #size-cells = <0>;
109
110 panel_in_edp: endpoint@0 {
111 reg = <0>;
112 remote-endpoint = <&edp_out_panel>;
113 };
114 };
115 };
116 };
117
118 edp@ff970000 {
119 ports {
120 edp_out: port@1 {
121 reg = <1>;
122 #address-cells = <1>;
123 #size-cells = <0>;
124
125 edp_out_panel: endpoint@0 {
126 reg = <0>;
127 remote-endpoint = <&panel_in_edp>;
128 };
129 };
130 };
131 };
132
133 #if 0
134 edp@ff970000 {
135 status = "okay";
136 };
137
138 edp-panel {
139 status = "okay";
140 };
141
142 pwm@ff420000 {
143 status = "okay";
144 };
145
146 lcd-backlight {
147 status = "okay";
148 };
149 #endif
150
151 };
152
153 &pinctrl {
154 lcd_panel {
155 edp_panel_en: edp-panel-en {
156 rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
157 };
158 };
159
160 pcie {
161 pcie_pwr_en: pcie-pwr-en {
162 rockchip,pins =
163 <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
164 };
165
166 pcie_clkreqn: pci-clkreqn {
167 rockchip,pins =
168 <2 RK_PD2 RK_FUNC_2 &pcfg_pull_none>;
169 };
170 };
171 };
172
173 &pwm1 {
174 status = "okay";
175 };
176
177 &pcie_phy {
178 status = "okay";
179 };
180
181 &pcie0 {
182 ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
183 num-lanes = <4>;
184 max-link-speed = <2>;
185 pinctrl-names = "default";
186 pinctrl-0 = <&pcie_clkreqn>;
187 vpcie3v3-supply = <&vcc3v3_pcie>;
188 status = "okay";
189 };
190
191 &spi1 {
192 status = "okay";
193 spiflash {
194 compatible = "jedec,spi-nor";
195 reg = <0>;
196 status = "okay";
197 };
198 };
199
200 &hdmi_sound {
201 status = "okay";
202 };
203