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rk3399-rockpro64.dts revision 1.6 
      1 /* $NetBSD: rk3399-rockpro64.dts,v 1.6 2019/06/12 10:13:44 jmcneill Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #include "../../../external/gpl2/dts/dist/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts"
     30 
     31 / {
     32 	pwm-fan {
     33 		compatible = "pwm-fan";
     34 		status = "okay";
     35 		pwms = <&pwm1 0 40000 0>;
     36 		cooling-levels = <0 150 195 240>;
     37 	};
     38 
     39 	vcc3v3_pcie: vcc3v3-pcie-regulator {
     40 		compatible = "regulator-fixed";
     41 		regulator-min-microvolt = <3300000>;
     42 		regulator-max-microvolt = <3300000>;
     43 		enable-active-high;
     44 		gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
     45 		pinctrl-names = "default";
     46 		pinctrl-0 = <&pcie_pwr_en>;
     47 		regulator-name = "vcc3v3_pcie";
     48 	};
     49 };
     50 
     51 &pinctrl {
     52 	pcie {
     53 		pcie_pwr_en: pcie-pwr-en {
     54 			rockchip,pins =
     55 				<1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
     56 		};
     57 
     58 		pcie_clkreqn: pci-clkreqn {
     59 			rockchip,pins =
     60 				<2 RK_PD2 RK_FUNC_2 &pcfg_pull_none>;
     61 		};
     62 	};
     63 };
     64 
     65 &pwm1 {
     66 	status = "okay";
     67 };
     68 
     69 &pcie_phy {
     70 	status = "okay";
     71 };
     72 
     73 &pcie0 {
     74 	assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
     75 	assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
     76 	assigned-clock-rates = <100000000>;
     77 
     78 	ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
     79 	num-lanes = <4>;
     80 	pinctrl-names = "default";
     81 	pinctrl-0 = <&pcie_clkreqn>;
     82 	vpcie3v3-supply = <&vcc3v3_pcie>;
     83 	status = "okay";
     84 };
     85