sun50i-a64.dtsi revision 1.12 1 /* $NetBSD: sun50i-a64.dtsi,v 1.12 2019/11/08 11:12:09 jmcneill Exp $ */
2
3 /*-
4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 / {
30 chosen {
31 #address-cells = <1>;
32 #size-cells = <1>;
33 ranges;
34
35 framebuffer@0 {
36 compatible = "allwinner,simple-framebuffer",
37 "simple-framebuffer";
38 allwinner,pipeline = "mixer1-lcd1-hdmi";
39 status = "disabled";
40 };
41 };
42
43 soc {
44 rtp: rtp@1c25000 {
45 compatible = "allwinner,sun50i-a64-ts";
46 reg = <0x01c25000 0x400>;
47 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
48 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
49 clock-names = "ahb", "ths";
50 resets = <&ccu RST_BUS_THS>;
51 #thermal-sensor-cells = <0>;
52 };
53 };
54
55 /* PMU interrupt numbers are wrong in mainline dts */
56 pmu {
57 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
58 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
59 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
61 };
62 };
63
64 &cpu0 {
65 clocks = <&ccu 1>; /* 1=CLK_PLL_CPUX */
66 };
67