11.5Sbouyer/* $NetBSD: sun8i-h3-orangepi-plus2e.dts,v 1.5 2023/09/12 12:56:21 bouyer Exp $ */
21.1Sjmcneill
31.1Sjmcneill/*-
41.1Sjmcneill * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
51.1Sjmcneill * All rights reserved.
61.1Sjmcneill *
71.1Sjmcneill * Redistribution and use in source and binary forms, with or without
81.1Sjmcneill * modification, are permitted provided that the following conditions
91.1Sjmcneill * are met:
101.1Sjmcneill * 1. Redistributions of source code must retain the above copyright
111.1Sjmcneill *    notice, this list of conditions and the following disclaimer.
121.1Sjmcneill * 2. Redistributions in binary form must reproduce the above copyright
131.1Sjmcneill *    notice, this list of conditions and the following disclaimer in the
141.1Sjmcneill *    documentation and/or other materials provided with the distribution.
151.1Sjmcneill *
161.1Sjmcneill * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
171.1Sjmcneill * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
181.1Sjmcneill * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
191.1Sjmcneill * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
201.1Sjmcneill * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
211.1Sjmcneill * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
221.1Sjmcneill * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
231.1Sjmcneill * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
241.1Sjmcneill * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
251.1Sjmcneill * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
261.1Sjmcneill * SUCH DAMAGE.
271.1Sjmcneill */
281.1Sjmcneill
291.1Sjmcneill#include "../../../external/gpl2/dts/dist/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts"
301.1Sjmcneill
311.1Sjmcneill/ {
321.2Sjmcneill	cpus {
331.2Sjmcneill		cpu@0 {
341.2Sjmcneill			cpu-supply = <&vdd_cpu>;
351.2Sjmcneill		};
361.2Sjmcneill	};
371.1Sjmcneill};
381.1Sjmcneill
391.4Sjmcneill&cpu0_opp_table {
401.4Sjmcneill	opp@1200000000 {
411.4Sjmcneill		opp-hz = /bits/ 64 <1200000000>;
421.4Sjmcneill		opp-microvolt = <1320000 1320000 1320000>;
431.4Sjmcneill		clock-latency-ns = <244144>;
441.4Sjmcneill	};
451.4Sjmcneill
461.4Sjmcneill	opp@1296000000 {
471.4Sjmcneill		opp-hz = /bits/ 64 <1296000000>;
481.4Sjmcneill		opp-microvolt = <1340000 1340000 1340000>;
491.4Sjmcneill		clock-latency-ns = <244144>;
501.4Sjmcneill	};
511.4Sjmcneill};
521.4Sjmcneill
531.2Sjmcneill&r_i2c {
541.2Sjmcneill	status = "okay";
551.2Sjmcneill
561.2Sjmcneill	vdd_cpu: regulator@65 {
571.2Sjmcneill		compatible = "silergy,sy8106a";
581.2Sjmcneill		reg = <0x65>;
591.2Sjmcneill
601.2Sjmcneill		regulator-name = "vdd-cpu";
611.2Sjmcneill		regulator-min-microvolt = <1000000>;
621.2Sjmcneill		regulator-max-microvolt = <1400000>;
631.2Sjmcneill		regulator-ramp-delay = <200>;
641.2Sjmcneill		regulator-boot-on;
651.2Sjmcneill		regulator-always-on;
661.2Sjmcneill	};
671.2Sjmcneill};
68