sun8i-h3-orangepi-plus2e.dts revision 1.4 
1/* $NetBSD: sun8i-h3-orangepi-plus2e.dts,v 1.4 2019/05/21 22:31:39 jmcneill Exp $ */
2
3/*-
4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include "../../../external/gpl2/dts/dist/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts"
30#include "sun8i-h3.dtsi"
31
32/ {
33	cpus {
34		cpu@0 {
35			cpu-supply = <&vdd_cpu>;
36		};
37	};
38};
39
40&cpu0_opp_table {
41	opp@1200000000 {
42		opp-hz = /bits/ 64 <1200000000>;
43		opp-microvolt = <1320000 1320000 1320000>;
44		clock-latency-ns = <244144>;
45	};
46
47	opp@1296000000 {
48		opp-hz = /bits/ 64 <1296000000>;
49		opp-microvolt = <1340000 1340000 1340000>;
50		clock-latency-ns = <244144>;
51	};
52};
53
54&r_i2c {
55	status = "okay";
56
57	vdd_cpu: regulator@65 {
58		compatible = "silergy,sy8106a";
59		reg = <0x65>;
60
61		regulator-name = "vdd-cpu";
62		regulator-min-microvolt = <1000000>;
63		regulator-max-microvolt = <1400000>;
64		regulator-ramp-delay = <200>;
65		regulator-boot-on;
66		regulator-always-on;
67	};
68};
69