ep93xx_intr.c revision 1.14
1 /* $NetBSD: ep93xx_intr.c,v 1.14 2010/06/13 02:11:22 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jesse Off 9 * 10 * This code is derived from software contributed to The NetBSD Foundation 11 * by Ichiro FUKUHARA and Naoto Shimazaki. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: ep93xx_intr.c,v 1.14 2010/06/13 02:11:22 tsutsui Exp $"); 37 38 /* 39 * Interrupt support for the Cirrus Logic EP93XX 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/malloc.h> 45 #include <sys/termios.h> 46 47 #include <uvm/uvm_extern.h> 48 49 #include <machine/bus.h> 50 #include <machine/intr.h> 51 52 #include <arm/cpufunc.h> 53 54 #include <arm/ep93xx/ep93xxreg.h> 55 #include <arm/ep93xx/ep93xxvar.h> 56 57 /* Interrupt handler queues. */ 58 struct intrq intrq[NIRQ]; 59 60 /* Interrupts to mask at each level. */ 61 static u_int32_t vic1_imask[NIPL]; 62 static u_int32_t vic2_imask[NIPL]; 63 64 /* Current interrupt priority level. */ 65 volatile int hardware_spl_level; 66 67 /* Software copy of the IRQs we have enabled. */ 68 volatile u_int32_t vic1_intr_enabled; 69 volatile u_int32_t vic2_intr_enabled; 70 71 /* Interrupts pending. */ 72 static volatile int ipending; 73 74 void ep93xx_intr_dispatch(struct irqframe *frame); 75 76 #define VIC1REG(reg) *((volatile u_int32_t*) (EP93XX_AHB_VBASE + \ 77 EP93XX_AHB_VIC1 + (reg))) 78 #define VIC2REG(reg) *((volatile u_int32_t*) (EP93XX_AHB_VBASE + \ 79 EP93XX_AHB_VIC2 + (reg))) 80 81 static void 82 ep93xx_set_intrmask(u_int32_t vic1_irqs, u_int32_t vic2_irqs) 83 { 84 VIC1REG(EP93XX_VIC_IntEnClear) = vic1_irqs; 85 VIC1REG(EP93XX_VIC_IntEnable) = vic1_intr_enabled & ~vic1_irqs; 86 VIC2REG(EP93XX_VIC_IntEnClear) = vic2_irqs; 87 VIC2REG(EP93XX_VIC_IntEnable) = vic2_intr_enabled & ~vic2_irqs; 88 } 89 90 static void 91 ep93xx_enable_irq(int irq) 92 { 93 if (irq < VIC_NIRQ) { 94 vic1_intr_enabled |= (1U << irq); 95 VIC1REG(EP93XX_VIC_IntEnable) = (1U << irq); 96 } else { 97 vic2_intr_enabled |= (1U << (irq - VIC_NIRQ)); 98 VIC2REG(EP93XX_VIC_IntEnable) = (1U << (irq - VIC_NIRQ)); 99 } 100 } 101 102 static inline void 103 ep93xx_disable_irq(int irq) 104 { 105 if (irq < VIC_NIRQ) { 106 vic1_intr_enabled &= ~(1U << irq); 107 VIC1REG(EP93XX_VIC_IntEnClear) = (1U << irq); 108 } else { 109 vic2_intr_enabled &= ~(1U << (irq - VIC_NIRQ)); 110 VIC2REG(EP93XX_VIC_IntEnClear) = (1U << (irq - VIC_NIRQ)); 111 } 112 } 113 114 /* 115 * NOTE: This routine must be called with interrupts disabled in the CPSR. 116 */ 117 static void 118 ep93xx_intr_calculate_masks(void) 119 { 120 struct intrq *iq; 121 struct intrhand *ih; 122 int irq, ipl; 123 124 /* First, figure out which IPLs each IRQ has. */ 125 for (irq = 0; irq < NIRQ; irq++) { 126 int levels = 0; 127 iq = &intrq[irq]; 128 ep93xx_disable_irq(irq); 129 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 130 ih = TAILQ_NEXT(ih, ih_list)) 131 levels |= (1U << ih->ih_ipl); 132 iq->iq_levels = levels; 133 } 134 135 /* Next, figure out which IRQs are used by each IPL. */ 136 for (ipl = 0; ipl < NIPL; ipl++) { 137 int vic1_irqs = 0; 138 int vic2_irqs = 0; 139 for (irq = 0; irq < VIC_NIRQ; irq++) { 140 if (intrq[irq].iq_levels & (1U << ipl)) 141 vic1_irqs |= (1U << irq); 142 } 143 vic1_imask[ipl] = vic1_irqs; 144 for (irq = 0; irq < VIC_NIRQ; irq++) { 145 if (intrq[irq + VIC_NIRQ].iq_levels & (1U << ipl)) 146 vic2_irqs |= (1U << irq); 147 } 148 vic2_imask[ipl] = vic2_irqs; 149 } 150 151 KASSERT(vic1_imask[IPL_NONE] == 0); 152 KASSERT(vic2_imask[IPL_NONE] == 0); 153 KASSERT(vic1_imask[IPL_SOFTCLOCK] == 0); 154 KASSERT(vic2_imask[IPL_SOFTCLOCK] == 0); 155 KASSERT(vic1_imask[IPL_SOFTBIO] == 0); 156 KASSERT(vic2_imask[IPL_SOFTBIO] == 0); 157 KASSERT(vic1_imask[IPL_SOFTNET] == 0); 158 KASSERT(vic2_imask[IPL_SOFTNET] == 0); 159 KASSERT(vic1_imask[IPL_SOFTSERIAL] == 0); 160 KASSERT(vic2_imask[IPL_SOFTSERIAL] == 0); 161 162 /* 163 * splsched() must block anything that uses the scheduler. 164 */ 165 vic1_imask[IPL_SCHED] |= vic1_imask[IPL_VM]; 166 vic2_imask[IPL_SCHED] |= vic2_imask[IPL_VM]; 167 168 /* 169 * splhigh() must block "everything". 170 */ 171 vic1_imask[IPL_HIGH] |= vic1_imask[IPL_SCHED]; 172 vic2_imask[IPL_HIGH] |= vic2_imask[IPL_SCHED]; 173 174 /* 175 * Now compute which IRQs must be blocked when servicing any 176 * given IRQ. 177 */ 178 for (irq = 0; irq < NIRQ; irq++) { 179 int vic1_irqs; 180 int vic2_irqs; 181 182 if (irq < VIC_NIRQ) { 183 vic1_irqs = (1U << irq); 184 vic2_irqs = 0; 185 } else { 186 vic1_irqs = 0; 187 vic2_irqs = (1U << (irq - VIC_NIRQ)); 188 } 189 iq = &intrq[irq]; 190 if (TAILQ_FIRST(&iq->iq_list) != NULL) 191 ep93xx_enable_irq(irq); 192 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 193 ih = TAILQ_NEXT(ih, ih_list)) { 194 vic1_irqs |= vic1_imask[ih->ih_ipl]; 195 vic2_irqs |= vic2_imask[ih->ih_ipl]; 196 } 197 iq->iq_vic1_mask = vic1_irqs; 198 iq->iq_vic2_mask = vic2_irqs; 199 } 200 } 201 202 inline void 203 splx(int new) 204 { 205 int old; 206 u_int oldirqstate; 207 208 oldirqstate = disable_interrupts(I32_bit); 209 old = curcpl(); 210 set_curcpl(new); 211 if (new != hardware_spl_level) { 212 hardware_spl_level = new; 213 ep93xx_set_intrmask(vic1_imask[new], vic2_imask[new]); 214 } 215 restore_interrupts(oldirqstate); 216 217 #ifdef __HAVE_FAST_SOFTINTS 218 cpu_dosoftints(); 219 #endif 220 } 221 222 int 223 _splraise(int ipl) 224 { 225 int old; 226 u_int oldirqstate; 227 228 oldirqstate = disable_interrupts(I32_bit); 229 old = curcpl(); 230 set_curcpl(ipl); 231 restore_interrupts(oldirqstate); 232 return (old); 233 } 234 235 int 236 _spllower(int ipl) 237 { 238 int old = curcpl(); 239 240 if (old <= ipl) 241 return (old); 242 splx(ipl); 243 return (old); 244 } 245 246 /* 247 * ep93xx_intr_init: 248 * 249 * Initialize the rest of the interrupt subsystem, making it 250 * ready to handle interrupts from devices. 251 */ 252 void 253 ep93xx_intr_init(void) 254 { 255 struct intrq *iq; 256 int i; 257 258 vic1_intr_enabled = 0; 259 vic2_intr_enabled = 0; 260 261 for (i = 0; i < NIRQ; i++) { 262 iq = &intrq[i]; 263 TAILQ_INIT(&iq->iq_list); 264 265 sprintf(iq->iq_name, "irq %d", i); 266 evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR, 267 NULL, (i < VIC_NIRQ ? "vic1" : "vic2"), 268 iq->iq_name); 269 } 270 curcpu()->ci_intr_depth = 0; 271 set_curcpl(0); 272 hardware_spl_level = 0; 273 274 /* All interrupts should use IRQ not FIQ */ 275 VIC1REG(EP93XX_VIC_IntSelect) = 0; 276 VIC2REG(EP93XX_VIC_IntSelect) = 0; 277 278 ep93xx_intr_calculate_masks(); 279 280 /* Enable IRQs (don't yet use FIQs). */ 281 enable_interrupts(I32_bit); 282 } 283 284 void * 285 ep93xx_intr_establish(int irq, int ipl, int (*ih_func)(void *), void *arg) 286 { 287 struct intrq* iq; 288 struct intrhand* ih; 289 u_int oldirqstate; 290 291 if (irq < 0 || irq > NIRQ) 292 panic("ep93xx_intr_establish: IRQ %d out of range", irq); 293 if (ipl < 0 || ipl > NIPL) 294 panic("ep93xx_intr_establish: IPL %d out of range", ipl); 295 296 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 297 if (ih == NULL) 298 return (NULL); 299 300 ih->ih_func = ih_func; 301 ih->ih_arg = arg; 302 ih->ih_irq = irq; 303 ih->ih_ipl = ipl; 304 305 iq = &intrq[irq]; 306 307 oldirqstate = disable_interrupts(I32_bit); 308 TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list); 309 ep93xx_intr_calculate_masks(); 310 restore_interrupts(oldirqstate); 311 312 return (ih); 313 } 314 315 void 316 ep93xx_intr_disestablish(void *cookie) 317 { 318 struct intrhand* ih = cookie; 319 struct intrq* iq = &intrq[ih->ih_irq]; 320 u_int oldirqstate; 321 322 oldirqstate = disable_interrupts(I32_bit); 323 TAILQ_REMOVE(&iq->iq_list, ih, ih_list); 324 ep93xx_intr_calculate_masks(); 325 restore_interrupts(oldirqstate); 326 } 327 328 void 329 ep93xx_intr_dispatch(struct irqframe *frame) 330 { 331 struct intrq* iq; 332 struct intrhand* ih; 333 u_int oldirqstate; 334 int pcpl; 335 u_int32_t vic1_hwpend; 336 u_int32_t vic2_hwpend; 337 int irq; 338 339 pcpl = curcpl(); 340 341 vic1_hwpend = VIC1REG(EP93XX_VIC_IRQStatus); 342 vic2_hwpend = VIC2REG(EP93XX_VIC_IRQStatus); 343 344 hardware_spl_level = pcpl; 345 ep93xx_set_intrmask(vic1_imask[pcpl] | vic1_hwpend, 346 vic2_imask[pcpl] | vic2_hwpend); 347 348 vic1_hwpend &= ~vic1_imask[pcpl]; 349 vic2_hwpend &= ~vic2_imask[pcpl]; 350 351 if (vic1_hwpend) { 352 irq = ffs(vic1_hwpend) - 1; 353 354 iq = &intrq[irq]; 355 iq->iq_ev.ev_count++; 356 uvmexp.intrs++; 357 TAILQ_FOREACH(ih, &iq->iq_list, ih_list) { 358 set_curcpl(ih->ih_ipl); 359 oldirqstate = enable_interrupts(I32_bit); 360 (void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame); 361 restore_interrupts(oldirqstate); 362 } 363 } else if (vic2_hwpend) { 364 irq = ffs(vic2_hwpend) - 1; 365 366 iq = &intrq[irq + VIC_NIRQ]; 367 iq->iq_ev.ev_count++; 368 uvmexp.intrs++; 369 TAILQ_FOREACH(ih, &iq->iq_list, ih_list) { 370 set_curcpl(ih->ih_ipl); 371 oldirqstate = enable_interrupts(I32_bit); 372 (void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame); 373 restore_interrupts(oldirqstate); 374 } 375 } 376 377 set_curcpl(pcpl); 378 hardware_spl_level = pcpl; 379 ep93xx_set_intrmask(vic1_imask[pcpl], vic2_imask[pcpl]); 380 381 #ifdef __HAVE_FAST_SOFTINTS 382 cpu_dosoftints(); 383 #endif 384 } 385
Indexes created Thu Oct 16 14:10:15 GMT 2025