ep93xxreg.h revision 1.2
1 /* $NetBSD: ep93xxreg.h,v 1.2 2005/01/10 23:17:53 joff Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Jesse Off 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Ichiro FUKUHARA. 18 * 4. The name of the company nor the name of the author may be used to 19 * endorse or promote products derived from this software without specific 20 * prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 #ifndef _EP93XXREG_H_ 36 #define _EP93XXREG_H_ 37 38 /* 39 * Physical memory map for the Cirrus Logic EP93XX 40 */ 41 42 /* 43 * FFFF FFFF --------------------------- 44 * Device 12 45 * External SMC CS#0 ROM/SRAM 46 * F000 0000 --------------------------- 47 * Device 11 48 * SDRAM CS#2 49 * E000 0000 --------------------------- 50 * Device 10 51 * SDRAM CS#1 52 * D000 0000 --------------------------- 53 * Device 9 54 * SDRAM CS#0 55 * C000 0000 --------------------------- 56 * Device 8 57 * Not used 58 * 9000 0000 --------------------------- 59 * Device 7 60 * EP93XX System Registers 61 * 8080 0000 - 8094 FFFF 62 * APB Mapped Registers 63 * 8010 0000 - 807F FFFF 64 * Reserved 65 * 8000 0000 - 800F FFFF 66 * AHB Mapped Registers 67 * 8000 0000 --------------------------- 68 * Device 6 69 * External SMC CS#7 ROM/SRAM 70 * 7000 0000 --------------------------- 71 * Device 5 72 * External SMC CS#6 ROM/SRAM 73 * 6000 0000 --------------------------- 74 * Device 4 75 * Reserved 76 * 4000 0000 --------------------------- 77 * Device 3 78 * External SMC CS#3 ROM/SRAM 79 * 3000 0000 --------------------------- 80 * Device 2 81 * External SMC CS#2 ROM/SRAM 82 * 2000 0000 --------------------------- 83 * Device 1 84 * External SMC CS#1 ROM/SRAM 85 * 1000 0000 --------------------------- 86 * Device 0 87 * SDRAM CS#3 88 * 0000 0000 --------------------------- 89 */ 90 91 92 /* 93 * Virtual memory map for the Cirrus Logic EP93XX integrated devices 94 * 95 * Some device registers are staticaly mapped on upper address region. 96 * because we have to access them before bus_space is initialized. 97 * Most device is dynamicaly mapped by bus_space_map(). In this case, 98 * the actual mapped (virtual) address are not cared by device drivers. 99 */ 100 101 /* 102 * FFFF FFFF --------------------------- 103 * not used 104 * F030 0000 --------------------------- 105 * APB bus (2Mbyte) 106 * F010 0000 --------------------------- 107 * AHB bus (1Mbyte) 108 * F000 0000 --------------------------- 109 * Kernel text and data 110 * C000 0000 --------------------------- 111 * 0000 0000 --------------------------- 112 * 113 */ 114 115 /* Virtual address for I/O space */ 116 #define EP93XX_IO_VBASE 0xf0000000UL 117 118 /* EP93xx System and Peripheral Registers */ 119 #define EP93XX_AHB_VBASE 0xf0000000UL 120 #define EP93XX_AHB_HWBASE 0x80000000UL 121 #define EP93XX_AHB_SIZE 0x00100000UL /* 1Mbyte */ 122 #define EP93XX_AHB_VIC1 0x000b0000UL 123 #define EP93XX_AHB_VIC2 0x000c0000UL 124 #define EP93XX_VIC_IRQStatus 0x00000000UL 125 #define EP93XX_VIC_FIQStatus 0x00000004UL 126 #define EP93XX_VIC_RawIntr 0x00000008UL 127 #define EP93XX_VIC_IntSelect 0x0000000cUL 128 #define EP93XX_VIC_IntEnable 0x00000010UL 129 #define EP93XX_VIC_IntEnClear 0x00000014UL 130 #define EP93XX_VIC_SoftInt 0x00000018UL 131 #define EP93XX_VIC_SoftIntClear 0x0000001cUL 132 #define EP93XX_VIC_Protection 0x00000020UL 133 #define EP93XX_VIC_VectAddr 0x00000030UL 134 #define EP93XX_VIC_DefVectAddr 0x00000034UL 135 #define EP93XX_VIC_VectAddr0 0x00000100UL 136 #define EP93XX_VIC_VectCntl0 0x00000200UL 137 #define EP93XX_VIC_PeriphID0 0x00000fe0UL 138 139 #define EP93XX_APB_VBASE 0xf0100000UL 140 #define EP93XX_APB_HWBASE 0x80800000UL 141 #define EP93XX_APB_SIZE 0x00200000UL /* 2Mbyte */ 142 #define EP93XX_APB_GPIO 0x00040000UL 143 #define EP93XX_APB_GPIO_SIZE 0x000000d0UL 144 #define EP93XX_GPIO_PADR 0x00000000UL 145 #define EP93XX_GPIO_PADDR 0x00000010UL 146 #define EP93XX_GPIO_PHDR 0x00000040UL 147 #define EP93XX_GPIO_PHDDR 0x00000044UL 148 #define EP93XX_APB_SYSCON 0x00130000UL 149 #define EP93XX_APB_SYSCON_SIZE 0x000000c0UL 150 #define EP93XX_SYSCON_PwrSts 0x00000000UL 151 #define EP93XX_SYSCON_PwrCnt 0x00000004UL 152 #define PwrCnt_UARTBAUD 0x20000000UL 153 #define EP93XX_SYSCON_TEOI 0x00000018UL 154 #define EP93XX_SYSCON_ClkSet1 0x00000020UL 155 #define EP93XX_SYSCON_ClkSet2 0x00000024UL 156 #define EP93XX_SYSCON_ChipID 0x00000094UL 157 #define EP93XX_APB_TIMERS 0x00010000UL 158 #define EP93XX_TIMERS_Timer4Enable 0x00000064UL 159 #define EP93XX_TIMERS_Timer4ValueHigh 0x00000064UL 160 #define EP93XX_TIMERS_Timer4ValueLow 0x00000060UL 161 #define EP93XX_APB_UART1 0x000c0000UL 162 #define EP93XX_APB_UART2 0x000d0000UL 163 #define EP93XX_APB_UART_SIZE 0x00000220UL 164 #define EP93XX_UART_Flag 0x00000018UL 165 #define EP93XX_UART_Data 0x00000000UL 166 167 #define NIRQ 64 168 #define VIC_NIRQ 32 169 170 #define EP93XX_INTR_bit31 31 171 #define EP93XX_INTR_bit30 30 172 #define EP93XX_INTR_bit29 29 173 #define EP93XX_INTR_bit28 28 174 #define EP93XX_INTR_bit27 27 175 #define EP93XX_INTR_bit26 26 176 #define EP93XX_INTR_bit25 25 177 #define EP93XX_INTR_bit24 24 178 #define EP93XX_INTR_bit23 23 179 #define EP93XX_INTR_bit22 22 180 #define EP93XX_INTR_bit21 21 181 #define EP93XX_INTR_bit20 20 182 #define EP93XX_INTR_bit19 19 183 #define EP93XX_INTR_bit18 18 184 #define EP93XX_INTR_bit17 17 185 #define EP93XX_INTR_bit16 16 186 #define EP93XX_INTR_bit15 15 187 #define EP93XX_INTR_bit14 14 188 #define EP93XX_INTR_bit13 13 189 #define EP93XX_INTR_bit12 12 190 #define EP93XX_INTR_bit11 11 191 #define EP93XX_INTR_bit10 10 192 #define EP93XX_INTR_bit9 9 193 #define EP93XX_INTR_bit8 8 194 #define EP93XX_INTR_bit7 7 195 #define EP93XX_INTR_bit6 6 196 #define EP93XX_INTR_bit5 5 197 #define EP93XX_INTR_bit4 4 198 #define EP93XX_INTR_bit3 3 199 #define EP93XX_INTR_bit2 2 200 #define EP93XX_INTR_bit1 1 201 #define EP93XX_INTR_bit0 0 202 203 #endif /* _EP93XXREG_H_ */ 204
Indexes created Tue Sep 30 17:09:57 GMT 2025