epe.c revision 1.2.2.2
1 1.2.2.2 skrll /* $NetBSD: epe.c,v 1.2.2.2 2005/01/17 19:29:12 skrll Exp $ */ 2 1.2.2.2 skrll 3 1.2.2.2 skrll /* 4 1.2.2.2 skrll * Copyright (c) 2004 Jesse Off 5 1.2.2.2 skrll * All rights reserved. 6 1.2.2.2 skrll * 7 1.2.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.2.2.2 skrll * modification, are permitted provided that the following conditions 9 1.2.2.2 skrll * are met: 10 1.2.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.2.2.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.2.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.2.2.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.2.2.2 skrll * documentation and/or other materials provided with the distribution. 15 1.2.2.2 skrll * 3. All advertising materials mentioning features or use of this software 16 1.2.2.2 skrll * must display the following acknowledgement: 17 1.2.2.2 skrll * This product includes software developed by the NetBSD 18 1.2.2.2 skrll * Foundation, Inc. and its contributors. 19 1.2.2.2 skrll * 4. Neither the name of The NetBSD Foundation nor the names of its 20 1.2.2.2 skrll * contributors may be used to endorse or promote products derived 21 1.2.2.2 skrll * from this software without specific prior written permission. 22 1.2.2.2 skrll * 23 1.2.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 1.2.2.2 skrll * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 1.2.2.2 skrll * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 1.2.2.2 skrll * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 1.2.2.2 skrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 1.2.2.2 skrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 1.2.2.2 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 1.2.2.2 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 1.2.2.2 skrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 1.2.2.2 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 1.2.2.2 skrll * POSSIBILITY OF SUCH DAMAGE. 34 1.2.2.2 skrll */ 35 1.2.2.2 skrll 36 1.2.2.2 skrll #include <sys/cdefs.h> 37 1.2.2.2 skrll __KERNEL_RCSID(0, "$NetBSD: epe.c,v 1.2.2.2 2005/01/17 19:29:12 skrll Exp $"); 38 1.2.2.2 skrll 39 1.2.2.2 skrll #include <sys/types.h> 40 1.2.2.2 skrll #include <sys/param.h> 41 1.2.2.2 skrll #include <sys/systm.h> 42 1.2.2.2 skrll #include <sys/ioctl.h> 43 1.2.2.2 skrll #include <sys/kernel.h> 44 1.2.2.2 skrll #include <sys/proc.h> 45 1.2.2.2 skrll #include <sys/malloc.h> 46 1.2.2.2 skrll #include <sys/time.h> 47 1.2.2.2 skrll #include <sys/device.h> 48 1.2.2.2 skrll #include <uvm/uvm_extern.h> 49 1.2.2.2 skrll 50 1.2.2.2 skrll #include <machine/bus.h> 51 1.2.2.2 skrll #include <machine/intr.h> 52 1.2.2.2 skrll 53 1.2.2.2 skrll #include <arm/cpufunc.h> 54 1.2.2.2 skrll 55 1.2.2.2 skrll #include <arm/ep93xx/epsocvar.h> 56 1.2.2.2 skrll #include <arm/ep93xx/ep93xxvar.h> 57 1.2.2.2 skrll 58 1.2.2.2 skrll #include <net/if.h> 59 1.2.2.2 skrll #include <net/if_dl.h> 60 1.2.2.2 skrll #include <net/if_types.h> 61 1.2.2.2 skrll #include <net/if_media.h> 62 1.2.2.2 skrll #include <net/if_ether.h> 63 1.2.2.2 skrll 64 1.2.2.2 skrll #include <dev/mii/mii.h> 65 1.2.2.2 skrll #include <dev/mii/miivar.h> 66 1.2.2.2 skrll 67 1.2.2.2 skrll #ifdef INET 68 1.2.2.2 skrll #include <netinet/in.h> 69 1.2.2.2 skrll #include <netinet/in_systm.h> 70 1.2.2.2 skrll #include <netinet/in_var.h> 71 1.2.2.2 skrll #include <netinet/ip.h> 72 1.2.2.2 skrll #include <netinet/if_inarp.h> 73 1.2.2.2 skrll #endif 74 1.2.2.2 skrll 75 1.2.2.2 skrll #ifdef NS 76 1.2.2.2 skrll #include <netns/ns.h> 77 1.2.2.2 skrll #include <netns/ns_if.h> 78 1.2.2.2 skrll #endif 79 1.2.2.2 skrll 80 1.2.2.2 skrll #include "bpfilter.h" 81 1.2.2.2 skrll #if NBPFILTER > 0 82 1.2.2.2 skrll #include <net/bpf.h> 83 1.2.2.2 skrll #include <net/bpfdesc.h> 84 1.2.2.2 skrll #endif 85 1.2.2.2 skrll 86 1.2.2.2 skrll #include <machine/bus.h> 87 1.2.2.2 skrll 88 1.2.2.2 skrll #ifdef IPKDB_EP93XX 89 1.2.2.2 skrll #include <ipkdb/ipkdb.h> 90 1.2.2.2 skrll #endif 91 1.2.2.2 skrll 92 1.2.2.2 skrll #include <arm/ep93xx/ep93xxreg.h> 93 1.2.2.2 skrll #include <arm/ep93xx/epereg.h> 94 1.2.2.2 skrll #include <arm/ep93xx/epevar.h> 95 1.2.2.2 skrll 96 1.2.2.2 skrll #ifndef EPE_FAST 97 1.2.2.2 skrll #define EPE_FAST 98 1.2.2.2 skrll #endif 99 1.2.2.2 skrll 100 1.2.2.2 skrll #ifndef EPE_FAST 101 1.2.2.2 skrll #define EPE_READ(x) \ 102 1.2.2.2 skrll bus_space_read_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x)) 103 1.2.2.2 skrll #define EPE_WRITE(x, y) \ 104 1.2.2.2 skrll bus_space_write_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x), (y)) 105 1.2.2.2 skrll #define CTRLPAGE_DMASYNC(x, y, z) \ 106 1.2.2.2 skrll bus_dmamap_sync(sc->sc_dmat, sc->ctrlpage_dmamap, (x), (y), (z)) 107 1.2.2.2 skrll #else 108 1.2.2.2 skrll #define EPE_READ(x) *(__volatile u_int32_t *) \ 109 1.2.2.2 skrll (EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x)) 110 1.2.2.2 skrll #define EPE_WRITE(x, y) *(__volatile u_int32_t *) \ 111 1.2.2.2 skrll (EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x)) = y 112 1.2.2.2 skrll #define CTRLPAGE_DMASYNC(x, y, z) 113 1.2.2.2 skrll #endif /* ! EPE_FAST */ 114 1.2.2.2 skrll 115 1.2.2.2 skrll static int epe_match(struct device *, struct cfdata *, void *); 116 1.2.2.2 skrll static void epe_attach(struct device *, struct device *, void *); 117 1.2.2.2 skrll static void epe_init(struct epe_softc *); 118 1.2.2.2 skrll static int epe_intr(void* arg); 119 1.2.2.2 skrll static int epe_gctx(struct epe_softc *); 120 1.2.2.2 skrll static int epe_mediachange(struct ifnet *); 121 1.2.2.2 skrll static void epe_mediastatus(struct ifnet *, struct ifmediareq *); 122 1.2.2.2 skrll int epe_mii_readreg (struct device *, int, int); 123 1.2.2.2 skrll void epe_mii_writereg (struct device *, int, int, int); 124 1.2.2.2 skrll void epe_statchg (struct device *); 125 1.2.2.2 skrll void epe_tick (void *); 126 1.2.2.2 skrll static int epe_ifioctl (struct ifnet *, u_long, caddr_t); 127 1.2.2.2 skrll static void epe_ifstart (struct ifnet *); 128 1.2.2.2 skrll static void epe_ifwatchdog (struct ifnet *); 129 1.2.2.2 skrll static int epe_ifinit (struct ifnet *); 130 1.2.2.2 skrll static void epe_ifstop (struct ifnet *, int); 131 1.2.2.2 skrll static void epe_setaddr (struct ifnet *); 132 1.2.2.2 skrll 133 1.2.2.2 skrll CFATTACH_DECL(epe, sizeof(struct epe_softc), 134 1.2.2.2 skrll epe_match, epe_attach, NULL, NULL); 135 1.2.2.2 skrll 136 1.2.2.2 skrll static int 137 1.2.2.2 skrll epe_match(struct device *parent, struct cfdata *match, void *aux) 138 1.2.2.2 skrll { 139 1.2.2.2 skrll return 2; 140 1.2.2.2 skrll } 141 1.2.2.2 skrll 142 1.2.2.2 skrll static void 143 1.2.2.2 skrll epe_attach(struct device *parent, struct device *self, void *aux) 144 1.2.2.2 skrll { 145 1.2.2.2 skrll struct epe_softc *sc; 146 1.2.2.2 skrll struct epsoc_attach_args *sa; 147 1.2.2.2 skrll 148 1.2.2.2 skrll printf("\n"); 149 1.2.2.2 skrll sc = (struct epe_softc*) self; 150 1.2.2.2 skrll sa = aux; 151 1.2.2.2 skrll sc->sc_iot = sa->sa_iot; 152 1.2.2.2 skrll sc->sc_intr = sa->sa_intr; 153 1.2.2.2 skrll sc->sc_dmat = sa->sa_dmat; 154 1.2.2.2 skrll 155 1.2.2.2 skrll if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 156 1.2.2.2 skrll 0, &sc->sc_ioh)) 157 1.2.2.2 skrll panic("%s: Cannot map registers", self->dv_xname); 158 1.2.2.2 skrll 159 1.2.2.2 skrll ep93xx_intr_establish(sc->sc_intr, IPL_NET, epe_intr, sc); 160 1.2.2.2 skrll epe_init(sc); 161 1.2.2.2 skrll } 162 1.2.2.2 skrll 163 1.2.2.2 skrll static int 164 1.2.2.2 skrll epe_gctx(struct epe_softc *sc) 165 1.2.2.2 skrll { 166 1.2.2.2 skrll struct ifnet * ifp = &sc->sc_ec.ec_if; 167 1.2.2.2 skrll u_int32_t *cur, ndq = 0; 168 1.2.2.2 skrll 169 1.2.2.2 skrll /* Handle transmit completions */ 170 1.2.2.2 skrll cur = (u_int32_t *)(EPE_READ(TXStsQCurAdd) - 171 1.2.2.2 skrll sc->ctrlpage_dsaddr + sc->ctrlpage); 172 1.2.2.2 skrll 173 1.2.2.2 skrll if (sc->TXStsQ_cur != cur) { 174 1.2.2.2 skrll CTRLPAGE_DMASYNC(TX_QLEN * 2 * sizeof(u_int32_t), 175 1.2.2.2 skrll TX_QLEN * sizeof(u_int32_t), BUS_DMASYNC_PREREAD); 176 1.2.2.2 skrll } else { 177 1.2.2.2 skrll return 0; 178 1.2.2.2 skrll } 179 1.2.2.2 skrll 180 1.2.2.2 skrll do { 181 1.2.2.2 skrll u_int32_t tbi = *sc->TXStsQ_cur & 0x7fff; 182 1.2.2.2 skrll struct mbuf *m = sc->txq[tbi].m; 183 1.2.2.2 skrll 184 1.2.2.2 skrll if ((*sc->TXStsQ_cur & TXStsQ_TxWE) == 0) { 185 1.2.2.2 skrll ifp->if_oerrors++; 186 1.2.2.2 skrll } 187 1.2.2.2 skrll bus_dmamap_unload(sc->sc_dmat, sc->txq[tbi].m_dmamap); 188 1.2.2.2 skrll m_freem(m); 189 1.2.2.2 skrll do { 190 1.2.2.2 skrll sc->txq[tbi].m = NULL; 191 1.2.2.2 skrll ndq++; 192 1.2.2.2 skrll tbi = (tbi + 1) % TX_QLEN; 193 1.2.2.2 skrll } while (sc->txq[tbi].m == m); 194 1.2.2.2 skrll 195 1.2.2.2 skrll ifp->if_opackets++; 196 1.2.2.2 skrll sc->TXStsQ_cur++; 197 1.2.2.2 skrll if (sc->TXStsQ_cur >= sc->TXStsQ + TX_QLEN) { 198 1.2.2.2 skrll sc->TXStsQ_cur = sc->TXStsQ; 199 1.2.2.2 skrll } 200 1.2.2.2 skrll } while (sc->TXStsQ_cur != cur); 201 1.2.2.2 skrll 202 1.2.2.2 skrll sc->TXDQ_avail += ndq; 203 1.2.2.2 skrll if (ifp->if_flags & IFF_OACTIVE) { 204 1.2.2.2 skrll ifp->if_flags &= ~IFF_OACTIVE; 205 1.2.2.2 skrll /* Disable end-of-tx-chain interrupt */ 206 1.2.2.2 skrll EPE_WRITE(IntEn, IntEn_REOFIE); 207 1.2.2.2 skrll } 208 1.2.2.2 skrll return ndq; 209 1.2.2.2 skrll } 210 1.2.2.2 skrll 211 1.2.2.2 skrll static int 212 1.2.2.2 skrll epe_intr(void *arg) 213 1.2.2.2 skrll { 214 1.2.2.2 skrll struct epe_softc *sc = (struct epe_softc *)arg; 215 1.2.2.2 skrll struct ifnet * ifp = &sc->sc_ec.ec_if; 216 1.2.2.2 skrll u_int32_t ndq = 0, irq, *cur; 217 1.2.2.2 skrll 218 1.2.2.2 skrll irq = EPE_READ(IntStsC); 219 1.2.2.2 skrll begin: 220 1.2.2.2 skrll cur = (u_int32_t *)(EPE_READ(RXStsQCurAdd) - 221 1.2.2.2 skrll sc->ctrlpage_dsaddr + sc->ctrlpage); 222 1.2.2.2 skrll CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(u_int32_t), 223 1.2.2.2 skrll RX_QLEN * 4 * sizeof(u_int32_t), 224 1.2.2.2 skrll BUS_DMASYNC_PREREAD); 225 1.2.2.2 skrll while (sc->RXStsQ_cur != cur) { 226 1.2.2.2 skrll if ((sc->RXStsQ_cur[0] & (RXStsQ_RWE|RXStsQ_RFP|RXStsQ_EOB)) == 227 1.2.2.2 skrll (RXStsQ_RWE|RXStsQ_RFP|RXStsQ_EOB)) { 228 1.2.2.2 skrll u_int32_t bi = (sc->RXStsQ_cur[1] >> 16) & 0x7fff; 229 1.2.2.2 skrll u_int32_t fl = sc->RXStsQ_cur[1] & 0xffff; 230 1.2.2.2 skrll struct mbuf *m; 231 1.2.2.2 skrll 232 1.2.2.2 skrll MGETHDR(m, M_DONTWAIT, MT_DATA); 233 1.2.2.2 skrll if (m != NULL) MCLGET(m, M_DONTWAIT); 234 1.2.2.2 skrll if (m != NULL && (m->m_flags & M_EXT)) { 235 1.2.2.2 skrll bus_dmamap_unload(sc->sc_dmat, 236 1.2.2.2 skrll sc->rxq[bi].m_dmamap); 237 1.2.2.2 skrll sc->rxq[bi].m->m_pkthdr.rcvif = ifp; 238 1.2.2.2 skrll sc->rxq[bi].m->m_pkthdr.len = 239 1.2.2.2 skrll sc->rxq[bi].m->m_len = fl; 240 1.2.2.2 skrll #if NBPFILTER > 0 241 1.2.2.2 skrll if (ifp->if_bpf) 242 1.2.2.2 skrll bpf_mtap(ifp->if_bpf, sc->rxq[bi].m); 243 1.2.2.2 skrll #endif /* NBPFILTER > 0 */ 244 1.2.2.2 skrll (*ifp->if_input)(ifp, sc->rxq[bi].m); 245 1.2.2.2 skrll sc->rxq[bi].m = m; 246 1.2.2.2 skrll bus_dmamap_load(sc->sc_dmat, 247 1.2.2.2 skrll sc->rxq[bi].m_dmamap, 248 1.2.2.2 skrll m->m_ext.ext_buf, MCLBYTES, 249 1.2.2.2 skrll NULL, BUS_DMA_NOWAIT); 250 1.2.2.2 skrll sc->RXDQ[bi * 2] = 251 1.2.2.2 skrll sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr; 252 1.2.2.2 skrll } else { 253 1.2.2.2 skrll /* Drop packets until we can get replacement 254 1.2.2.2 skrll * empty mbufs for the RXDQ. 255 1.2.2.2 skrll */ 256 1.2.2.2 skrll if (m != NULL) { 257 1.2.2.2 skrll m_freem(m); 258 1.2.2.2 skrll } 259 1.2.2.2 skrll ifp->if_ierrors++; 260 1.2.2.2 skrll } 261 1.2.2.2 skrll } else { 262 1.2.2.2 skrll ifp->if_ierrors++; 263 1.2.2.2 skrll } 264 1.2.2.2 skrll 265 1.2.2.2 skrll ndq++; 266 1.2.2.2 skrll 267 1.2.2.2 skrll sc->RXStsQ_cur += 2; 268 1.2.2.2 skrll if (sc->RXStsQ_cur >= sc->RXStsQ + (RX_QLEN * 2)) { 269 1.2.2.2 skrll sc->RXStsQ_cur = sc->RXStsQ; 270 1.2.2.2 skrll } 271 1.2.2.2 skrll } 272 1.2.2.2 skrll 273 1.2.2.2 skrll if (ndq > 0) { 274 1.2.2.2 skrll ifp->if_ipackets += ndq; 275 1.2.2.2 skrll CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(u_int32_t), 276 1.2.2.2 skrll RX_QLEN * 4 * sizeof(u_int32_t), 277 1.2.2.2 skrll BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 278 1.2.2.2 skrll EPE_WRITE(RXStsEnq, ndq); 279 1.2.2.2 skrll EPE_WRITE(RXDEnq, ndq); 280 1.2.2.2 skrll ndq = 0; 281 1.2.2.2 skrll } 282 1.2.2.2 skrll 283 1.2.2.2 skrll if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 284 1.2.2.2 skrll epe_ifstart(ifp); 285 1.2.2.2 skrll } 286 1.2.2.2 skrll 287 1.2.2.2 skrll irq = EPE_READ(IntStsC); 288 1.2.2.2 skrll if ((irq & (IntSts_RxSQ|IntSts_ECI)) != 0) 289 1.2.2.2 skrll goto begin; 290 1.2.2.2 skrll 291 1.2.2.2 skrll return (1); 292 1.2.2.2 skrll } 293 1.2.2.2 skrll 294 1.2.2.2 skrll 295 1.2.2.2 skrll static void 296 1.2.2.2 skrll epe_init(struct epe_softc *sc) 297 1.2.2.2 skrll { 298 1.2.2.2 skrll bus_dma_segment_t segs; 299 1.2.2.2 skrll caddr_t addr; 300 1.2.2.2 skrll int rsegs, err, i; 301 1.2.2.2 skrll struct ifnet * ifp = &sc->sc_ec.ec_if; 302 1.2.2.2 skrll 303 1.2.2.2 skrll callout_init(&sc->epe_tick_ch); 304 1.2.2.2 skrll 305 1.2.2.2 skrll /* Select primary Individual Address in Address Filter Pointer */ 306 1.2.2.2 skrll EPE_WRITE(AFP, 0); 307 1.2.2.2 skrll /* Read ethernet MAC, should already be set by bootrom */ 308 1.2.2.2 skrll bus_space_read_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 309 1.2.2.2 skrll sc->sc_enaddr, ETHER_ADDR_LEN); 310 1.2.2.2 skrll printf("%s: MAC address %s\n", sc->sc_dev.dv_xname, 311 1.2.2.2 skrll ether_sprintf(sc->sc_enaddr)); 312 1.2.2.2 skrll 313 1.2.2.2 skrll /* Soft Reset the MAC */ 314 1.2.2.2 skrll EPE_WRITE(SelfCtl, SelfCtl_RESET); 315 1.2.2.2 skrll while(EPE_READ(SelfCtl) & SelfCtl_RESET); 316 1.2.2.2 skrll 317 1.2.2.2 skrll /* suggested magic initialization values from datasheet */ 318 1.2.2.2 skrll EPE_WRITE(RXBufThrshld, 0x800040); 319 1.2.2.2 skrll EPE_WRITE(TXBufThrshld, 0x200010); 320 1.2.2.2 skrll EPE_WRITE(RXStsThrshld, 0x40002); 321 1.2.2.2 skrll EPE_WRITE(TXStsThrshld, 0x40002); 322 1.2.2.2 skrll EPE_WRITE(RXDThrshld, 0x40002); 323 1.2.2.2 skrll EPE_WRITE(TXDThrshld, 0x40002); 324 1.2.2.2 skrll 325 1.2.2.2 skrll /* Allocate a page of memory for descriptor and status queues */ 326 1.2.2.2 skrll err = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, 0, PAGE_SIZE, 327 1.2.2.2 skrll &segs, 1, &rsegs, BUS_DMA_WAITOK); 328 1.2.2.2 skrll if (err == 0) { 329 1.2.2.2 skrll err = bus_dmamem_map(sc->sc_dmat, &segs, 1, PAGE_SIZE, 330 1.2.2.2 skrll &sc->ctrlpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT)); 331 1.2.2.2 skrll } 332 1.2.2.2 skrll if (err == 0) { 333 1.2.2.2 skrll err = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 334 1.2.2.2 skrll 0, BUS_DMA_WAITOK, &sc->ctrlpage_dmamap); 335 1.2.2.2 skrll } 336 1.2.2.2 skrll if (err == 0) { 337 1.2.2.2 skrll err = bus_dmamap_load(sc->sc_dmat, sc->ctrlpage_dmamap, 338 1.2.2.2 skrll sc->ctrlpage, PAGE_SIZE, NULL, BUS_DMA_WAITOK); 339 1.2.2.2 skrll } 340 1.2.2.2 skrll if (err != 0) { 341 1.2.2.2 skrll panic("%s: Cannot get DMA memory", sc->sc_dev.dv_xname); 342 1.2.2.2 skrll } 343 1.2.2.2 skrll sc->ctrlpage_dsaddr = sc->ctrlpage_dmamap->dm_segs[0].ds_addr; 344 1.2.2.2 skrll bzero(sc->ctrlpage, PAGE_SIZE); 345 1.2.2.2 skrll 346 1.2.2.2 skrll /* Set up pointers to start of each queue in kernel addr space. 347 1.2.2.2 skrll * Each descriptor queue or status queue entry uses 2 words 348 1.2.2.2 skrll */ 349 1.2.2.2 skrll sc->TXDQ = (u_int32_t *)sc->ctrlpage; 350 1.2.2.2 skrll sc->TXDQ_cur = sc->TXDQ; 351 1.2.2.2 skrll sc->TXDQ_avail = TX_QLEN - 1; 352 1.2.2.2 skrll sc->TXStsQ = &sc->TXDQ[TX_QLEN * 2]; 353 1.2.2.2 skrll sc->TXStsQ_cur = sc->TXStsQ; 354 1.2.2.2 skrll sc->RXDQ = &sc->TXStsQ[TX_QLEN]; 355 1.2.2.2 skrll sc->RXStsQ = &sc->RXDQ[RX_QLEN * 2]; 356 1.2.2.2 skrll sc->RXStsQ_cur = sc->RXStsQ; 357 1.2.2.2 skrll 358 1.2.2.2 skrll /* Program each queue's start addr, cur addr, and len registers 359 1.2.2.2 skrll * with the physical addresses. 360 1.2.2.2 skrll */ 361 1.2.2.2 skrll addr = (caddr_t)sc->ctrlpage_dmamap->dm_segs[0].ds_addr; 362 1.2.2.2 skrll EPE_WRITE(TXDQBAdd, (u_int32_t)addr); 363 1.2.2.2 skrll EPE_WRITE(TXDQCurAdd, (u_int32_t)addr); 364 1.2.2.2 skrll EPE_WRITE(TXDQBLen, TX_QLEN * 2 * sizeof(u_int32_t)); 365 1.2.2.2 skrll 366 1.2.2.2 skrll addr += (sc->TXStsQ - sc->TXDQ) * sizeof(u_int32_t); 367 1.2.2.2 skrll EPE_WRITE(TXStsQBAdd, (u_int32_t)addr); 368 1.2.2.2 skrll EPE_WRITE(TXStsQCurAdd, (u_int32_t)addr); 369 1.2.2.2 skrll EPE_WRITE(TXStsQBLen, TX_QLEN * sizeof(u_int32_t)); 370 1.2.2.2 skrll 371 1.2.2.2 skrll addr += (sc->RXDQ - sc->TXStsQ) * sizeof(u_int32_t); 372 1.2.2.2 skrll EPE_WRITE(RXDQBAdd, (u_int32_t)addr); 373 1.2.2.2 skrll EPE_WRITE(RXDCurAdd, (u_int32_t)addr); 374 1.2.2.2 skrll EPE_WRITE(RXDQBLen, RX_QLEN * 2 * sizeof(u_int32_t)); 375 1.2.2.2 skrll 376 1.2.2.2 skrll addr += (sc->RXStsQ - sc->RXDQ) * sizeof(u_int32_t); 377 1.2.2.2 skrll EPE_WRITE(RXStsQBAdd, (u_int32_t)addr); 378 1.2.2.2 skrll EPE_WRITE(RXStsQCurAdd, (u_int32_t)addr); 379 1.2.2.2 skrll EPE_WRITE(RXStsQBLen, RX_QLEN * 2 * sizeof(u_int32_t)); 380 1.2.2.2 skrll 381 1.2.2.2 skrll /* Populate the RXDQ with mbufs */ 382 1.2.2.2 skrll for(i = 0; i < RX_QLEN; i++) { 383 1.2.2.2 skrll struct mbuf *m; 384 1.2.2.2 skrll 385 1.2.2.2 skrll bus_dmamap_create(sc->sc_dmat, MCLBYTES, TX_QLEN/4, MCLBYTES, 0, 386 1.2.2.2 skrll BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 387 1.2.2.2 skrll MGETHDR(m, M_WAIT, MT_DATA); 388 1.2.2.2 skrll MCLGET(m, M_WAIT); 389 1.2.2.2 skrll sc->rxq[i].m = m; 390 1.2.2.2 skrll bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 391 1.2.2.2 skrll m->m_ext.ext_buf, MCLBYTES, NULL, 392 1.2.2.2 skrll BUS_DMA_WAITOK); 393 1.2.2.2 skrll 394 1.2.2.2 skrll sc->RXDQ[i * 2] = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr; 395 1.2.2.2 skrll sc->RXDQ[i * 2 + 1] = (i << 16) | MCLBYTES; 396 1.2.2.2 skrll bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 397 1.2.2.2 skrll MCLBYTES, BUS_DMASYNC_PREREAD); 398 1.2.2.2 skrll } 399 1.2.2.2 skrll 400 1.2.2.2 skrll for(i = 0; i < TX_QLEN; i++) { 401 1.2.2.2 skrll bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 402 1.2.2.2 skrll (BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW), 403 1.2.2.2 skrll &sc->txq[i].m_dmamap); 404 1.2.2.2 skrll sc->txq[i].m = NULL; 405 1.2.2.2 skrll sc->TXDQ[i * 2 + 1] = (i << 16); 406 1.2.2.2 skrll } 407 1.2.2.2 skrll 408 1.2.2.2 skrll /* Divide HCLK by 32 for MDC clock */ 409 1.2.2.2 skrll EPE_WRITE(SelfCtl, (SelfCtl_MDCDIV(32)|SelfCtl_PSPRS)); 410 1.2.2.2 skrll 411 1.2.2.2 skrll sc->sc_mii.mii_ifp = ifp; 412 1.2.2.2 skrll sc->sc_mii.mii_readreg = epe_mii_readreg; 413 1.2.2.2 skrll sc->sc_mii.mii_writereg = epe_mii_writereg; 414 1.2.2.2 skrll sc->sc_mii.mii_statchg = epe_statchg; 415 1.2.2.2 skrll ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, epe_mediachange, 416 1.2.2.2 skrll epe_mediastatus); 417 1.2.2.2 skrll mii_attach((struct device *)sc, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 418 1.2.2.2 skrll MII_OFFSET_ANY, 0); 419 1.2.2.2 skrll ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 420 1.2.2.2 skrll 421 1.2.2.2 skrll EPE_WRITE(BMCtl, BMCtl_RxEn|BMCtl_TxEn); 422 1.2.2.2 skrll EPE_WRITE(IntEn, IntEn_REOFIE); 423 1.2.2.2 skrll /* maximum valid max frame length */ 424 1.2.2.2 skrll EPE_WRITE(MaxFrmLen, (0x7ff << 16)|MHLEN); 425 1.2.2.2 skrll /* wait for receiver ready */ 426 1.2.2.2 skrll while((EPE_READ(BMSts) & BMSts_RxAct) == 0); 427 1.2.2.2 skrll /* enqueue the entries in RXStsQ and RXDQ */ 428 1.2.2.2 skrll CTRLPAGE_DMASYNC(0, sc->ctrlpage_dmamap->dm_mapsize, 429 1.2.2.2 skrll BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 430 1.2.2.2 skrll EPE_WRITE(RXDEnq, RX_QLEN - 1); 431 1.2.2.2 skrll EPE_WRITE(RXStsEnq, RX_QLEN - 1); 432 1.2.2.2 skrll 433 1.2.2.2 skrll /* 434 1.2.2.2 skrll * We can support 802.1Q VLAN-sized frames. 435 1.2.2.2 skrll */ 436 1.2.2.2 skrll sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 437 1.2.2.2 skrll 438 1.2.2.2 skrll strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 439 1.2.2.2 skrll ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 440 1.2.2.2 skrll ifp->if_ioctl = epe_ifioctl; 441 1.2.2.2 skrll ifp->if_start = epe_ifstart; 442 1.2.2.2 skrll ifp->if_watchdog = epe_ifwatchdog; 443 1.2.2.2 skrll ifp->if_init = epe_ifinit; 444 1.2.2.2 skrll ifp->if_stop = epe_ifstop; 445 1.2.2.2 skrll ifp->if_timer = 0; 446 1.2.2.2 skrll ifp->if_softc = sc; 447 1.2.2.2 skrll IFQ_SET_READY(&ifp->if_snd); 448 1.2.2.2 skrll if_attach(ifp); 449 1.2.2.2 skrll ether_ifattach(ifp, (sc)->sc_enaddr); 450 1.2.2.2 skrll } 451 1.2.2.2 skrll 452 1.2.2.2 skrll static int 453 1.2.2.2 skrll epe_mediachange(ifp) 454 1.2.2.2 skrll struct ifnet *ifp; 455 1.2.2.2 skrll { 456 1.2.2.2 skrll if (ifp->if_flags & IFF_UP) 457 1.2.2.2 skrll epe_ifinit(ifp); 458 1.2.2.2 skrll return (0); 459 1.2.2.2 skrll } 460 1.2.2.2 skrll 461 1.2.2.2 skrll static void 462 1.2.2.2 skrll epe_mediastatus(ifp, ifmr) 463 1.2.2.2 skrll struct ifnet *ifp; 464 1.2.2.2 skrll struct ifmediareq *ifmr; 465 1.2.2.2 skrll { 466 1.2.2.2 skrll struct epe_softc *sc = ifp->if_softc; 467 1.2.2.2 skrll 468 1.2.2.2 skrll mii_pollstat(&sc->sc_mii); 469 1.2.2.2 skrll ifmr->ifm_active = sc->sc_mii.mii_media_active; 470 1.2.2.2 skrll ifmr->ifm_status = sc->sc_mii.mii_media_status; 471 1.2.2.2 skrll } 472 1.2.2.2 skrll 473 1.2.2.2 skrll 474 1.2.2.2 skrll int 475 1.2.2.2 skrll epe_mii_readreg(self, phy, reg) 476 1.2.2.2 skrll struct device *self; 477 1.2.2.2 skrll int phy, reg; 478 1.2.2.2 skrll { 479 1.2.2.2 skrll u_int32_t d, v; 480 1.2.2.2 skrll struct epe_softc *sc; 481 1.2.2.2 skrll 482 1.2.2.2 skrll sc = (struct epe_softc *)self; 483 1.2.2.2 skrll d = EPE_READ(SelfCtl); 484 1.2.2.2 skrll EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */ 485 1.2.2.2 skrll EPE_WRITE(MIICmd, (MIICmd_READ | (phy << 5) | reg)); 486 1.2.2.2 skrll while(EPE_READ(MIISts) & MIISts_BUSY); 487 1.2.2.2 skrll v = EPE_READ(MIIData); 488 1.2.2.2 skrll EPE_WRITE(SelfCtl, d); /* restore old value */ 489 1.2.2.2 skrll return v; 490 1.2.2.2 skrll } 491 1.2.2.2 skrll 492 1.2.2.2 skrll void 493 1.2.2.2 skrll epe_mii_writereg(self, phy, reg, val) 494 1.2.2.2 skrll struct device *self; 495 1.2.2.2 skrll int phy, reg, val; 496 1.2.2.2 skrll { 497 1.2.2.2 skrll struct epe_softc *sc; 498 1.2.2.2 skrll u_int32_t d; 499 1.2.2.2 skrll 500 1.2.2.2 skrll sc = (struct epe_softc *)self; 501 1.2.2.2 skrll d = EPE_READ(SelfCtl); 502 1.2.2.2 skrll EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */ 503 1.2.2.2 skrll EPE_WRITE(MIICmd, (MIICmd_WRITE | (phy << 5) | reg)); 504 1.2.2.2 skrll EPE_WRITE(MIIData, val); 505 1.2.2.2 skrll while(EPE_READ(MIISts) & MIISts_BUSY); 506 1.2.2.2 skrll EPE_WRITE(SelfCtl, d); /* restore old value */ 507 1.2.2.2 skrll } 508 1.2.2.2 skrll 509 1.2.2.2 skrll 510 1.2.2.2 skrll void 511 1.2.2.2 skrll epe_statchg(self) 512 1.2.2.2 skrll struct device *self; 513 1.2.2.2 skrll { 514 1.2.2.2 skrll struct epe_softc *sc = (struct epe_softc *)self; 515 1.2.2.2 skrll u_int32_t reg; 516 1.2.2.2 skrll 517 1.2.2.2 skrll /* 518 1.2.2.2 skrll * We must keep the MAC and the PHY in sync as 519 1.2.2.2 skrll * to the status of full-duplex! 520 1.2.2.2 skrll */ 521 1.2.2.2 skrll reg = EPE_READ(TestCtl); 522 1.2.2.2 skrll if (sc->sc_mii.mii_media_active & IFM_FDX) 523 1.2.2.2 skrll reg |= TestCtl_MFDX; 524 1.2.2.2 skrll else 525 1.2.2.2 skrll reg &= ~TestCtl_MFDX; 526 1.2.2.2 skrll EPE_WRITE(TestCtl, reg); 527 1.2.2.2 skrll } 528 1.2.2.2 skrll 529 1.2.2.2 skrll void 530 1.2.2.2 skrll epe_tick(arg) 531 1.2.2.2 skrll void *arg; 532 1.2.2.2 skrll { 533 1.2.2.2 skrll struct epe_softc* sc = (struct epe_softc *)arg; 534 1.2.2.2 skrll struct ifnet * ifp = &sc->sc_ec.ec_if; 535 1.2.2.2 skrll int s; 536 1.2.2.2 skrll u_int32_t misses; 537 1.2.2.2 skrll 538 1.2.2.2 skrll ifp->if_collisions += EPE_READ(TXCollCnt); 539 1.2.2.2 skrll /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 540 1.2.2.2 skrll misses = EPE_READ(RXMissCnt); 541 1.2.2.2 skrll if (misses > 0) 542 1.2.2.2 skrll printf("%s: %d rx misses\n", sc->sc_dev.dv_xname, misses); 543 1.2.2.2 skrll 544 1.2.2.2 skrll s = splnet(); 545 1.2.2.2 skrll if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 546 1.2.2.2 skrll epe_ifstart(ifp); 547 1.2.2.2 skrll } 548 1.2.2.2 skrll splx(s); 549 1.2.2.2 skrll 550 1.2.2.2 skrll mii_tick(&sc->sc_mii); 551 1.2.2.2 skrll callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc); 552 1.2.2.2 skrll } 553 1.2.2.2 skrll 554 1.2.2.2 skrll 555 1.2.2.2 skrll static int 556 1.2.2.2 skrll epe_ifioctl(ifp, cmd, data) 557 1.2.2.2 skrll struct ifnet *ifp; 558 1.2.2.2 skrll u_long cmd; 559 1.2.2.2 skrll caddr_t data; 560 1.2.2.2 skrll { 561 1.2.2.2 skrll struct epe_softc *sc = ifp->if_softc; 562 1.2.2.2 skrll struct ifreq *ifr = (struct ifreq *)data; 563 1.2.2.2 skrll int s, error; 564 1.2.2.2 skrll 565 1.2.2.2 skrll s = splnet(); 566 1.2.2.2 skrll switch(cmd) { 567 1.2.2.2 skrll case SIOCSIFMEDIA: 568 1.2.2.2 skrll case SIOCGIFMEDIA: 569 1.2.2.2 skrll error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 570 1.2.2.2 skrll break; 571 1.2.2.2 skrll default: 572 1.2.2.2 skrll error = ether_ioctl(ifp, cmd, data); 573 1.2.2.2 skrll if (error == ENETRESET) { 574 1.2.2.2 skrll if (ifp->if_flags & IFF_RUNNING) 575 1.2.2.2 skrll epe_setaddr(ifp); 576 1.2.2.2 skrll error = 0; 577 1.2.2.2 skrll } 578 1.2.2.2 skrll } 579 1.2.2.2 skrll splx(s); 580 1.2.2.2 skrll return error; 581 1.2.2.2 skrll } 582 1.2.2.2 skrll 583 1.2.2.2 skrll static void 584 1.2.2.2 skrll epe_ifstart(ifp) 585 1.2.2.2 skrll struct ifnet *ifp; 586 1.2.2.2 skrll { 587 1.2.2.2 skrll struct epe_softc *sc = (struct epe_softc *)ifp->if_softc; 588 1.2.2.2 skrll struct mbuf *m; 589 1.2.2.2 skrll bus_dma_segment_t *segs; 590 1.2.2.2 skrll int s, bi, err, nsegs, ndq; 591 1.2.2.2 skrll 592 1.2.2.2 skrll s = splnet(); 593 1.2.2.2 skrll start: 594 1.2.2.2 skrll ndq = 0; 595 1.2.2.2 skrll if (sc->TXDQ_avail == 0) { 596 1.2.2.2 skrll if (epe_gctx(sc) == 0) { 597 1.2.2.2 skrll /* Enable End-Of-TX-Chain interrupt */ 598 1.2.2.2 skrll EPE_WRITE(IntEn, IntEn_REOFIE|IntEn_ECIE); 599 1.2.2.2 skrll ifp->if_flags |= IFF_OACTIVE; 600 1.2.2.2 skrll ifp->if_timer = 10; 601 1.2.2.2 skrll splx(s); 602 1.2.2.2 skrll return; 603 1.2.2.2 skrll } 604 1.2.2.2 skrll } 605 1.2.2.2 skrll 606 1.2.2.2 skrll bi = sc->TXDQ_cur - sc->TXDQ; 607 1.2.2.2 skrll 608 1.2.2.2 skrll IFQ_POLL(&ifp->if_snd, m); 609 1.2.2.2 skrll if (m == NULL) { 610 1.2.2.2 skrll splx(s); 611 1.2.2.2 skrll return; 612 1.2.2.2 skrll } 613 1.2.2.2 skrll more: 614 1.2.2.2 skrll if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 615 1.2.2.2 skrll BUS_DMA_NOWAIT)) || 616 1.2.2.2 skrll sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 617 1.2.2.2 skrll sc->txq[bi].m_dmamap->dm_nsegs > (sc->TXDQ_avail - ndq)) { 618 1.2.2.2 skrll /* Copy entire mbuf chain to new and 32-bit aligned storage */ 619 1.2.2.2 skrll struct mbuf *mn; 620 1.2.2.2 skrll 621 1.2.2.2 skrll if (err == 0) 622 1.2.2.2 skrll bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 623 1.2.2.2 skrll 624 1.2.2.2 skrll MGETHDR(mn, M_DONTWAIT, MT_DATA); 625 1.2.2.2 skrll if (mn == NULL) goto stop; 626 1.2.2.2 skrll if (m->m_pkthdr.len > (MHLEN & (~0x3))) { 627 1.2.2.2 skrll MCLGET(mn, M_DONTWAIT); 628 1.2.2.2 skrll if ((mn->m_flags & M_EXT) == 0) { 629 1.2.2.2 skrll m_freem(mn); 630 1.2.2.2 skrll goto stop; 631 1.2.2.2 skrll } 632 1.2.2.2 skrll } 633 1.2.2.2 skrll mn->m_data = (caddr_t)(((u_int32_t)mn->m_data + 0x3) & (~0x3)); 634 1.2.2.2 skrll m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, caddr_t)); 635 1.2.2.2 skrll mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 636 1.2.2.2 skrll IFQ_DEQUEUE(&ifp->if_snd, m); 637 1.2.2.2 skrll m_freem(m); 638 1.2.2.2 skrll m = mn; 639 1.2.2.2 skrll bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 640 1.2.2.2 skrll BUS_DMA_NOWAIT); 641 1.2.2.2 skrll } else { 642 1.2.2.2 skrll IFQ_DEQUEUE(&ifp->if_snd, m); 643 1.2.2.2 skrll } 644 1.2.2.2 skrll 645 1.2.2.2 skrll #if NBPFILTER > 0 646 1.2.2.2 skrll if (ifp->if_bpf) 647 1.2.2.2 skrll bpf_mtap(ifp->if_bpf, m); 648 1.2.2.2 skrll #endif /* NBPFILTER > 0 */ 649 1.2.2.2 skrll 650 1.2.2.2 skrll nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 651 1.2.2.2 skrll segs = sc->txq[bi].m_dmamap->dm_segs; 652 1.2.2.2 skrll bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 653 1.2.2.2 skrll sc->txq[bi].m_dmamap->dm_mapsize, 654 1.2.2.2 skrll BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 655 1.2.2.2 skrll 656 1.2.2.2 skrll /* XXX: This driver hasn't been tested w/nsegs > 1 */ 657 1.2.2.2 skrll while (nsegs > 0) { 658 1.2.2.2 skrll nsegs--; 659 1.2.2.2 skrll sc->txq[bi].m = m; 660 1.2.2.2 skrll sc->TXDQ[bi * 2] = segs->ds_addr; 661 1.2.2.2 skrll if (nsegs == 0) 662 1.2.2.2 skrll sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16) | 663 1.2.2.2 skrll (1 << 31); 664 1.2.2.2 skrll else 665 1.2.2.2 skrll sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16); 666 1.2.2.2 skrll segs++; 667 1.2.2.2 skrll bi = (bi + 1) % TX_QLEN; 668 1.2.2.2 skrll ndq++; 669 1.2.2.2 skrll } 670 1.2.2.2 skrll 671 1.2.2.2 skrll 672 1.2.2.2 skrll /* 673 1.2.2.2 skrll * Enqueue another. Don't do more than half the available 674 1.2.2.2 skrll * descriptors before telling the MAC about them 675 1.2.2.2 skrll */ 676 1.2.2.2 skrll if ((sc->TXDQ_avail - ndq) > 0 && ndq < TX_QLEN / 2) { 677 1.2.2.2 skrll IFQ_POLL(&ifp->if_snd, m); 678 1.2.2.2 skrll if (m != NULL) { 679 1.2.2.2 skrll goto more; 680 1.2.2.2 skrll } 681 1.2.2.2 skrll } 682 1.2.2.2 skrll stop: 683 1.2.2.2 skrll if (ndq > 0) { 684 1.2.2.2 skrll sc->TXDQ_avail -= ndq; 685 1.2.2.2 skrll sc->TXDQ_cur = &sc->TXDQ[bi]; 686 1.2.2.2 skrll CTRLPAGE_DMASYNC(0, TX_QLEN * 2 * sizeof(u_int32_t), 687 1.2.2.2 skrll BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 688 1.2.2.2 skrll EPE_WRITE(TXDEnq, ndq); 689 1.2.2.2 skrll } 690 1.2.2.2 skrll 691 1.2.2.2 skrll if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 692 1.2.2.2 skrll goto start; 693 1.2.2.2 skrll 694 1.2.2.2 skrll splx(s); 695 1.2.2.2 skrll return; 696 1.2.2.2 skrll } 697 1.2.2.2 skrll 698 1.2.2.2 skrll static void 699 1.2.2.2 skrll epe_ifwatchdog(ifp) 700 1.2.2.2 skrll struct ifnet *ifp; 701 1.2.2.2 skrll { 702 1.2.2.2 skrll struct epe_softc *sc = (struct epe_softc *)ifp->if_softc; 703 1.2.2.2 skrll 704 1.2.2.2 skrll if ((ifp->if_flags & IFF_RUNNING) == 0) 705 1.2.2.2 skrll return; 706 1.2.2.2 skrll printf("%s: device timeout, BMCtl = 0x%08x, BMSts = 0x%08x\n", 707 1.2.2.2 skrll sc->sc_dev.dv_xname, EPE_READ(BMCtl), EPE_READ(BMSts)); 708 1.2.2.2 skrll } 709 1.2.2.2 skrll 710 1.2.2.2 skrll static int 711 1.2.2.2 skrll epe_ifinit(ifp) 712 1.2.2.2 skrll struct ifnet *ifp; 713 1.2.2.2 skrll { 714 1.2.2.2 skrll struct epe_softc *sc = ifp->if_softc; 715 1.2.2.2 skrll int s = splnet(); 716 1.2.2.2 skrll 717 1.2.2.2 skrll callout_stop(&sc->epe_tick_ch); 718 1.2.2.2 skrll EPE_WRITE(RXCtl, RXCtl_IA0|RXCtl_BA|RXCtl_RCRCA|RXCtl_SRxON); 719 1.2.2.2 skrll EPE_WRITE(TXCtl, TXCtl_STxON); 720 1.2.2.2 skrll EPE_WRITE(GIIntMsk, GIIntMsk_INT); /* start interrupting */ 721 1.2.2.2 skrll mii_mediachg(&sc->sc_mii); 722 1.2.2.2 skrll callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc); 723 1.2.2.2 skrll ifp->if_flags |= IFF_RUNNING; 724 1.2.2.2 skrll splx(s); 725 1.2.2.2 skrll return 0; 726 1.2.2.2 skrll } 727 1.2.2.2 skrll 728 1.2.2.2 skrll static void 729 1.2.2.2 skrll epe_ifstop(ifp, disable) 730 1.2.2.2 skrll struct ifnet *ifp; 731 1.2.2.2 skrll int disable; 732 1.2.2.2 skrll { 733 1.2.2.2 skrll struct epe_softc *sc = ifp->if_softc; 734 1.2.2.2 skrll 735 1.2.2.2 skrll 736 1.2.2.2 skrll EPE_WRITE(RXCtl, 0); 737 1.2.2.2 skrll EPE_WRITE(TXCtl, 0); 738 1.2.2.2 skrll EPE_WRITE(GIIntMsk, 0); 739 1.2.2.2 skrll callout_stop(&sc->epe_tick_ch); 740 1.2.2.2 skrll 741 1.2.2.2 skrll /* Down the MII. */ 742 1.2.2.2 skrll mii_down(&sc->sc_mii); 743 1.2.2.2 skrll 744 1.2.2.2 skrll ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 745 1.2.2.2 skrll ifp->if_timer = 0; 746 1.2.2.2 skrll sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 747 1.2.2.2 skrll } 748 1.2.2.2 skrll 749 1.2.2.2 skrll static void 750 1.2.2.2 skrll epe_setaddr(ifp) 751 1.2.2.2 skrll struct ifnet *ifp; 752 1.2.2.2 skrll { 753 1.2.2.2 skrll struct epe_softc *sc = ifp->if_softc; 754 1.2.2.2 skrll struct ethercom *ac = &sc->sc_ec; 755 1.2.2.2 skrll struct ether_multi *enm; 756 1.2.2.2 skrll struct ether_multistep step; 757 1.2.2.2 skrll u_int8_t ias[2][ETHER_ADDR_LEN]; 758 1.2.2.2 skrll u_int32_t h, nma = 0, hashes[2] = { 0, 0 }; 759 1.2.2.2 skrll u_int32_t rxctl = EPE_READ(RXCtl); 760 1.2.2.2 skrll 761 1.2.2.2 skrll /* disable receiver temporarily */ 762 1.2.2.2 skrll EPE_WRITE(RXCtl, rxctl & ~RXCtl_SRxON); 763 1.2.2.2 skrll 764 1.2.2.2 skrll rxctl &= ~(RXCtl_MA|RXCtl_PA|RXCtl_IA2|RXCtl_IA3); 765 1.2.2.2 skrll 766 1.2.2.2 skrll if (ifp->if_flags & IFF_PROMISC) { 767 1.2.2.2 skrll rxctl |= RXCtl_PA; 768 1.2.2.2 skrll } 769 1.2.2.2 skrll 770 1.2.2.2 skrll ifp->if_flags &= ~IFF_ALLMULTI; 771 1.2.2.2 skrll 772 1.2.2.2 skrll ETHER_FIRST_MULTI(step, ac, enm); 773 1.2.2.2 skrll while (enm != NULL) { 774 1.2.2.2 skrll if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 775 1.2.2.2 skrll /* 776 1.2.2.2 skrll * We must listen to a range of multicast addresses. 777 1.2.2.2 skrll * For now, just accept all multicasts, rather than 778 1.2.2.2 skrll * trying to set only those filter bits needed to match 779 1.2.2.2 skrll * the range. (At this time, the only use of address 780 1.2.2.2 skrll * ranges is for IP multicast routing, for which the 781 1.2.2.2 skrll * range is big enough to require all bits set.) 782 1.2.2.2 skrll */ 783 1.2.2.2 skrll rxctl &= ~(RXCtl_IA2|RXCtl_IA3); 784 1.2.2.2 skrll rxctl |= RXCtl_MA; 785 1.2.2.2 skrll hashes[0] = 0xffffffffUL; 786 1.2.2.2 skrll hashes[1] = 0xffffffffUL; 787 1.2.2.2 skrll ifp->if_flags |= IFF_ALLMULTI; 788 1.2.2.2 skrll break; 789 1.2.2.2 skrll } 790 1.2.2.2 skrll 791 1.2.2.2 skrll if (nma < 2) { 792 1.2.2.2 skrll /* We can program 2 perfect address filters for mcast */ 793 1.2.2.2 skrll memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 794 1.2.2.2 skrll rxctl |= (1 << (nma + 2)); 795 1.2.2.2 skrll } else { 796 1.2.2.2 skrll /* 797 1.2.2.2 skrll * XXX: Datasheet is not very clear here, I'm not sure 798 1.2.2.2 skrll * if I'm doing this right. --joff 799 1.2.2.2 skrll */ 800 1.2.2.2 skrll h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 801 1.2.2.2 skrll 802 1.2.2.2 skrll /* Just want the 6 most-significant bits. */ 803 1.2.2.2 skrll h = h >> 26; 804 1.2.2.2 skrll 805 1.2.2.2 skrll hashes[ h / 32 ] |= (1 << (h % 32)); 806 1.2.2.2 skrll rxctl |= RXCtl_MA; 807 1.2.2.2 skrll } 808 1.2.2.2 skrll ETHER_NEXT_MULTI(step, enm); 809 1.2.2.2 skrll nma++; 810 1.2.2.2 skrll } 811 1.2.2.2 skrll 812 1.2.2.2 skrll EPE_WRITE(AFP, 0); 813 1.2.2.2 skrll bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 814 1.2.2.2 skrll sc->sc_enaddr, ETHER_ADDR_LEN); 815 1.2.2.2 skrll if (rxctl & RXCtl_IA2) { 816 1.2.2.2 skrll EPE_WRITE(AFP, 2); 817 1.2.2.2 skrll bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 818 1.2.2.2 skrll ias[0], ETHER_ADDR_LEN); 819 1.2.2.2 skrll } 820 1.2.2.2 skrll if (rxctl & RXCtl_IA3) { 821 1.2.2.2 skrll EPE_WRITE(AFP, 3); 822 1.2.2.2 skrll bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 823 1.2.2.2 skrll ias[1], ETHER_ADDR_LEN); 824 1.2.2.2 skrll } 825 1.2.2.2 skrll if (hashes[0] != 0 && hashes[1] != 0) { 826 1.2.2.2 skrll EPE_WRITE(AFP, 7); 827 1.2.2.2 skrll EPE_WRITE(HashTbl, hashes[0]); 828 1.2.2.2 skrll EPE_WRITE(HashTbl + 4, hashes[1]); 829 1.2.2.2 skrll } 830 1.2.2.2 skrll EPE_WRITE(RXCtl, rxctl); 831 1.2.2.2 skrll } 832
Indexes created Sat Nov 01 05:10:12 GMT 2025