epe.c revision 1.1
1 /* $NetBSD: epe.c,v 1.1 2004/12/22 19:11:10 joff Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Jesse Off 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: epe.c,v 1.1 2004/12/22 19:11:10 joff Exp $"); 38 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/ioctl.h> 43 #include <sys/kernel.h> 44 #include <sys/proc.h> 45 #include <sys/malloc.h> 46 #include <sys/time.h> 47 #include <sys/device.h> 48 #include <uvm/uvm_extern.h> 49 50 #include <machine/bus.h> 51 #include <machine/intr.h> 52 53 #include <arm/cpufunc.h> 54 55 #include <arm/ep93xx/epsocvar.h> 56 #include <arm/ep93xx/ep93xxvar.h> 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_types.h> 61 #include <net/if_media.h> 62 #include <net/if_ether.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #ifdef INET 68 #include <netinet/in.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/in_var.h> 71 #include <netinet/ip.h> 72 #include <netinet/if_inarp.h> 73 #endif 74 75 #ifdef NS 76 #include <netns/ns.h> 77 #include <netns/ns_if.h> 78 #endif 79 80 #include "bpfilter.h" 81 #if NBPFILTER > 0 82 #include <net/bpf.h> 83 #include <net/bpfdesc.h> 84 #endif 85 86 #include <machine/bus.h> 87 88 #ifdef IPKDB_EP93XX 89 #include <ipkdb/ipkdb.h> 90 #endif 91 92 #include <arm/ep93xx/epereg.h> 93 #include <arm/ep93xx/epevar.h> 94 95 96 #define EPE_READ(x) \ 97 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x)) 98 #define EPE_WRITE(x, y) \ 99 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x), (y)) 100 101 static int epe_match(struct device *, struct cfdata *, void *); 102 static void epe_attach(struct device *, struct device *, void *); 103 static void epe_init(struct epe_softc *); 104 static int epe_intr(void* arg); 105 static int epe_mediachange(struct ifnet *); 106 static void epe_mediastatus(struct ifnet *, struct ifmediareq *); 107 int epe_mii_readreg (struct device *, int, int); 108 void epe_mii_writereg (struct device *, int, int, int); 109 void epe_statchg (struct device *); 110 void epe_tick (void *); 111 static int epe_ifioctl (struct ifnet *, u_long, caddr_t); 112 static void epe_ifstart (struct ifnet *); 113 static void epe_ifwatchdog (struct ifnet *); 114 static int epe_ifinit (struct ifnet *); 115 static void epe_ifstop (struct ifnet *, int); 116 static void epe_setaddr (struct ifnet *); 117 118 CFATTACH_DECL(epe, sizeof(struct epe_softc), 119 epe_match, epe_attach, NULL, NULL); 120 121 static int 122 epe_match(struct device *parent, struct cfdata *match, void *aux) 123 { 124 return 2; 125 } 126 127 static void 128 epe_attach(struct device *parent, struct device *self, void *aux) 129 { 130 struct epe_softc *sc; 131 struct epsoc_attach_args *sa; 132 133 printf("\n"); 134 sc = (struct epe_softc*) self; 135 sa = aux; 136 sc->sc_iot = sa->sa_iot; 137 sc->sc_intr = sa->sa_intr; 138 sc->sc_dmat = sa->sa_dmat; 139 140 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 141 0, &sc->sc_ioh)) 142 panic("%s: Cannot map registers", self->dv_xname); 143 144 ep93xx_intr_establish(sc->sc_intr, IPL_NET, epe_intr, sc); 145 epe_init(sc); 146 } 147 148 static int 149 epe_intr(void *arg) 150 { 151 struct epe_softc *sc = (struct epe_softc *)arg; 152 struct ifnet * ifp = &sc->sc_ec.ec_if; 153 u_int32_t ndq = 0, irq, *cur; 154 155 irq = EPE_READ(IntStsC); 156 begin: 157 if ((irq & IntSts_RxSQ) == 0) goto txq; 158 cur = (u_int32_t *)(EPE_READ(RXStsQCurAdd) - 159 sc->ctrlpage_dmamap->dm_segs[0].ds_addr + 160 sc->ctrlpage); 161 bus_dmamap_sync(sc->sc_dmat, sc->ctrlpage_dmamap, 162 TX_QLEN * 3 * sizeof(u_int32_t), 163 RX_QLEN * 4 * sizeof(u_int32_t), 164 BUS_DMASYNC_PREREAD); 165 while (sc->RXStsQ_cur != cur) { 166 if ((sc->RXStsQ_cur[0] & (RXStsQ_RWE|RXStsQ_RFP|RXStsQ_EOB)) == 167 (RXStsQ_RWE|RXStsQ_RFP|RXStsQ_EOB)) { 168 u_int32_t bi = (sc->RXStsQ_cur[1] >> 16) & 0x7fff; 169 u_int32_t fl = sc->RXStsQ_cur[1] & 0xffff; 170 struct mbuf *m; 171 172 bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 173 0, fl, BUS_DMASYNC_PREREAD); 174 MGETHDR(m, M_DONTWAIT, MT_DATA); 175 if (m != NULL) MCLGET(m, M_DONTWAIT); 176 if (m != NULL && (m->m_flags & M_EXT)) { 177 bus_dmamap_unload(sc->sc_dmat, 178 sc->rxq[bi].m_dmamap); 179 sc->rxq[bi].m->m_pkthdr.rcvif = ifp; 180 sc->rxq[bi].m->m_pkthdr.len = 181 sc->rxq[bi].m->m_len = fl; 182 #if NBPFILTER > 0 183 if (ifp->if_bpf) 184 bpf_mtap(ifp->if_bpf, sc->rxq[bi].m); 185 #endif /* NBPFILTER > 0 */ 186 (*ifp->if_input)(ifp, sc->rxq[bi].m); 187 sc->rxq[bi].m = m; 188 bus_dmamap_load(sc->sc_dmat, 189 sc->rxq[bi].m_dmamap, 190 m->m_ext.ext_buf, MCLBYTES, 191 NULL, BUS_DMA_NOWAIT); 192 sc->RXDQ[bi * 2] = 193 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr; 194 bus_dmamap_sync(sc->sc_dmat, 195 sc->rxq[bi].m_dmamap, 0, MCLBYTES, 196 BUS_DMASYNC_PREREAD); 197 } else { 198 /* Drop packets until we can get replacement 199 * empty mbufs for the RXDQ. 200 */ 201 if (m != NULL) { 202 m_freem(m); 203 } 204 ifp->if_ierrors++; 205 } 206 } else { 207 ifp->if_ierrors++; 208 } 209 210 ndq++; 211 212 sc->RXStsQ_cur += 2; 213 if (sc->RXStsQ_cur >= sc->RXStsQ + (RX_QLEN * 2)) { 214 sc->RXStsQ_cur = sc->RXStsQ; 215 } 216 } 217 218 if (ndq > 0) { 219 ifp->if_ipackets += ndq; 220 bus_dmamap_sync(sc->sc_dmat, sc->ctrlpage_dmamap, 221 TX_QLEN * 3 * sizeof(u_int32_t), 222 RX_QLEN * 4 * sizeof(u_int32_t), 223 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 224 EPE_WRITE(RXStsEnq, ndq); 225 EPE_WRITE(RXDEnq, ndq); 226 ndq = 0; 227 } 228 229 txq: 230 if ((irq & IntSts_TxSQ) == 0) 231 goto end; 232 233 /* Handle transmit completions */ 234 cur = (u_int32_t *)(EPE_READ(TXStsQCurAdd) - 235 sc->ctrlpage_dmamap->dm_segs[0].ds_addr + 236 sc->ctrlpage); 237 bus_dmamap_sync(sc->sc_dmat, sc->ctrlpage_dmamap, 238 TX_QLEN * 2 * sizeof(u_int32_t), 239 TX_QLEN * sizeof(u_int32_t), BUS_DMASYNC_PREREAD); 240 while (sc->TXStsQ_cur != cur) { 241 u_int32_t tbi = *sc->TXStsQ_cur & 0x7fff; 242 struct mbuf *m = sc->txq[tbi].m; 243 244 if ((*sc->TXStsQ_cur & TXStsQ_TxWE) == 0) { 245 ifp->if_oerrors++; 246 } 247 bus_dmamap_unload(sc->sc_dmat, sc->txq[tbi].m_dmamap); 248 m_freem(m); 249 do { 250 sc->txq[tbi].m = NULL; 251 ndq++; 252 tbi = (tbi + 1) % TX_QLEN; 253 } while (sc->txq[tbi].m == m); 254 255 ifp->if_opackets++; 256 sc->TXStsQ_cur++; 257 if (sc->TXStsQ_cur >= sc->TXStsQ + TX_QLEN) { 258 sc->TXStsQ_cur = sc->TXStsQ; 259 } 260 } 261 262 if (ndq > 0) { 263 sc->TXDQ_avail += ndq; 264 if (sc->TXDQ_avail == TX_QLEN - 1) { 265 ifp->if_flags &= ~IFF_OACTIVE; 266 ifp->if_timer = 0; 267 } else { 268 ifp->if_timer = 10; 269 } 270 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0 && 271 sc->TXDQ_avail > TX_QLEN / 2) epe_ifstart(ifp); 272 ndq = 0; 273 } 274 275 end: 276 irq = EPE_READ(IntStsC); 277 if ((irq & (IntSts_TxSQ|IntSts_RxSQ)) != 0) 278 goto begin; 279 return (1); 280 } 281 282 283 static void 284 epe_init(struct epe_softc *sc) 285 { 286 bus_dma_segment_t segs; 287 caddr_t addr; 288 int rsegs, err, i; 289 struct ifnet * ifp = &sc->sc_ec.ec_if; 290 291 callout_init(&sc->epe_tick_ch); 292 293 /* Select primary Individual Address in Address Filter Pointer */ 294 EPE_WRITE(AFP, 0); 295 /* Read ethernet MAC, should already be set by bootrom */ 296 bus_space_read_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 297 sc->sc_enaddr, ETHER_ADDR_LEN); 298 printf("%s: MAC address %s\n", sc->sc_dev.dv_xname, 299 ether_sprintf(sc->sc_enaddr)); 300 301 /* Soft Reset the MAC */ 302 EPE_WRITE(SelfCtl, SelfCtl_RESET); 303 while(EPE_READ(SelfCtl) & SelfCtl_RESET); 304 305 /* suggested magic initialization values from datasheet */ 306 EPE_WRITE(RXBufThrshld, 0x800040); 307 EPE_WRITE(TXBufThrshld, 0x200010); 308 EPE_WRITE(RXStsThrshld, 0x40002); 309 EPE_WRITE(TXStsThrshld, 0x40002); 310 EPE_WRITE(RXDThrshld, 0x40002); 311 EPE_WRITE(TXDThrshld, 0x40002); 312 313 /* Allocate a page of memory for descriptor and status queues */ 314 err = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, 0, PAGE_SIZE, 315 &segs, 1, &rsegs, BUS_DMA_WAITOK); 316 if (err == 0) { 317 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, PAGE_SIZE, 318 &sc->ctrlpage, (BUS_DMA_WAITOK)); 319 } 320 if (err == 0) { 321 err = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 322 0, BUS_DMA_WAITOK, &sc->ctrlpage_dmamap); 323 } 324 if (err == 0) { 325 err = bus_dmamap_load(sc->sc_dmat, sc->ctrlpage_dmamap, 326 sc->ctrlpage, PAGE_SIZE, NULL, BUS_DMA_WAITOK); 327 } 328 if (err != 0) { 329 panic("%s: Cannot get DMA memory", sc->sc_dev.dv_xname); 330 } 331 bzero(sc->ctrlpage, PAGE_SIZE); 332 333 /* Set up pointers to start of each queue in kernel addr space. 334 * Each descriptor queue or status queue entry uses 2 words 335 */ 336 sc->TXDQ = (u_int32_t *)sc->ctrlpage; 337 sc->TXDQ_cur = sc->TXDQ; 338 sc->TXDQ_avail = TX_QLEN - 1; 339 sc->TXStsQ = &sc->TXDQ[TX_QLEN * 2]; 340 sc->TXStsQ_cur = sc->TXStsQ; 341 sc->RXDQ = &sc->TXStsQ[TX_QLEN]; 342 sc->RXStsQ = &sc->RXDQ[RX_QLEN * 2]; 343 sc->RXStsQ_cur = sc->RXStsQ; 344 345 /* Program each queue's start addr, cur addr, and len registers 346 * with the physical addresses. 347 */ 348 addr = (caddr_t)sc->ctrlpage_dmamap->dm_segs[0].ds_addr; 349 EPE_WRITE(TXDQBAdd, (u_int32_t)addr); 350 EPE_WRITE(TXDQCurAdd, (u_int32_t)addr); 351 EPE_WRITE(TXDQBLen, TX_QLEN * 2 * sizeof(u_int32_t)); 352 353 addr += (sc->TXStsQ - sc->TXDQ) * sizeof(u_int32_t); 354 EPE_WRITE(TXStsQBAdd, (u_int32_t)addr); 355 EPE_WRITE(TXStsQCurAdd, (u_int32_t)addr); 356 EPE_WRITE(TXStsQBLen, TX_QLEN * sizeof(u_int32_t)); 357 358 addr += (sc->RXDQ - sc->TXStsQ) * sizeof(u_int32_t); 359 EPE_WRITE(RXDQBAdd, (u_int32_t)addr); 360 EPE_WRITE(RXDCurAdd, (u_int32_t)addr); 361 EPE_WRITE(RXDQBLen, RX_QLEN * 2 * sizeof(u_int32_t)); 362 363 addr += (sc->RXStsQ - sc->RXDQ) * sizeof(u_int32_t); 364 EPE_WRITE(RXStsQBAdd, (u_int32_t)addr); 365 EPE_WRITE(RXStsQCurAdd, (u_int32_t)addr); 366 EPE_WRITE(RXStsQBLen, RX_QLEN * 2 * sizeof(u_int32_t)); 367 368 /* Populate the RXDQ with mbufs */ 369 for(i = 0; i < RX_QLEN; i++) { 370 struct mbuf *m; 371 372 bus_dmamap_create(sc->sc_dmat, MCLBYTES, TX_QLEN/4, MCLBYTES, 0, 373 BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 374 MGETHDR(m, M_WAIT, MT_DATA); 375 MCLGET(m, M_WAIT); 376 sc->rxq[i].m = m; 377 bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 378 m->m_ext.ext_buf, MCLBYTES, NULL, 379 BUS_DMA_WAITOK); 380 381 sc->RXDQ[i * 2] = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr; 382 sc->RXDQ[i * 2 + 1] = (i << 16) | MCLBYTES; 383 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 384 MCLBYTES, BUS_DMASYNC_PREREAD); 385 } 386 387 for(i = 0; i < TX_QLEN; i++) { 388 bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 389 (BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW), 390 &sc->txq[i].m_dmamap); 391 sc->txq[i].m = NULL; 392 sc->TXDQ[i * 2 + 1] = (i << 16); 393 } 394 395 /* Divide HCLK by 32 for MDC clock */ 396 EPE_WRITE(SelfCtl, (SelfCtl_MDCDIV(32)|SelfCtl_PSPRS)); 397 398 sc->sc_mii.mii_ifp = ifp; 399 sc->sc_mii.mii_readreg = epe_mii_readreg; 400 sc->sc_mii.mii_writereg = epe_mii_writereg; 401 sc->sc_mii.mii_statchg = epe_statchg; 402 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, epe_mediachange, 403 epe_mediastatus); 404 mii_attach((struct device *)sc, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 405 MII_OFFSET_ANY, 0); 406 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 407 408 EPE_WRITE(BMCtl, BMCtl_RxEn|BMCtl_TxEn); 409 EPE_WRITE(IntEn, IntEn_TSQIE|IntEn_REOFIE); 410 /* maximum valid max frame length */ 411 EPE_WRITE(MaxFrmLen, (0x7ff << 16)|MHLEN); 412 /* wait for receiver ready */ 413 while((EPE_READ(BMSts) & BMSts_RxAct) == 0); 414 /* enqueue the entries in RXStsQ and RXDQ */ 415 bus_dmamap_sync(sc->sc_dmat, sc->ctrlpage_dmamap, 0, 416 sc->ctrlpage_dmamap->dm_mapsize, 417 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 418 EPE_WRITE(RXDEnq, RX_QLEN - 1); 419 EPE_WRITE(RXStsEnq, RX_QLEN - 1); 420 421 /* 422 * We can support 802.1Q VLAN-sized frames. 423 */ 424 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 425 426 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 427 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 428 ifp->if_ioctl = epe_ifioctl; 429 ifp->if_start = epe_ifstart; 430 ifp->if_watchdog = epe_ifwatchdog; 431 ifp->if_init = epe_ifinit; 432 ifp->if_stop = epe_ifstop; 433 ifp->if_timer = 0; 434 ifp->if_softc = sc; 435 IFQ_SET_READY(&ifp->if_snd); 436 if_attach(ifp); 437 ether_ifattach(ifp, (sc)->sc_enaddr); 438 } 439 440 static int 441 epe_mediachange(ifp) 442 struct ifnet *ifp; 443 { 444 if (ifp->if_flags & IFF_UP) 445 epe_ifinit(ifp); 446 return (0); 447 } 448 449 static void 450 epe_mediastatus(ifp, ifmr) 451 struct ifnet *ifp; 452 struct ifmediareq *ifmr; 453 { 454 struct epe_softc *sc = ifp->if_softc; 455 456 mii_pollstat(&sc->sc_mii); 457 ifmr->ifm_active = sc->sc_mii.mii_media_active; 458 ifmr->ifm_status = sc->sc_mii.mii_media_status; 459 } 460 461 462 int 463 epe_mii_readreg(self, phy, reg) 464 struct device *self; 465 int phy, reg; 466 { 467 struct epe_softc *sc = (struct epe_softc *)self; 468 u_int32_t d, v; 469 470 d = EPE_READ(SelfCtl); 471 EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */ 472 EPE_WRITE(MIICmd, (MIICmd_READ | (phy << 5) | reg)); 473 while(EPE_READ(MIISts) & MIISts_BUSY); 474 v = EPE_READ(MIIData); 475 EPE_WRITE(SelfCtl, d); /* restore old value */ 476 return v; 477 } 478 479 void 480 epe_mii_writereg(self, phy, reg, val) 481 struct device *self; 482 int phy, reg, val; 483 { 484 struct epe_softc *sc = (struct epe_softc *)self; 485 u_int32_t d; 486 487 d = EPE_READ(SelfCtl); 488 EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */ 489 EPE_WRITE(MIICmd, (MIICmd_WRITE | (phy << 5) | reg)); 490 EPE_WRITE(MIIData, val); 491 while(EPE_READ(MIISts) & MIISts_BUSY); 492 EPE_WRITE(SelfCtl, d); /* restore old value */ 493 } 494 495 496 void 497 epe_statchg(self) 498 struct device *self; 499 { 500 struct epe_softc *sc = (struct epe_softc *)self; 501 u_int32_t reg; 502 503 /* 504 * We must keep the MAC and the PHY in sync as 505 * to the status of full-duplex! 506 */ 507 reg = EPE_READ(TestCtl); 508 if (sc->sc_mii.mii_media_active & IFM_FDX) 509 reg |= TestCtl_MFDX; 510 else 511 reg &= ~TestCtl_MFDX; 512 EPE_WRITE(TestCtl, reg); 513 } 514 515 void 516 epe_tick(arg) 517 void *arg; 518 { 519 struct epe_softc* sc = (struct epe_softc *)arg; 520 struct ifnet * ifp = &sc->sc_ec.ec_if; 521 u_int32_t misses; 522 523 ifp->if_collisions += EPE_READ(TXCollCnt); 524 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 525 misses = EPE_READ(RXMissCnt); 526 if (misses > 0) 527 printf("%s: %d rx misses\n", sc->sc_dev.dv_xname, misses); 528 529 mii_tick(&sc->sc_mii); 530 callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc); 531 } 532 533 534 static int 535 epe_ifioctl(ifp, cmd, data) 536 struct ifnet *ifp; 537 u_long cmd; 538 caddr_t data; 539 { 540 struct epe_softc *sc = ifp->if_softc; 541 struct ifreq *ifr = (struct ifreq *)data; 542 int s, error; 543 544 s = splnet(); 545 switch(cmd) { 546 case SIOCSIFMEDIA: 547 case SIOCGIFMEDIA: 548 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 549 break; 550 default: 551 error = ether_ioctl(ifp, cmd, data); 552 if (error == ENETRESET) { 553 if (ifp->if_flags & IFF_RUNNING) 554 epe_setaddr(ifp); 555 error = 0; 556 } 557 } 558 splx(s); 559 return error; 560 } 561 562 static void 563 epe_ifstart(ifp) 564 struct ifnet *ifp; 565 { 566 struct epe_softc *sc = (struct epe_softc *)ifp->if_softc; 567 struct mbuf *m; 568 bus_dma_segment_t *segs; 569 int s, bi, err, nsegs, ndq = 0; 570 571 s = splnet(); 572 if (sc->TXDQ_avail == 0) { 573 splx(s); 574 return; 575 } 576 bi = sc->TXDQ_cur - sc->TXDQ; 577 578 IFQ_POLL(&ifp->if_snd, m); 579 if (m == NULL) { 580 splx(s); 581 return; 582 } 583 again: 584 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 585 BUS_DMA_NOWAIT)) || 586 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 587 sc->txq[bi].m_dmamap->dm_nsegs > (sc->TXDQ_avail - ndq)) { 588 /* Copy entire mbuf chain to new and 32-bit aligned storage */ 589 struct mbuf *mn; 590 591 if (err == 0) 592 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 593 594 MGETHDR(mn, M_DONTWAIT, MT_DATA); 595 if (mn == NULL) goto stop; 596 if (m->m_pkthdr.len > (MHLEN & (~0x3))) { 597 MCLGET(mn, M_DONTWAIT); 598 if ((mn->m_flags & M_EXT) == 0) { 599 m_freem(mn); 600 goto stop; 601 } 602 } 603 mn->m_data = (caddr_t)(((u_int32_t)mn->m_data + 0x3) & (~0x3)); 604 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, caddr_t)); 605 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 606 IFQ_DEQUEUE(&ifp->if_snd, m); 607 m_freem(m); 608 m = mn; 609 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 610 BUS_DMA_NOWAIT); 611 } else { 612 IFQ_DEQUEUE(&ifp->if_snd, m); 613 } 614 615 #if NBPFILTER > 0 616 if (ifp->if_bpf) 617 bpf_mtap(ifp->if_bpf, m); 618 #endif /* NBPFILTER > 0 */ 619 620 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 621 segs = sc->txq[bi].m_dmamap->dm_segs; 622 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 623 sc->txq[bi].m_dmamap->dm_mapsize, 624 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 625 626 /* XXX: This driver hasn't been tested w/nsegs > 1 */ 627 while (nsegs > 0) { 628 nsegs--; 629 sc->txq[bi].m = m; 630 sc->TXDQ[bi * 2] = segs->ds_addr; 631 if (nsegs == 0) 632 sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16) | 633 (1 << 31); 634 else 635 sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16); 636 segs++; 637 bi = (bi + 1) % TX_QLEN; 638 ndq++; 639 } 640 641 642 if ((sc->TXDQ_avail - ndq) > 0) { 643 IFQ_POLL(&ifp->if_snd, m); 644 if (m != NULL) { 645 goto again; 646 } 647 } 648 stop: 649 if (ndq > 0) { 650 sc->TXDQ_avail -= ndq; 651 ifp->if_flags |= IFF_OACTIVE; 652 ifp->if_timer = 10; 653 sc->TXDQ_cur = &sc->TXDQ[bi]; 654 bus_dmamap_sync(sc->sc_dmat, sc->ctrlpage_dmamap, 0, 655 TX_QLEN * 2 * sizeof(u_int32_t), 656 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 657 EPE_WRITE(TXDEnq, ndq); 658 } 659 splx(s); 660 661 return; 662 } 663 664 static void 665 epe_ifwatchdog(ifp) 666 struct ifnet *ifp; 667 { 668 struct epe_softc *sc = (struct epe_softc *)ifp->if_softc; 669 670 if ((ifp->if_flags & IFF_RUNNING) == 0) 671 return; 672 printf("%s: device timeout, BMCtl = 0x%08x, BMSts = 0x%08x\n", 673 sc->sc_dev.dv_xname, EPE_READ(BMCtl), EPE_READ(BMSts)); 674 } 675 676 static int 677 epe_ifinit(ifp) 678 struct ifnet *ifp; 679 { 680 struct epe_softc *sc = ifp->if_softc; 681 int s = splnet(); 682 683 callout_stop(&sc->epe_tick_ch); 684 EPE_WRITE(RXCtl, RXCtl_IA0|RXCtl_BA|RXCtl_RCRCA|RXCtl_SRxON); 685 EPE_WRITE(TXCtl, TXCtl_STxON); 686 EPE_WRITE(GIIntMsk, GIIntMsk_INT); /* start interrupting */ 687 mii_mediachg(&sc->sc_mii); 688 callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc); 689 ifp->if_flags |= IFF_RUNNING; 690 splx(s); 691 return 0; 692 } 693 694 static void 695 epe_ifstop(ifp, disable) 696 struct ifnet *ifp; 697 int disable; 698 { 699 struct epe_softc *sc = ifp->if_softc; 700 701 702 EPE_WRITE(RXCtl, 0); 703 EPE_WRITE(TXCtl, 0); 704 EPE_WRITE(GIIntMsk, 0); 705 callout_stop(&sc->epe_tick_ch); 706 707 /* Down the MII. */ 708 mii_down(&sc->sc_mii); 709 710 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 711 ifp->if_timer = 0; 712 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 713 } 714 715 static void 716 epe_setaddr(ifp) 717 struct ifnet *ifp; 718 { 719 struct epe_softc *sc = ifp->if_softc; 720 struct ethercom *ac = &sc->sc_ec; 721 struct ether_multi *enm; 722 struct ether_multistep step; 723 u_int8_t ias[2][ETHER_ADDR_LEN]; 724 u_int32_t h, nma = 0, hashes[2] = { 0, 0 }; 725 u_int32_t rxctl = EPE_READ(RXCtl); 726 727 /* disable receiver temporarily */ 728 EPE_WRITE(RXCtl, rxctl & ~RXCtl_SRxON); 729 730 rxctl &= ~(RXCtl_MA|RXCtl_PA|RXCtl_IA2|RXCtl_IA3); 731 732 if (ifp->if_flags & IFF_PROMISC) { 733 rxctl |= RXCtl_PA; 734 } 735 736 ifp->if_flags &= ~IFF_ALLMULTI; 737 738 ETHER_FIRST_MULTI(step, ac, enm); 739 while (enm != NULL) { 740 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 741 /* 742 * We must listen to a range of multicast addresses. 743 * For now, just accept all multicasts, rather than 744 * trying to set only those filter bits needed to match 745 * the range. (At this time, the only use of address 746 * ranges is for IP multicast routing, for which the 747 * range is big enough to require all bits set.) 748 */ 749 rxctl &= ~(RXCtl_IA2|RXCtl_IA3); 750 rxctl |= RXCtl_MA; 751 hashes[0] = 0xffffffffUL; 752 hashes[1] = 0xffffffffUL; 753 ifp->if_flags |= IFF_ALLMULTI; 754 break; 755 } 756 757 if (nma < 2) { 758 /* We can program 2 perfect address filters for mcast */ 759 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 760 rxctl |= (1 << (nma + 2)); 761 } else { 762 /* 763 * XXX: Datasheet is not very clear here, I'm not sure 764 * if I'm doing this right. --joff 765 */ 766 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 767 768 /* Just want the 6 most-significant bits. */ 769 h = h >> 26; 770 771 hashes[ h / 32 ] |= (1 << (h % 32)); 772 rxctl |= RXCtl_MA; 773 } 774 ETHER_NEXT_MULTI(step, enm); 775 nma++; 776 } 777 778 EPE_WRITE(AFP, 0); 779 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 780 sc->sc_enaddr, ETHER_ADDR_LEN); 781 if (rxctl & RXCtl_IA2) { 782 EPE_WRITE(AFP, 2); 783 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 784 ias[0], ETHER_ADDR_LEN); 785 } 786 if (rxctl & RXCtl_IA3) { 787 EPE_WRITE(AFP, 3); 788 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 789 ias[1], ETHER_ADDR_LEN); 790 } 791 if (hashes[0] != 0 && hashes[1] != 0) { 792 EPE_WRITE(AFP, 7); 793 EPE_WRITE(HashTbl, hashes[0]); 794 EPE_WRITE(HashTbl + 4, hashes[1]); 795 } 796 EPE_WRITE(RXCtl, rxctl); 797 } 798
Indexes created Tue Sep 30 20:09:53 GMT 2025