epe.c revision 1.14
1 /* $NetBSD: epe.c,v 1.14 2008/01/19 13:11:09 chris Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Jesse Off 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: epe.c,v 1.14 2008/01/19 13:11:09 chris Exp $"); 38 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/ioctl.h> 43 #include <sys/kernel.h> 44 #include <sys/proc.h> 45 #include <sys/malloc.h> 46 #include <sys/time.h> 47 #include <sys/device.h> 48 #include <uvm/uvm_extern.h> 49 50 #include <machine/bus.h> 51 #include <machine/intr.h> 52 53 #include <arm/cpufunc.h> 54 55 #include <arm/ep93xx/epsocvar.h> 56 #include <arm/ep93xx/ep93xxvar.h> 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_types.h> 61 #include <net/if_media.h> 62 #include <net/if_ether.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #ifdef INET 68 #include <netinet/in.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/in_var.h> 71 #include <netinet/ip.h> 72 #include <netinet/if_inarp.h> 73 #endif 74 75 #ifdef NS 76 #include <netns/ns.h> 77 #include <netns/ns_if.h> 78 #endif 79 80 #include "bpfilter.h" 81 #if NBPFILTER > 0 82 #include <net/bpf.h> 83 #include <net/bpfdesc.h> 84 #endif 85 86 #include <arm/ep93xx/ep93xxreg.h> 87 #include <arm/ep93xx/epereg.h> 88 #include <arm/ep93xx/epevar.h> 89 90 #define DEFAULT_MDCDIV 32 91 92 #ifndef EPE_FAST 93 #define EPE_FAST 94 #endif 95 96 #ifndef EPE_FAST 97 #define EPE_READ(x) \ 98 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x)) 99 #define EPE_WRITE(x, y) \ 100 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x), (y)) 101 #define CTRLPAGE_DMASYNC(x, y, z) \ 102 bus_dmamap_sync(sc->sc_dmat, sc->ctrlpage_dmamap, (x), (y), (z)) 103 #else 104 #define EPE_READ(x) *(volatile u_int32_t *) \ 105 (EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x)) 106 #define EPE_WRITE(x, y) *(volatile u_int32_t *) \ 107 (EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x)) = y 108 #define CTRLPAGE_DMASYNC(x, y, z) 109 #endif /* ! EPE_FAST */ 110 111 static int epe_match(struct device *, struct cfdata *, void *); 112 static void epe_attach(struct device *, struct device *, void *); 113 static void epe_init(struct epe_softc *); 114 static int epe_intr(void* arg); 115 static int epe_gctx(struct epe_softc *); 116 static int epe_mediachange(struct ifnet *); 117 static void epe_mediastatus(struct ifnet *, struct ifmediareq *); 118 int epe_mii_readreg (struct device *, int, int); 119 void epe_mii_writereg (struct device *, int, int, int); 120 void epe_statchg (struct device *); 121 void epe_tick (void *); 122 static int epe_ifioctl (struct ifnet *, u_long, void *); 123 static void epe_ifstart (struct ifnet *); 124 static void epe_ifwatchdog (struct ifnet *); 125 static int epe_ifinit (struct ifnet *); 126 static void epe_ifstop (struct ifnet *, int); 127 static void epe_setaddr (struct ifnet *); 128 129 CFATTACH_DECL(epe, sizeof(struct epe_softc), 130 epe_match, epe_attach, NULL, NULL); 131 132 static int 133 epe_match(struct device *parent, struct cfdata *match, void *aux) 134 { 135 return 2; 136 } 137 138 static void 139 epe_attach(struct device *parent, struct device *self, void *aux) 140 { 141 struct epe_softc *sc; 142 struct epsoc_attach_args *sa; 143 prop_data_t enaddr; 144 145 printf("\n"); 146 sc = (struct epe_softc*) self; 147 sa = aux; 148 sc->sc_iot = sa->sa_iot; 149 sc->sc_intr = sa->sa_intr; 150 sc->sc_dmat = sa->sa_dmat; 151 152 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 153 0, &sc->sc_ioh)) 154 panic("%s: Cannot map registers", self->dv_xname); 155 156 /* Fetch the Ethernet address from property if set. */ 157 enaddr = prop_dictionary_get(device_properties(self), "mac-addr"); 158 if (enaddr != NULL) { 159 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 160 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 161 memcpy(sc->sc_enaddr, prop_data_data_nocopy(enaddr), 162 ETHER_ADDR_LEN); 163 bus_space_write_4(sc->sc_iot, sc->sc_ioh, EPE_AFP, 0); 164 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 165 sc->sc_enaddr, ETHER_ADDR_LEN); 166 } 167 168 ep93xx_intr_establish(sc->sc_intr, IPL_NET, epe_intr, sc); 169 epe_init(sc); 170 } 171 172 static int 173 epe_gctx(struct epe_softc *sc) 174 { 175 struct ifnet * ifp = &sc->sc_ec.ec_if; 176 u_int32_t *cur, ndq = 0; 177 178 /* Handle transmit completions */ 179 cur = (u_int32_t *)(EPE_READ(TXStsQCurAdd) - 180 sc->ctrlpage_dsaddr + (char*)sc->ctrlpage); 181 182 if (sc->TXStsQ_cur != cur) { 183 CTRLPAGE_DMASYNC(TX_QLEN * 2 * sizeof(u_int32_t), 184 TX_QLEN * sizeof(u_int32_t), BUS_DMASYNC_PREREAD); 185 } else { 186 return 0; 187 } 188 189 do { 190 u_int32_t tbi = *sc->TXStsQ_cur & 0x7fff; 191 struct mbuf *m = sc->txq[tbi].m; 192 193 if ((*sc->TXStsQ_cur & TXStsQ_TxWE) == 0) { 194 ifp->if_oerrors++; 195 } 196 bus_dmamap_unload(sc->sc_dmat, sc->txq[tbi].m_dmamap); 197 m_freem(m); 198 do { 199 sc->txq[tbi].m = NULL; 200 ndq++; 201 tbi = (tbi + 1) % TX_QLEN; 202 } while (sc->txq[tbi].m == m); 203 204 ifp->if_opackets++; 205 sc->TXStsQ_cur++; 206 if (sc->TXStsQ_cur >= sc->TXStsQ + TX_QLEN) { 207 sc->TXStsQ_cur = sc->TXStsQ; 208 } 209 } while (sc->TXStsQ_cur != cur); 210 211 sc->TXDQ_avail += ndq; 212 if (ifp->if_flags & IFF_OACTIVE) { 213 ifp->if_flags &= ~IFF_OACTIVE; 214 /* Disable end-of-tx-chain interrupt */ 215 EPE_WRITE(IntEn, IntEn_REOFIE); 216 } 217 return ndq; 218 } 219 220 static int 221 epe_intr(void *arg) 222 { 223 struct epe_softc *sc = (struct epe_softc *)arg; 224 struct ifnet * ifp = &sc->sc_ec.ec_if; 225 u_int32_t ndq = 0, irq, *cur; 226 227 irq = EPE_READ(IntStsC); 228 begin: 229 cur = (u_int32_t *)(EPE_READ(RXStsQCurAdd) - 230 sc->ctrlpage_dsaddr + (char*)sc->ctrlpage); 231 CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(u_int32_t), 232 RX_QLEN * 4 * sizeof(u_int32_t), 233 BUS_DMASYNC_PREREAD); 234 while (sc->RXStsQ_cur != cur) { 235 if ((sc->RXStsQ_cur[0] & (RXStsQ_RWE|RXStsQ_RFP|RXStsQ_EOB)) == 236 (RXStsQ_RWE|RXStsQ_RFP|RXStsQ_EOB)) { 237 u_int32_t bi = (sc->RXStsQ_cur[1] >> 16) & 0x7fff; 238 u_int32_t fl = sc->RXStsQ_cur[1] & 0xffff; 239 struct mbuf *m; 240 241 MGETHDR(m, M_DONTWAIT, MT_DATA); 242 if (m != NULL) MCLGET(m, M_DONTWAIT); 243 if (m != NULL && (m->m_flags & M_EXT)) { 244 bus_dmamap_unload(sc->sc_dmat, 245 sc->rxq[bi].m_dmamap); 246 sc->rxq[bi].m->m_pkthdr.rcvif = ifp; 247 sc->rxq[bi].m->m_pkthdr.len = 248 sc->rxq[bi].m->m_len = fl; 249 #if NBPFILTER > 0 250 if (ifp->if_bpf) 251 bpf_mtap(ifp->if_bpf, sc->rxq[bi].m); 252 #endif /* NBPFILTER > 0 */ 253 (*ifp->if_input)(ifp, sc->rxq[bi].m); 254 sc->rxq[bi].m = m; 255 bus_dmamap_load(sc->sc_dmat, 256 sc->rxq[bi].m_dmamap, 257 m->m_ext.ext_buf, MCLBYTES, 258 NULL, BUS_DMA_NOWAIT); 259 sc->RXDQ[bi * 2] = 260 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr; 261 } else { 262 /* Drop packets until we can get replacement 263 * empty mbufs for the RXDQ. 264 */ 265 if (m != NULL) { 266 m_freem(m); 267 } 268 ifp->if_ierrors++; 269 } 270 } else { 271 ifp->if_ierrors++; 272 } 273 274 ndq++; 275 276 sc->RXStsQ_cur += 2; 277 if (sc->RXStsQ_cur >= sc->RXStsQ + (RX_QLEN * 2)) { 278 sc->RXStsQ_cur = sc->RXStsQ; 279 } 280 } 281 282 if (ndq > 0) { 283 ifp->if_ipackets += ndq; 284 CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(u_int32_t), 285 RX_QLEN * 4 * sizeof(u_int32_t), 286 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 287 EPE_WRITE(RXStsEnq, ndq); 288 EPE_WRITE(RXDEnq, ndq); 289 ndq = 0; 290 } 291 292 if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 293 epe_ifstart(ifp); 294 } 295 296 irq = EPE_READ(IntStsC); 297 if ((irq & (IntSts_RxSQ|IntSts_ECI)) != 0) 298 goto begin; 299 300 return (1); 301 } 302 303 304 static void 305 epe_init(struct epe_softc *sc) 306 { 307 bus_dma_segment_t segs; 308 char *addr; 309 int rsegs, err, i; 310 struct ifnet * ifp = &sc->sc_ec.ec_if; 311 int mdcdiv = DEFAULT_MDCDIV; 312 313 callout_init(&sc->epe_tick_ch, 0); 314 315 /* Select primary Individual Address in Address Filter Pointer */ 316 EPE_WRITE(AFP, 0); 317 /* Read ethernet MAC, should already be set by bootrom */ 318 bus_space_read_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 319 sc->sc_enaddr, ETHER_ADDR_LEN); 320 printf("%s: MAC address %s\n", sc->sc_dev.dv_xname, 321 ether_sprintf(sc->sc_enaddr)); 322 323 /* Soft Reset the MAC */ 324 EPE_WRITE(SelfCtl, SelfCtl_RESET); 325 while(EPE_READ(SelfCtl) & SelfCtl_RESET); 326 327 /* suggested magic initialization values from datasheet */ 328 EPE_WRITE(RXBufThrshld, 0x800040); 329 EPE_WRITE(TXBufThrshld, 0x200010); 330 EPE_WRITE(RXStsThrshld, 0x40002); 331 EPE_WRITE(TXStsThrshld, 0x40002); 332 EPE_WRITE(RXDThrshld, 0x40002); 333 EPE_WRITE(TXDThrshld, 0x40002); 334 335 /* Allocate a page of memory for descriptor and status queues */ 336 err = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, 0, PAGE_SIZE, 337 &segs, 1, &rsegs, BUS_DMA_WAITOK); 338 if (err == 0) { 339 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, PAGE_SIZE, 340 &sc->ctrlpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT)); 341 } 342 if (err == 0) { 343 err = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 344 0, BUS_DMA_WAITOK, &sc->ctrlpage_dmamap); 345 } 346 if (err == 0) { 347 err = bus_dmamap_load(sc->sc_dmat, sc->ctrlpage_dmamap, 348 sc->ctrlpage, PAGE_SIZE, NULL, BUS_DMA_WAITOK); 349 } 350 if (err != 0) { 351 panic("%s: Cannot get DMA memory", sc->sc_dev.dv_xname); 352 } 353 sc->ctrlpage_dsaddr = sc->ctrlpage_dmamap->dm_segs[0].ds_addr; 354 bzero(sc->ctrlpage, PAGE_SIZE); 355 356 /* Set up pointers to start of each queue in kernel addr space. 357 * Each descriptor queue or status queue entry uses 2 words 358 */ 359 sc->TXDQ = (u_int32_t *)sc->ctrlpage; 360 sc->TXDQ_cur = sc->TXDQ; 361 sc->TXDQ_avail = TX_QLEN - 1; 362 sc->TXStsQ = &sc->TXDQ[TX_QLEN * 2]; 363 sc->TXStsQ_cur = sc->TXStsQ; 364 sc->RXDQ = &sc->TXStsQ[TX_QLEN]; 365 sc->RXStsQ = &sc->RXDQ[RX_QLEN * 2]; 366 sc->RXStsQ_cur = sc->RXStsQ; 367 368 /* Program each queue's start addr, cur addr, and len registers 369 * with the physical addresses. 370 */ 371 addr = (char *)sc->ctrlpage_dmamap->dm_segs[0].ds_addr; 372 EPE_WRITE(TXDQBAdd, (u_int32_t)addr); 373 EPE_WRITE(TXDQCurAdd, (u_int32_t)addr); 374 EPE_WRITE(TXDQBLen, TX_QLEN * 2 * sizeof(u_int32_t)); 375 376 addr += (sc->TXStsQ - sc->TXDQ) * sizeof(u_int32_t); 377 EPE_WRITE(TXStsQBAdd, (u_int32_t)addr); 378 EPE_WRITE(TXStsQCurAdd, (u_int32_t)addr); 379 EPE_WRITE(TXStsQBLen, TX_QLEN * sizeof(u_int32_t)); 380 381 addr += (sc->RXDQ - sc->TXStsQ) * sizeof(u_int32_t); 382 EPE_WRITE(RXDQBAdd, (u_int32_t)addr); 383 EPE_WRITE(RXDCurAdd, (u_int32_t)addr); 384 EPE_WRITE(RXDQBLen, RX_QLEN * 2 * sizeof(u_int32_t)); 385 386 addr += (sc->RXStsQ - sc->RXDQ) * sizeof(u_int32_t); 387 EPE_WRITE(RXStsQBAdd, (u_int32_t)addr); 388 EPE_WRITE(RXStsQCurAdd, (u_int32_t)addr); 389 EPE_WRITE(RXStsQBLen, RX_QLEN * 2 * sizeof(u_int32_t)); 390 391 /* Populate the RXDQ with mbufs */ 392 for(i = 0; i < RX_QLEN; i++) { 393 struct mbuf *m; 394 395 bus_dmamap_create(sc->sc_dmat, MCLBYTES, TX_QLEN/4, MCLBYTES, 0, 396 BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 397 MGETHDR(m, M_WAIT, MT_DATA); 398 MCLGET(m, M_WAIT); 399 sc->rxq[i].m = m; 400 bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 401 m->m_ext.ext_buf, MCLBYTES, NULL, 402 BUS_DMA_WAITOK); 403 404 sc->RXDQ[i * 2] = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr; 405 sc->RXDQ[i * 2 + 1] = (i << 16) | MCLBYTES; 406 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 407 MCLBYTES, BUS_DMASYNC_PREREAD); 408 } 409 410 for(i = 0; i < TX_QLEN; i++) { 411 bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 412 (BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW), 413 &sc->txq[i].m_dmamap); 414 sc->txq[i].m = NULL; 415 sc->TXDQ[i * 2 + 1] = (i << 16); 416 } 417 418 /* Divide HCLK by 32 for MDC clock */ 419 if (device_cfdata(&sc->sc_dev)->cf_flags) 420 mdcdiv = device_cfdata(&sc->sc_dev)->cf_flags; 421 EPE_WRITE(SelfCtl, (SelfCtl_MDCDIV(mdcdiv)|SelfCtl_PSPRS)); 422 423 sc->sc_mii.mii_ifp = ifp; 424 sc->sc_mii.mii_readreg = epe_mii_readreg; 425 sc->sc_mii.mii_writereg = epe_mii_writereg; 426 sc->sc_mii.mii_statchg = epe_statchg; 427 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, epe_mediachange, 428 epe_mediastatus); 429 mii_attach((struct device *)sc, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 430 MII_OFFSET_ANY, 0); 431 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 432 433 EPE_WRITE(BMCtl, BMCtl_RxEn|BMCtl_TxEn); 434 EPE_WRITE(IntEn, IntEn_REOFIE); 435 /* maximum valid max frame length */ 436 EPE_WRITE(MaxFrmLen, (0x7ff << 16)|MHLEN); 437 /* wait for receiver ready */ 438 while((EPE_READ(BMSts) & BMSts_RxAct) == 0); 439 /* enqueue the entries in RXStsQ and RXDQ */ 440 CTRLPAGE_DMASYNC(0, sc->ctrlpage_dmamap->dm_mapsize, 441 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 442 EPE_WRITE(RXDEnq, RX_QLEN - 1); 443 EPE_WRITE(RXStsEnq, RX_QLEN - 1); 444 445 /* 446 * We can support 802.1Q VLAN-sized frames. 447 */ 448 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 449 450 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 451 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 452 ifp->if_ioctl = epe_ifioctl; 453 ifp->if_start = epe_ifstart; 454 ifp->if_watchdog = epe_ifwatchdog; 455 ifp->if_init = epe_ifinit; 456 ifp->if_stop = epe_ifstop; 457 ifp->if_timer = 0; 458 ifp->if_softc = sc; 459 IFQ_SET_READY(&ifp->if_snd); 460 if_attach(ifp); 461 ether_ifattach(ifp, (sc)->sc_enaddr); 462 } 463 464 static int 465 epe_mediachange(ifp) 466 struct ifnet *ifp; 467 { 468 if (ifp->if_flags & IFF_UP) 469 epe_ifinit(ifp); 470 return (0); 471 } 472 473 static void 474 epe_mediastatus(ifp, ifmr) 475 struct ifnet *ifp; 476 struct ifmediareq *ifmr; 477 { 478 struct epe_softc *sc = ifp->if_softc; 479 480 mii_pollstat(&sc->sc_mii); 481 ifmr->ifm_active = sc->sc_mii.mii_media_active; 482 ifmr->ifm_status = sc->sc_mii.mii_media_status; 483 } 484 485 486 int 487 epe_mii_readreg(self, phy, reg) 488 struct device *self; 489 int phy, reg; 490 { 491 u_int32_t d, v; 492 struct epe_softc *sc; 493 494 sc = (struct epe_softc *)self; 495 d = EPE_READ(SelfCtl); 496 EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */ 497 EPE_WRITE(MIICmd, (MIICmd_READ | (phy << 5) | reg)); 498 while(EPE_READ(MIISts) & MIISts_BUSY); 499 v = EPE_READ(MIIData); 500 EPE_WRITE(SelfCtl, d); /* restore old value */ 501 return v; 502 } 503 504 void 505 epe_mii_writereg(self, phy, reg, val) 506 struct device *self; 507 int phy, reg, val; 508 { 509 struct epe_softc *sc; 510 u_int32_t d; 511 512 sc = (struct epe_softc *)self; 513 d = EPE_READ(SelfCtl); 514 EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */ 515 EPE_WRITE(MIIData, val); 516 EPE_WRITE(MIICmd, (MIICmd_WRITE | (phy << 5) | reg)); 517 while(EPE_READ(MIISts) & MIISts_BUSY); 518 EPE_WRITE(SelfCtl, d); /* restore old value */ 519 } 520 521 522 void 523 epe_statchg(self) 524 struct device *self; 525 { 526 struct epe_softc *sc = (struct epe_softc *)self; 527 u_int32_t reg; 528 529 /* 530 * We must keep the MAC and the PHY in sync as 531 * to the status of full-duplex! 532 */ 533 reg = EPE_READ(TestCtl); 534 if (sc->sc_mii.mii_media_active & IFM_FDX) 535 reg |= TestCtl_MFDX; 536 else 537 reg &= ~TestCtl_MFDX; 538 EPE_WRITE(TestCtl, reg); 539 } 540 541 void 542 epe_tick(arg) 543 void *arg; 544 { 545 struct epe_softc* sc = (struct epe_softc *)arg; 546 struct ifnet * ifp = &sc->sc_ec.ec_if; 547 int s; 548 u_int32_t misses; 549 550 ifp->if_collisions += EPE_READ(TXCollCnt); 551 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 552 misses = EPE_READ(RXMissCnt); 553 if (misses > 0) 554 printf("%s: %d rx misses\n", sc->sc_dev.dv_xname, misses); 555 556 s = splnet(); 557 if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 558 epe_ifstart(ifp); 559 } 560 splx(s); 561 562 mii_tick(&sc->sc_mii); 563 callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc); 564 } 565 566 567 static int 568 epe_ifioctl(ifp, cmd, data) 569 struct ifnet *ifp; 570 u_long cmd; 571 void *data; 572 { 573 struct epe_softc *sc = ifp->if_softc; 574 struct ifreq *ifr = (struct ifreq *)data; 575 int s, error; 576 577 s = splnet(); 578 switch(cmd) { 579 case SIOCSIFMEDIA: 580 case SIOCGIFMEDIA: 581 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 582 break; 583 default: 584 error = ether_ioctl(ifp, cmd, data); 585 if (error == ENETRESET) { 586 if (ifp->if_flags & IFF_RUNNING) 587 epe_setaddr(ifp); 588 error = 0; 589 } 590 } 591 splx(s); 592 return error; 593 } 594 595 static void 596 epe_ifstart(ifp) 597 struct ifnet *ifp; 598 { 599 struct epe_softc *sc = (struct epe_softc *)ifp->if_softc; 600 struct mbuf *m; 601 bus_dma_segment_t *segs; 602 int s, bi, err, nsegs, ndq; 603 604 s = splnet(); 605 start: 606 ndq = 0; 607 if (sc->TXDQ_avail == 0) { 608 if (epe_gctx(sc) == 0) { 609 /* Enable End-Of-TX-Chain interrupt */ 610 EPE_WRITE(IntEn, IntEn_REOFIE|IntEn_ECIE); 611 ifp->if_flags |= IFF_OACTIVE; 612 ifp->if_timer = 10; 613 splx(s); 614 return; 615 } 616 } 617 618 bi = sc->TXDQ_cur - sc->TXDQ; 619 620 IFQ_POLL(&ifp->if_snd, m); 621 if (m == NULL) { 622 splx(s); 623 return; 624 } 625 more: 626 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 627 BUS_DMA_NOWAIT)) || 628 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 629 sc->txq[bi].m_dmamap->dm_nsegs > (sc->TXDQ_avail - ndq)) { 630 /* Copy entire mbuf chain to new and 32-bit aligned storage */ 631 struct mbuf *mn; 632 633 if (err == 0) 634 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 635 636 MGETHDR(mn, M_DONTWAIT, MT_DATA); 637 if (mn == NULL) goto stop; 638 if (m->m_pkthdr.len > (MHLEN & (~0x3))) { 639 MCLGET(mn, M_DONTWAIT); 640 if ((mn->m_flags & M_EXT) == 0) { 641 m_freem(mn); 642 goto stop; 643 } 644 } 645 mn->m_data = (void *)(((u_int32_t)mn->m_data + 0x3) & (~0x3)); 646 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 647 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 648 IFQ_DEQUEUE(&ifp->if_snd, m); 649 m_freem(m); 650 m = mn; 651 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 652 BUS_DMA_NOWAIT); 653 } else { 654 IFQ_DEQUEUE(&ifp->if_snd, m); 655 } 656 657 #if NBPFILTER > 0 658 if (ifp->if_bpf) 659 bpf_mtap(ifp->if_bpf, m); 660 #endif /* NBPFILTER > 0 */ 661 662 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 663 segs = sc->txq[bi].m_dmamap->dm_segs; 664 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 665 sc->txq[bi].m_dmamap->dm_mapsize, 666 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 667 668 /* XXX: This driver hasn't been tested w/nsegs > 1 */ 669 while (nsegs > 0) { 670 nsegs--; 671 sc->txq[bi].m = m; 672 sc->TXDQ[bi * 2] = segs->ds_addr; 673 if (nsegs == 0) 674 sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16) | 675 (1 << 31); 676 else 677 sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16); 678 segs++; 679 bi = (bi + 1) % TX_QLEN; 680 ndq++; 681 } 682 683 684 /* 685 * Enqueue another. Don't do more than half the available 686 * descriptors before telling the MAC about them 687 */ 688 if ((sc->TXDQ_avail - ndq) > 0 && ndq < TX_QLEN / 2) { 689 IFQ_POLL(&ifp->if_snd, m); 690 if (m != NULL) { 691 goto more; 692 } 693 } 694 stop: 695 if (ndq > 0) { 696 sc->TXDQ_avail -= ndq; 697 sc->TXDQ_cur = &sc->TXDQ[bi]; 698 CTRLPAGE_DMASYNC(0, TX_QLEN * 2 * sizeof(u_int32_t), 699 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 700 EPE_WRITE(TXDEnq, ndq); 701 } 702 703 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 704 goto start; 705 706 splx(s); 707 return; 708 } 709 710 static void 711 epe_ifwatchdog(ifp) 712 struct ifnet *ifp; 713 { 714 struct epe_softc *sc = (struct epe_softc *)ifp->if_softc; 715 716 if ((ifp->if_flags & IFF_RUNNING) == 0) 717 return; 718 printf("%s: device timeout, BMCtl = 0x%08x, BMSts = 0x%08x\n", 719 sc->sc_dev.dv_xname, EPE_READ(BMCtl), EPE_READ(BMSts)); 720 } 721 722 static int 723 epe_ifinit(ifp) 724 struct ifnet *ifp; 725 { 726 struct epe_softc *sc = ifp->if_softc; 727 int s = splnet(); 728 729 callout_stop(&sc->epe_tick_ch); 730 EPE_WRITE(RXCtl, RXCtl_IA0|RXCtl_BA|RXCtl_RCRCA|RXCtl_SRxON); 731 EPE_WRITE(TXCtl, TXCtl_STxON); 732 EPE_WRITE(GIIntMsk, GIIntMsk_INT); /* start interrupting */ 733 mii_mediachg(&sc->sc_mii); 734 callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc); 735 ifp->if_flags |= IFF_RUNNING; 736 splx(s); 737 return 0; 738 } 739 740 static void 741 epe_ifstop(ifp, disable) 742 struct ifnet *ifp; 743 int disable; 744 { 745 struct epe_softc *sc = ifp->if_softc; 746 747 748 EPE_WRITE(RXCtl, 0); 749 EPE_WRITE(TXCtl, 0); 750 EPE_WRITE(GIIntMsk, 0); 751 callout_stop(&sc->epe_tick_ch); 752 753 /* Down the MII. */ 754 mii_down(&sc->sc_mii); 755 756 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 757 ifp->if_timer = 0; 758 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 759 } 760 761 static void 762 epe_setaddr(ifp) 763 struct ifnet *ifp; 764 { 765 struct epe_softc *sc = ifp->if_softc; 766 struct ethercom *ac = &sc->sc_ec; 767 struct ether_multi *enm; 768 struct ether_multistep step; 769 u_int8_t ias[2][ETHER_ADDR_LEN]; 770 u_int32_t h, nma = 0, hashes[2] = { 0, 0 }; 771 u_int32_t rxctl = EPE_READ(RXCtl); 772 773 /* disable receiver temporarily */ 774 EPE_WRITE(RXCtl, rxctl & ~RXCtl_SRxON); 775 776 rxctl &= ~(RXCtl_MA|RXCtl_PA|RXCtl_IA2|RXCtl_IA3); 777 778 if (ifp->if_flags & IFF_PROMISC) { 779 rxctl |= RXCtl_PA; 780 } 781 782 ifp->if_flags &= ~IFF_ALLMULTI; 783 784 ETHER_FIRST_MULTI(step, ac, enm); 785 while (enm != NULL) { 786 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 787 /* 788 * We must listen to a range of multicast addresses. 789 * For now, just accept all multicasts, rather than 790 * trying to set only those filter bits needed to match 791 * the range. (At this time, the only use of address 792 * ranges is for IP multicast routing, for which the 793 * range is big enough to require all bits set.) 794 */ 795 rxctl &= ~(RXCtl_IA2|RXCtl_IA3); 796 rxctl |= RXCtl_MA; 797 hashes[0] = 0xffffffffUL; 798 hashes[1] = 0xffffffffUL; 799 ifp->if_flags |= IFF_ALLMULTI; 800 break; 801 } 802 803 if (nma < 2) { 804 /* We can program 2 perfect address filters for mcast */ 805 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 806 rxctl |= (1 << (nma + 2)); 807 } else { 808 /* 809 * XXX: Datasheet is not very clear here, I'm not sure 810 * if I'm doing this right. --joff 811 */ 812 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 813 814 /* Just want the 6 most-significant bits. */ 815 h = h >> 26; 816 817 hashes[ h / 32 ] |= (1 << (h % 32)); 818 rxctl |= RXCtl_MA; 819 } 820 ETHER_NEXT_MULTI(step, enm); 821 nma++; 822 } 823 824 EPE_WRITE(AFP, 0); 825 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 826 sc->sc_enaddr, ETHER_ADDR_LEN); 827 if (rxctl & RXCtl_IA2) { 828 EPE_WRITE(AFP, 2); 829 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 830 ias[0], ETHER_ADDR_LEN); 831 } 832 if (rxctl & RXCtl_IA3) { 833 EPE_WRITE(AFP, 3); 834 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 835 ias[1], ETHER_ADDR_LEN); 836 } 837 if (hashes[0] != 0 && hashes[1] != 0) { 838 EPE_WRITE(AFP, 7); 839 EPE_WRITE(HashTbl, hashes[0]); 840 EPE_WRITE(HashTbl + 4, hashes[1]); 841 } 842 EPE_WRITE(RXCtl, rxctl); 843 } 844
Indexes created Fri Oct 31 11:10:07 GMT 2025