epe.c revision 1.15
1 /* $NetBSD: epe.c,v 1.15 2008/01/19 22:10:14 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Jesse Off 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: epe.c,v 1.15 2008/01/19 22:10:14 dyoung Exp $"); 38 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/ioctl.h> 43 #include <sys/kernel.h> 44 #include <sys/proc.h> 45 #include <sys/malloc.h> 46 #include <sys/time.h> 47 #include <sys/device.h> 48 #include <uvm/uvm_extern.h> 49 50 #include <machine/bus.h> 51 #include <machine/intr.h> 52 53 #include <arm/cpufunc.h> 54 55 #include <arm/ep93xx/epsocvar.h> 56 #include <arm/ep93xx/ep93xxvar.h> 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_types.h> 61 #include <net/if_media.h> 62 #include <net/if_ether.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #ifdef INET 68 #include <netinet/in.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/in_var.h> 71 #include <netinet/ip.h> 72 #include <netinet/if_inarp.h> 73 #endif 74 75 #ifdef NS 76 #include <netns/ns.h> 77 #include <netns/ns_if.h> 78 #endif 79 80 #include "bpfilter.h" 81 #if NBPFILTER > 0 82 #include <net/bpf.h> 83 #include <net/bpfdesc.h> 84 #endif 85 86 #include <arm/ep93xx/ep93xxreg.h> 87 #include <arm/ep93xx/epereg.h> 88 #include <arm/ep93xx/epevar.h> 89 90 #define DEFAULT_MDCDIV 32 91 92 #ifndef EPE_FAST 93 #define EPE_FAST 94 #endif 95 96 #ifndef EPE_FAST 97 #define EPE_READ(x) \ 98 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x)) 99 #define EPE_WRITE(x, y) \ 100 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x), (y)) 101 #define CTRLPAGE_DMASYNC(x, y, z) \ 102 bus_dmamap_sync(sc->sc_dmat, sc->ctrlpage_dmamap, (x), (y), (z)) 103 #else 104 #define EPE_READ(x) *(volatile u_int32_t *) \ 105 (EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x)) 106 #define EPE_WRITE(x, y) *(volatile u_int32_t *) \ 107 (EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x)) = y 108 #define CTRLPAGE_DMASYNC(x, y, z) 109 #endif /* ! EPE_FAST */ 110 111 static int epe_match(struct device *, struct cfdata *, void *); 112 static void epe_attach(struct device *, struct device *, void *); 113 static void epe_init(struct epe_softc *); 114 static int epe_intr(void* arg); 115 static int epe_gctx(struct epe_softc *); 116 static int epe_mediachange(struct ifnet *); 117 int epe_mii_readreg (struct device *, int, int); 118 void epe_mii_writereg (struct device *, int, int, int); 119 void epe_statchg (struct device *); 120 void epe_tick (void *); 121 static int epe_ifioctl (struct ifnet *, u_long, void *); 122 static void epe_ifstart (struct ifnet *); 123 static void epe_ifwatchdog (struct ifnet *); 124 static int epe_ifinit (struct ifnet *); 125 static void epe_ifstop (struct ifnet *, int); 126 static void epe_setaddr (struct ifnet *); 127 128 CFATTACH_DECL(epe, sizeof(struct epe_softc), 129 epe_match, epe_attach, NULL, NULL); 130 131 static int 132 epe_match(struct device *parent, struct cfdata *match, void *aux) 133 { 134 return 2; 135 } 136 137 static void 138 epe_attach(struct device *parent, struct device *self, void *aux) 139 { 140 struct epe_softc *sc; 141 struct epsoc_attach_args *sa; 142 prop_data_t enaddr; 143 144 printf("\n"); 145 sc = (struct epe_softc*) self; 146 sa = aux; 147 sc->sc_iot = sa->sa_iot; 148 sc->sc_intr = sa->sa_intr; 149 sc->sc_dmat = sa->sa_dmat; 150 151 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 152 0, &sc->sc_ioh)) 153 panic("%s: Cannot map registers", self->dv_xname); 154 155 /* Fetch the Ethernet address from property if set. */ 156 enaddr = prop_dictionary_get(device_properties(self), "mac-addr"); 157 if (enaddr != NULL) { 158 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 159 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 160 memcpy(sc->sc_enaddr, prop_data_data_nocopy(enaddr), 161 ETHER_ADDR_LEN); 162 bus_space_write_4(sc->sc_iot, sc->sc_ioh, EPE_AFP, 0); 163 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 164 sc->sc_enaddr, ETHER_ADDR_LEN); 165 } 166 167 ep93xx_intr_establish(sc->sc_intr, IPL_NET, epe_intr, sc); 168 epe_init(sc); 169 } 170 171 static int 172 epe_gctx(struct epe_softc *sc) 173 { 174 struct ifnet * ifp = &sc->sc_ec.ec_if; 175 u_int32_t *cur, ndq = 0; 176 177 /* Handle transmit completions */ 178 cur = (u_int32_t *)(EPE_READ(TXStsQCurAdd) - 179 sc->ctrlpage_dsaddr + (char*)sc->ctrlpage); 180 181 if (sc->TXStsQ_cur != cur) { 182 CTRLPAGE_DMASYNC(TX_QLEN * 2 * sizeof(u_int32_t), 183 TX_QLEN * sizeof(u_int32_t), BUS_DMASYNC_PREREAD); 184 } else { 185 return 0; 186 } 187 188 do { 189 u_int32_t tbi = *sc->TXStsQ_cur & 0x7fff; 190 struct mbuf *m = sc->txq[tbi].m; 191 192 if ((*sc->TXStsQ_cur & TXStsQ_TxWE) == 0) { 193 ifp->if_oerrors++; 194 } 195 bus_dmamap_unload(sc->sc_dmat, sc->txq[tbi].m_dmamap); 196 m_freem(m); 197 do { 198 sc->txq[tbi].m = NULL; 199 ndq++; 200 tbi = (tbi + 1) % TX_QLEN; 201 } while (sc->txq[tbi].m == m); 202 203 ifp->if_opackets++; 204 sc->TXStsQ_cur++; 205 if (sc->TXStsQ_cur >= sc->TXStsQ + TX_QLEN) { 206 sc->TXStsQ_cur = sc->TXStsQ; 207 } 208 } while (sc->TXStsQ_cur != cur); 209 210 sc->TXDQ_avail += ndq; 211 if (ifp->if_flags & IFF_OACTIVE) { 212 ifp->if_flags &= ~IFF_OACTIVE; 213 /* Disable end-of-tx-chain interrupt */ 214 EPE_WRITE(IntEn, IntEn_REOFIE); 215 } 216 return ndq; 217 } 218 219 static int 220 epe_intr(void *arg) 221 { 222 struct epe_softc *sc = (struct epe_softc *)arg; 223 struct ifnet * ifp = &sc->sc_ec.ec_if; 224 u_int32_t ndq = 0, irq, *cur; 225 226 irq = EPE_READ(IntStsC); 227 begin: 228 cur = (u_int32_t *)(EPE_READ(RXStsQCurAdd) - 229 sc->ctrlpage_dsaddr + (char*)sc->ctrlpage); 230 CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(u_int32_t), 231 RX_QLEN * 4 * sizeof(u_int32_t), 232 BUS_DMASYNC_PREREAD); 233 while (sc->RXStsQ_cur != cur) { 234 if ((sc->RXStsQ_cur[0] & (RXStsQ_RWE|RXStsQ_RFP|RXStsQ_EOB)) == 235 (RXStsQ_RWE|RXStsQ_RFP|RXStsQ_EOB)) { 236 u_int32_t bi = (sc->RXStsQ_cur[1] >> 16) & 0x7fff; 237 u_int32_t fl = sc->RXStsQ_cur[1] & 0xffff; 238 struct mbuf *m; 239 240 MGETHDR(m, M_DONTWAIT, MT_DATA); 241 if (m != NULL) MCLGET(m, M_DONTWAIT); 242 if (m != NULL && (m->m_flags & M_EXT)) { 243 bus_dmamap_unload(sc->sc_dmat, 244 sc->rxq[bi].m_dmamap); 245 sc->rxq[bi].m->m_pkthdr.rcvif = ifp; 246 sc->rxq[bi].m->m_pkthdr.len = 247 sc->rxq[bi].m->m_len = fl; 248 #if NBPFILTER > 0 249 if (ifp->if_bpf) 250 bpf_mtap(ifp->if_bpf, sc->rxq[bi].m); 251 #endif /* NBPFILTER > 0 */ 252 (*ifp->if_input)(ifp, sc->rxq[bi].m); 253 sc->rxq[bi].m = m; 254 bus_dmamap_load(sc->sc_dmat, 255 sc->rxq[bi].m_dmamap, 256 m->m_ext.ext_buf, MCLBYTES, 257 NULL, BUS_DMA_NOWAIT); 258 sc->RXDQ[bi * 2] = 259 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr; 260 } else { 261 /* Drop packets until we can get replacement 262 * empty mbufs for the RXDQ. 263 */ 264 if (m != NULL) { 265 m_freem(m); 266 } 267 ifp->if_ierrors++; 268 } 269 } else { 270 ifp->if_ierrors++; 271 } 272 273 ndq++; 274 275 sc->RXStsQ_cur += 2; 276 if (sc->RXStsQ_cur >= sc->RXStsQ + (RX_QLEN * 2)) { 277 sc->RXStsQ_cur = sc->RXStsQ; 278 } 279 } 280 281 if (ndq > 0) { 282 ifp->if_ipackets += ndq; 283 CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(u_int32_t), 284 RX_QLEN * 4 * sizeof(u_int32_t), 285 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 286 EPE_WRITE(RXStsEnq, ndq); 287 EPE_WRITE(RXDEnq, ndq); 288 ndq = 0; 289 } 290 291 if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 292 epe_ifstart(ifp); 293 } 294 295 irq = EPE_READ(IntStsC); 296 if ((irq & (IntSts_RxSQ|IntSts_ECI)) != 0) 297 goto begin; 298 299 return (1); 300 } 301 302 303 static void 304 epe_init(struct epe_softc *sc) 305 { 306 bus_dma_segment_t segs; 307 char *addr; 308 int rsegs, err, i; 309 struct ifnet * ifp = &sc->sc_ec.ec_if; 310 int mdcdiv = DEFAULT_MDCDIV; 311 312 callout_init(&sc->epe_tick_ch, 0); 313 314 /* Select primary Individual Address in Address Filter Pointer */ 315 EPE_WRITE(AFP, 0); 316 /* Read ethernet MAC, should already be set by bootrom */ 317 bus_space_read_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 318 sc->sc_enaddr, ETHER_ADDR_LEN); 319 printf("%s: MAC address %s\n", sc->sc_dev.dv_xname, 320 ether_sprintf(sc->sc_enaddr)); 321 322 /* Soft Reset the MAC */ 323 EPE_WRITE(SelfCtl, SelfCtl_RESET); 324 while(EPE_READ(SelfCtl) & SelfCtl_RESET); 325 326 /* suggested magic initialization values from datasheet */ 327 EPE_WRITE(RXBufThrshld, 0x800040); 328 EPE_WRITE(TXBufThrshld, 0x200010); 329 EPE_WRITE(RXStsThrshld, 0x40002); 330 EPE_WRITE(TXStsThrshld, 0x40002); 331 EPE_WRITE(RXDThrshld, 0x40002); 332 EPE_WRITE(TXDThrshld, 0x40002); 333 334 /* Allocate a page of memory for descriptor and status queues */ 335 err = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, 0, PAGE_SIZE, 336 &segs, 1, &rsegs, BUS_DMA_WAITOK); 337 if (err == 0) { 338 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, PAGE_SIZE, 339 &sc->ctrlpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT)); 340 } 341 if (err == 0) { 342 err = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 343 0, BUS_DMA_WAITOK, &sc->ctrlpage_dmamap); 344 } 345 if (err == 0) { 346 err = bus_dmamap_load(sc->sc_dmat, sc->ctrlpage_dmamap, 347 sc->ctrlpage, PAGE_SIZE, NULL, BUS_DMA_WAITOK); 348 } 349 if (err != 0) { 350 panic("%s: Cannot get DMA memory", sc->sc_dev.dv_xname); 351 } 352 sc->ctrlpage_dsaddr = sc->ctrlpage_dmamap->dm_segs[0].ds_addr; 353 bzero(sc->ctrlpage, PAGE_SIZE); 354 355 /* Set up pointers to start of each queue in kernel addr space. 356 * Each descriptor queue or status queue entry uses 2 words 357 */ 358 sc->TXDQ = (u_int32_t *)sc->ctrlpage; 359 sc->TXDQ_cur = sc->TXDQ; 360 sc->TXDQ_avail = TX_QLEN - 1; 361 sc->TXStsQ = &sc->TXDQ[TX_QLEN * 2]; 362 sc->TXStsQ_cur = sc->TXStsQ; 363 sc->RXDQ = &sc->TXStsQ[TX_QLEN]; 364 sc->RXStsQ = &sc->RXDQ[RX_QLEN * 2]; 365 sc->RXStsQ_cur = sc->RXStsQ; 366 367 /* Program each queue's start addr, cur addr, and len registers 368 * with the physical addresses. 369 */ 370 addr = (char *)sc->ctrlpage_dmamap->dm_segs[0].ds_addr; 371 EPE_WRITE(TXDQBAdd, (u_int32_t)addr); 372 EPE_WRITE(TXDQCurAdd, (u_int32_t)addr); 373 EPE_WRITE(TXDQBLen, TX_QLEN * 2 * sizeof(u_int32_t)); 374 375 addr += (sc->TXStsQ - sc->TXDQ) * sizeof(u_int32_t); 376 EPE_WRITE(TXStsQBAdd, (u_int32_t)addr); 377 EPE_WRITE(TXStsQCurAdd, (u_int32_t)addr); 378 EPE_WRITE(TXStsQBLen, TX_QLEN * sizeof(u_int32_t)); 379 380 addr += (sc->RXDQ - sc->TXStsQ) * sizeof(u_int32_t); 381 EPE_WRITE(RXDQBAdd, (u_int32_t)addr); 382 EPE_WRITE(RXDCurAdd, (u_int32_t)addr); 383 EPE_WRITE(RXDQBLen, RX_QLEN * 2 * sizeof(u_int32_t)); 384 385 addr += (sc->RXStsQ - sc->RXDQ) * sizeof(u_int32_t); 386 EPE_WRITE(RXStsQBAdd, (u_int32_t)addr); 387 EPE_WRITE(RXStsQCurAdd, (u_int32_t)addr); 388 EPE_WRITE(RXStsQBLen, RX_QLEN * 2 * sizeof(u_int32_t)); 389 390 /* Populate the RXDQ with mbufs */ 391 for(i = 0; i < RX_QLEN; i++) { 392 struct mbuf *m; 393 394 bus_dmamap_create(sc->sc_dmat, MCLBYTES, TX_QLEN/4, MCLBYTES, 0, 395 BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 396 MGETHDR(m, M_WAIT, MT_DATA); 397 MCLGET(m, M_WAIT); 398 sc->rxq[i].m = m; 399 bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 400 m->m_ext.ext_buf, MCLBYTES, NULL, 401 BUS_DMA_WAITOK); 402 403 sc->RXDQ[i * 2] = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr; 404 sc->RXDQ[i * 2 + 1] = (i << 16) | MCLBYTES; 405 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 406 MCLBYTES, BUS_DMASYNC_PREREAD); 407 } 408 409 for(i = 0; i < TX_QLEN; i++) { 410 bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 411 (BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW), 412 &sc->txq[i].m_dmamap); 413 sc->txq[i].m = NULL; 414 sc->TXDQ[i * 2 + 1] = (i << 16); 415 } 416 417 /* Divide HCLK by 32 for MDC clock */ 418 if (device_cfdata(&sc->sc_dev)->cf_flags) 419 mdcdiv = device_cfdata(&sc->sc_dev)->cf_flags; 420 EPE_WRITE(SelfCtl, (SelfCtl_MDCDIV(mdcdiv)|SelfCtl_PSPRS)); 421 422 sc->sc_mii.mii_ifp = ifp; 423 sc->sc_mii.mii_readreg = epe_mii_readreg; 424 sc->sc_mii.mii_writereg = epe_mii_writereg; 425 sc->sc_mii.mii_statchg = epe_statchg; 426 sc->sc_ec.ec_mii = &sc->sc_mii; 427 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, epe_mediachange, 428 ether_mediastatus); 429 mii_attach((struct device *)sc, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 430 MII_OFFSET_ANY, 0); 431 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 432 433 EPE_WRITE(BMCtl, BMCtl_RxEn|BMCtl_TxEn); 434 EPE_WRITE(IntEn, IntEn_REOFIE); 435 /* maximum valid max frame length */ 436 EPE_WRITE(MaxFrmLen, (0x7ff << 16)|MHLEN); 437 /* wait for receiver ready */ 438 while((EPE_READ(BMSts) & BMSts_RxAct) == 0); 439 /* enqueue the entries in RXStsQ and RXDQ */ 440 CTRLPAGE_DMASYNC(0, sc->ctrlpage_dmamap->dm_mapsize, 441 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 442 EPE_WRITE(RXDEnq, RX_QLEN - 1); 443 EPE_WRITE(RXStsEnq, RX_QLEN - 1); 444 445 /* 446 * We can support 802.1Q VLAN-sized frames. 447 */ 448 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 449 450 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 451 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 452 ifp->if_ioctl = epe_ifioctl; 453 ifp->if_start = epe_ifstart; 454 ifp->if_watchdog = epe_ifwatchdog; 455 ifp->if_init = epe_ifinit; 456 ifp->if_stop = epe_ifstop; 457 ifp->if_timer = 0; 458 ifp->if_softc = sc; 459 IFQ_SET_READY(&ifp->if_snd); 460 if_attach(ifp); 461 ether_ifattach(ifp, (sc)->sc_enaddr); 462 } 463 464 static int 465 epe_mediachange(ifp) 466 struct ifnet *ifp; 467 { 468 if (ifp->if_flags & IFF_UP) 469 epe_ifinit(ifp); 470 return (0); 471 } 472 473 int 474 epe_mii_readreg(self, phy, reg) 475 struct device *self; 476 int phy, reg; 477 { 478 u_int32_t d, v; 479 struct epe_softc *sc; 480 481 sc = (struct epe_softc *)self; 482 d = EPE_READ(SelfCtl); 483 EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */ 484 EPE_WRITE(MIICmd, (MIICmd_READ | (phy << 5) | reg)); 485 while(EPE_READ(MIISts) & MIISts_BUSY); 486 v = EPE_READ(MIIData); 487 EPE_WRITE(SelfCtl, d); /* restore old value */ 488 return v; 489 } 490 491 void 492 epe_mii_writereg(self, phy, reg, val) 493 struct device *self; 494 int phy, reg, val; 495 { 496 struct epe_softc *sc; 497 u_int32_t d; 498 499 sc = (struct epe_softc *)self; 500 d = EPE_READ(SelfCtl); 501 EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */ 502 EPE_WRITE(MIIData, val); 503 EPE_WRITE(MIICmd, (MIICmd_WRITE | (phy << 5) | reg)); 504 while(EPE_READ(MIISts) & MIISts_BUSY); 505 EPE_WRITE(SelfCtl, d); /* restore old value */ 506 } 507 508 509 void 510 epe_statchg(self) 511 struct device *self; 512 { 513 struct epe_softc *sc = (struct epe_softc *)self; 514 u_int32_t reg; 515 516 /* 517 * We must keep the MAC and the PHY in sync as 518 * to the status of full-duplex! 519 */ 520 reg = EPE_READ(TestCtl); 521 if (sc->sc_mii.mii_media_active & IFM_FDX) 522 reg |= TestCtl_MFDX; 523 else 524 reg &= ~TestCtl_MFDX; 525 EPE_WRITE(TestCtl, reg); 526 } 527 528 void 529 epe_tick(arg) 530 void *arg; 531 { 532 struct epe_softc* sc = (struct epe_softc *)arg; 533 struct ifnet * ifp = &sc->sc_ec.ec_if; 534 int s; 535 u_int32_t misses; 536 537 ifp->if_collisions += EPE_READ(TXCollCnt); 538 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 539 misses = EPE_READ(RXMissCnt); 540 if (misses > 0) 541 printf("%s: %d rx misses\n", sc->sc_dev.dv_xname, misses); 542 543 s = splnet(); 544 if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 545 epe_ifstart(ifp); 546 } 547 splx(s); 548 549 mii_tick(&sc->sc_mii); 550 callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc); 551 } 552 553 554 static int 555 epe_ifioctl(ifp, cmd, data) 556 struct ifnet *ifp; 557 u_long cmd; 558 void *data; 559 { 560 struct epe_softc *sc = ifp->if_softc; 561 struct ifreq *ifr = (struct ifreq *)data; 562 int s, error; 563 564 s = splnet(); 565 error = ether_ioctl(ifp, cmd, data); 566 if (error == ENETRESET) { 567 if (ifp->if_flags & IFF_RUNNING) 568 epe_setaddr(ifp); 569 error = 0; 570 } 571 splx(s); 572 return error; 573 } 574 575 static void 576 epe_ifstart(ifp) 577 struct ifnet *ifp; 578 { 579 struct epe_softc *sc = (struct epe_softc *)ifp->if_softc; 580 struct mbuf *m; 581 bus_dma_segment_t *segs; 582 int s, bi, err, nsegs, ndq; 583 584 s = splnet(); 585 start: 586 ndq = 0; 587 if (sc->TXDQ_avail == 0) { 588 if (epe_gctx(sc) == 0) { 589 /* Enable End-Of-TX-Chain interrupt */ 590 EPE_WRITE(IntEn, IntEn_REOFIE|IntEn_ECIE); 591 ifp->if_flags |= IFF_OACTIVE; 592 ifp->if_timer = 10; 593 splx(s); 594 return; 595 } 596 } 597 598 bi = sc->TXDQ_cur - sc->TXDQ; 599 600 IFQ_POLL(&ifp->if_snd, m); 601 if (m == NULL) { 602 splx(s); 603 return; 604 } 605 more: 606 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 607 BUS_DMA_NOWAIT)) || 608 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 609 sc->txq[bi].m_dmamap->dm_nsegs > (sc->TXDQ_avail - ndq)) { 610 /* Copy entire mbuf chain to new and 32-bit aligned storage */ 611 struct mbuf *mn; 612 613 if (err == 0) 614 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 615 616 MGETHDR(mn, M_DONTWAIT, MT_DATA); 617 if (mn == NULL) goto stop; 618 if (m->m_pkthdr.len > (MHLEN & (~0x3))) { 619 MCLGET(mn, M_DONTWAIT); 620 if ((mn->m_flags & M_EXT) == 0) { 621 m_freem(mn); 622 goto stop; 623 } 624 } 625 mn->m_data = (void *)(((u_int32_t)mn->m_data + 0x3) & (~0x3)); 626 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 627 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 628 IFQ_DEQUEUE(&ifp->if_snd, m); 629 m_freem(m); 630 m = mn; 631 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 632 BUS_DMA_NOWAIT); 633 } else { 634 IFQ_DEQUEUE(&ifp->if_snd, m); 635 } 636 637 #if NBPFILTER > 0 638 if (ifp->if_bpf) 639 bpf_mtap(ifp->if_bpf, m); 640 #endif /* NBPFILTER > 0 */ 641 642 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 643 segs = sc->txq[bi].m_dmamap->dm_segs; 644 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 645 sc->txq[bi].m_dmamap->dm_mapsize, 646 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 647 648 /* XXX: This driver hasn't been tested w/nsegs > 1 */ 649 while (nsegs > 0) { 650 nsegs--; 651 sc->txq[bi].m = m; 652 sc->TXDQ[bi * 2] = segs->ds_addr; 653 if (nsegs == 0) 654 sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16) | 655 (1 << 31); 656 else 657 sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16); 658 segs++; 659 bi = (bi + 1) % TX_QLEN; 660 ndq++; 661 } 662 663 664 /* 665 * Enqueue another. Don't do more than half the available 666 * descriptors before telling the MAC about them 667 */ 668 if ((sc->TXDQ_avail - ndq) > 0 && ndq < TX_QLEN / 2) { 669 IFQ_POLL(&ifp->if_snd, m); 670 if (m != NULL) { 671 goto more; 672 } 673 } 674 stop: 675 if (ndq > 0) { 676 sc->TXDQ_avail -= ndq; 677 sc->TXDQ_cur = &sc->TXDQ[bi]; 678 CTRLPAGE_DMASYNC(0, TX_QLEN * 2 * sizeof(u_int32_t), 679 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 680 EPE_WRITE(TXDEnq, ndq); 681 } 682 683 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 684 goto start; 685 686 splx(s); 687 return; 688 } 689 690 static void 691 epe_ifwatchdog(ifp) 692 struct ifnet *ifp; 693 { 694 struct epe_softc *sc = (struct epe_softc *)ifp->if_softc; 695 696 if ((ifp->if_flags & IFF_RUNNING) == 0) 697 return; 698 printf("%s: device timeout, BMCtl = 0x%08x, BMSts = 0x%08x\n", 699 sc->sc_dev.dv_xname, EPE_READ(BMCtl), EPE_READ(BMSts)); 700 } 701 702 static int 703 epe_ifinit(ifp) 704 struct ifnet *ifp; 705 { 706 struct epe_softc *sc = ifp->if_softc; 707 int rc, s = splnet(); 708 709 callout_stop(&sc->epe_tick_ch); 710 EPE_WRITE(RXCtl, RXCtl_IA0|RXCtl_BA|RXCtl_RCRCA|RXCtl_SRxON); 711 EPE_WRITE(TXCtl, TXCtl_STxON); 712 EPE_WRITE(GIIntMsk, GIIntMsk_INT); /* start interrupting */ 713 714 if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 715 rc = 0; 716 else if (rc != 0) 717 goto out; 718 719 callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc); 720 ifp->if_flags |= IFF_RUNNING; 721 out: 722 splx(s); 723 return 0; 724 } 725 726 static void 727 epe_ifstop(ifp, disable) 728 struct ifnet *ifp; 729 int disable; 730 { 731 struct epe_softc *sc = ifp->if_softc; 732 733 734 EPE_WRITE(RXCtl, 0); 735 EPE_WRITE(TXCtl, 0); 736 EPE_WRITE(GIIntMsk, 0); 737 callout_stop(&sc->epe_tick_ch); 738 739 /* Down the MII. */ 740 mii_down(&sc->sc_mii); 741 742 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 743 ifp->if_timer = 0; 744 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 745 } 746 747 static void 748 epe_setaddr(ifp) 749 struct ifnet *ifp; 750 { 751 struct epe_softc *sc = ifp->if_softc; 752 struct ethercom *ac = &sc->sc_ec; 753 struct ether_multi *enm; 754 struct ether_multistep step; 755 u_int8_t ias[2][ETHER_ADDR_LEN]; 756 u_int32_t h, nma = 0, hashes[2] = { 0, 0 }; 757 u_int32_t rxctl = EPE_READ(RXCtl); 758 759 /* disable receiver temporarily */ 760 EPE_WRITE(RXCtl, rxctl & ~RXCtl_SRxON); 761 762 rxctl &= ~(RXCtl_MA|RXCtl_PA|RXCtl_IA2|RXCtl_IA3); 763 764 if (ifp->if_flags & IFF_PROMISC) { 765 rxctl |= RXCtl_PA; 766 } 767 768 ifp->if_flags &= ~IFF_ALLMULTI; 769 770 ETHER_FIRST_MULTI(step, ac, enm); 771 while (enm != NULL) { 772 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 773 /* 774 * We must listen to a range of multicast addresses. 775 * For now, just accept all multicasts, rather than 776 * trying to set only those filter bits needed to match 777 * the range. (At this time, the only use of address 778 * ranges is for IP multicast routing, for which the 779 * range is big enough to require all bits set.) 780 */ 781 rxctl &= ~(RXCtl_IA2|RXCtl_IA3); 782 rxctl |= RXCtl_MA; 783 hashes[0] = 0xffffffffUL; 784 hashes[1] = 0xffffffffUL; 785 ifp->if_flags |= IFF_ALLMULTI; 786 break; 787 } 788 789 if (nma < 2) { 790 /* We can program 2 perfect address filters for mcast */ 791 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 792 rxctl |= (1 << (nma + 2)); 793 } else { 794 /* 795 * XXX: Datasheet is not very clear here, I'm not sure 796 * if I'm doing this right. --joff 797 */ 798 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 799 800 /* Just want the 6 most-significant bits. */ 801 h = h >> 26; 802 803 hashes[ h / 32 ] |= (1 << (h % 32)); 804 rxctl |= RXCtl_MA; 805 } 806 ETHER_NEXT_MULTI(step, enm); 807 nma++; 808 } 809 810 EPE_WRITE(AFP, 0); 811 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 812 sc->sc_enaddr, ETHER_ADDR_LEN); 813 if (rxctl & RXCtl_IA2) { 814 EPE_WRITE(AFP, 2); 815 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 816 ias[0], ETHER_ADDR_LEN); 817 } 818 if (rxctl & RXCtl_IA3) { 819 EPE_WRITE(AFP, 3); 820 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 821 ias[1], ETHER_ADDR_LEN); 822 } 823 if (hashes[0] != 0 && hashes[1] != 0) { 824 EPE_WRITE(AFP, 7); 825 EPE_WRITE(HashTbl, hashes[0]); 826 EPE_WRITE(HashTbl + 4, hashes[1]); 827 } 828 EPE_WRITE(RXCtl, rxctl); 829 } 830
Indexes created Tue Sep 30 20:09:53 GMT 2025