epe.c revision 1.21
1 /* $NetBSD: epe.c,v 1.21 2009/03/18 16:00:09 cegger Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Jesse Off 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: epe.c,v 1.21 2009/03/18 16:00:09 cegger Exp $"); 38 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/ioctl.h> 43 #include <sys/kernel.h> 44 #include <sys/proc.h> 45 #include <sys/malloc.h> 46 #include <sys/time.h> 47 #include <sys/device.h> 48 #include <uvm/uvm_extern.h> 49 50 #include <machine/bus.h> 51 #include <machine/intr.h> 52 53 #include <arm/cpufunc.h> 54 55 #include <arm/ep93xx/epsocvar.h> 56 #include <arm/ep93xx/ep93xxvar.h> 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_types.h> 61 #include <net/if_media.h> 62 #include <net/if_ether.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #ifdef INET 68 #include <netinet/in.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/in_var.h> 71 #include <netinet/ip.h> 72 #include <netinet/if_inarp.h> 73 #endif 74 75 #ifdef NS 76 #include <netns/ns.h> 77 #include <netns/ns_if.h> 78 #endif 79 80 #include "bpfilter.h" 81 #if NBPFILTER > 0 82 #include <net/bpf.h> 83 #include <net/bpfdesc.h> 84 #endif 85 86 #include <arm/ep93xx/ep93xxreg.h> 87 #include <arm/ep93xx/epereg.h> 88 #include <arm/ep93xx/epevar.h> 89 90 #define DEFAULT_MDCDIV 32 91 92 #ifndef EPE_FAST 93 #define EPE_FAST 94 #endif 95 96 #ifndef EPE_FAST 97 #define EPE_READ(x) \ 98 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x)) 99 #define EPE_WRITE(x, y) \ 100 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x), (y)) 101 #define CTRLPAGE_DMASYNC(x, y, z) \ 102 bus_dmamap_sync(sc->sc_dmat, sc->ctrlpage_dmamap, (x), (y), (z)) 103 #else 104 #define EPE_READ(x) *(volatile u_int32_t *) \ 105 (EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x)) 106 #define EPE_WRITE(x, y) *(volatile u_int32_t *) \ 107 (EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x)) = y 108 #define CTRLPAGE_DMASYNC(x, y, z) 109 #endif /* ! EPE_FAST */ 110 111 static int epe_match(struct device *, struct cfdata *, void *); 112 static void epe_attach(struct device *, struct device *, void *); 113 static void epe_init(struct epe_softc *); 114 static int epe_intr(void* arg); 115 static int epe_gctx(struct epe_softc *); 116 static int epe_mediachange(struct ifnet *); 117 int epe_mii_readreg (struct device *, int, int); 118 void epe_mii_writereg (struct device *, int, int, int); 119 void epe_statchg (struct device *); 120 void epe_tick (void *); 121 static int epe_ifioctl (struct ifnet *, u_long, void *); 122 static void epe_ifstart (struct ifnet *); 123 static void epe_ifwatchdog (struct ifnet *); 124 static int epe_ifinit (struct ifnet *); 125 static void epe_ifstop (struct ifnet *, int); 126 static void epe_setaddr (struct ifnet *); 127 128 CFATTACH_DECL(epe, sizeof(struct epe_softc), 129 epe_match, epe_attach, NULL, NULL); 130 131 static int 132 epe_match(struct device *parent, struct cfdata *match, void *aux) 133 { 134 return 2; 135 } 136 137 static void 138 epe_attach(struct device *parent, struct device *self, void *aux) 139 { 140 struct epe_softc *sc; 141 struct epsoc_attach_args *sa; 142 prop_data_t enaddr; 143 144 printf("\n"); 145 sc = (struct epe_softc*) self; 146 sa = aux; 147 sc->sc_iot = sa->sa_iot; 148 sc->sc_intr = sa->sa_intr; 149 sc->sc_dmat = sa->sa_dmat; 150 151 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 152 0, &sc->sc_ioh)) 153 panic("%s: Cannot map registers", self->dv_xname); 154 155 /* Fetch the Ethernet address from property if set. */ 156 enaddr = prop_dictionary_get(device_properties(self), "mac-addr"); 157 if (enaddr != NULL) { 158 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 159 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 160 memcpy(sc->sc_enaddr, prop_data_data_nocopy(enaddr), 161 ETHER_ADDR_LEN); 162 bus_space_write_4(sc->sc_iot, sc->sc_ioh, EPE_AFP, 0); 163 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 164 sc->sc_enaddr, ETHER_ADDR_LEN); 165 } 166 167 ep93xx_intr_establish(sc->sc_intr, IPL_NET, epe_intr, sc); 168 epe_init(sc); 169 } 170 171 static int 172 epe_gctx(struct epe_softc *sc) 173 { 174 struct ifnet * ifp = &sc->sc_ec.ec_if; 175 u_int32_t *cur, ndq = 0; 176 177 /* Handle transmit completions */ 178 cur = (u_int32_t *)(EPE_READ(TXStsQCurAdd) - 179 sc->ctrlpage_dsaddr + (char*)sc->ctrlpage); 180 181 if (sc->TXStsQ_cur != cur) { 182 CTRLPAGE_DMASYNC(TX_QLEN * 2 * sizeof(u_int32_t), 183 TX_QLEN * sizeof(u_int32_t), BUS_DMASYNC_PREREAD); 184 } else { 185 return 0; 186 } 187 188 do { 189 u_int32_t tbi = *sc->TXStsQ_cur & 0x7fff; 190 struct mbuf *m = sc->txq[tbi].m; 191 192 if ((*sc->TXStsQ_cur & TXStsQ_TxWE) == 0) { 193 ifp->if_oerrors++; 194 } 195 bus_dmamap_unload(sc->sc_dmat, sc->txq[tbi].m_dmamap); 196 m_freem(m); 197 do { 198 sc->txq[tbi].m = NULL; 199 ndq++; 200 tbi = (tbi + 1) % TX_QLEN; 201 } while (sc->txq[tbi].m == m); 202 203 ifp->if_opackets++; 204 sc->TXStsQ_cur++; 205 if (sc->TXStsQ_cur >= sc->TXStsQ + TX_QLEN) { 206 sc->TXStsQ_cur = sc->TXStsQ; 207 } 208 } while (sc->TXStsQ_cur != cur); 209 210 sc->TXDQ_avail += ndq; 211 if (ifp->if_flags & IFF_OACTIVE) { 212 ifp->if_flags &= ~IFF_OACTIVE; 213 /* Disable end-of-tx-chain interrupt */ 214 EPE_WRITE(IntEn, IntEn_REOFIE); 215 } 216 return ndq; 217 } 218 219 static int 220 epe_intr(void *arg) 221 { 222 struct epe_softc *sc = (struct epe_softc *)arg; 223 struct ifnet * ifp = &sc->sc_ec.ec_if; 224 u_int32_t ndq = 0, irq, *cur; 225 226 irq = EPE_READ(IntStsC); 227 begin: 228 cur = (u_int32_t *)(EPE_READ(RXStsQCurAdd) - 229 sc->ctrlpage_dsaddr + (char*)sc->ctrlpage); 230 CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(u_int32_t), 231 RX_QLEN * 4 * sizeof(u_int32_t), 232 BUS_DMASYNC_PREREAD); 233 while (sc->RXStsQ_cur != cur) { 234 if ((sc->RXStsQ_cur[0] & (RXStsQ_RWE|RXStsQ_RFP|RXStsQ_EOB)) == 235 (RXStsQ_RWE|RXStsQ_RFP|RXStsQ_EOB)) { 236 u_int32_t bi = (sc->RXStsQ_cur[1] >> 16) & 0x7fff; 237 u_int32_t fl = sc->RXStsQ_cur[1] & 0xffff; 238 struct mbuf *m; 239 240 MGETHDR(m, M_DONTWAIT, MT_DATA); 241 if (m != NULL) MCLGET(m, M_DONTWAIT); 242 if (m != NULL && (m->m_flags & M_EXT)) { 243 bus_dmamap_unload(sc->sc_dmat, 244 sc->rxq[bi].m_dmamap); 245 sc->rxq[bi].m->m_pkthdr.rcvif = ifp; 246 sc->rxq[bi].m->m_pkthdr.len = 247 sc->rxq[bi].m->m_len = fl; 248 #if NBPFILTER > 0 249 if (ifp->if_bpf) 250 bpf_mtap(ifp->if_bpf, sc->rxq[bi].m); 251 #endif /* NBPFILTER > 0 */ 252 (*ifp->if_input)(ifp, sc->rxq[bi].m); 253 sc->rxq[bi].m = m; 254 bus_dmamap_load(sc->sc_dmat, 255 sc->rxq[bi].m_dmamap, 256 m->m_ext.ext_buf, MCLBYTES, 257 NULL, BUS_DMA_NOWAIT); 258 sc->RXDQ[bi * 2] = 259 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr; 260 } else { 261 /* Drop packets until we can get replacement 262 * empty mbufs for the RXDQ. 263 */ 264 if (m != NULL) { 265 m_freem(m); 266 } 267 ifp->if_ierrors++; 268 } 269 } else { 270 ifp->if_ierrors++; 271 } 272 273 ndq++; 274 275 sc->RXStsQ_cur += 2; 276 if (sc->RXStsQ_cur >= sc->RXStsQ + (RX_QLEN * 2)) { 277 sc->RXStsQ_cur = sc->RXStsQ; 278 } 279 } 280 281 if (ndq > 0) { 282 ifp->if_ipackets += ndq; 283 CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(u_int32_t), 284 RX_QLEN * 4 * sizeof(u_int32_t), 285 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 286 EPE_WRITE(RXStsEnq, ndq); 287 EPE_WRITE(RXDEnq, ndq); 288 ndq = 0; 289 } 290 291 if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 292 epe_ifstart(ifp); 293 } 294 295 irq = EPE_READ(IntStsC); 296 if ((irq & (IntSts_RxSQ|IntSts_ECI)) != 0) 297 goto begin; 298 299 return (1); 300 } 301 302 303 static void 304 epe_init(struct epe_softc *sc) 305 { 306 bus_dma_segment_t segs; 307 char *addr; 308 int rsegs, err, i; 309 struct ifnet * ifp = &sc->sc_ec.ec_if; 310 int mdcdiv = DEFAULT_MDCDIV; 311 312 callout_init(&sc->epe_tick_ch, 0); 313 314 /* Select primary Individual Address in Address Filter Pointer */ 315 EPE_WRITE(AFP, 0); 316 /* Read ethernet MAC, should already be set by bootrom */ 317 bus_space_read_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 318 sc->sc_enaddr, ETHER_ADDR_LEN); 319 printf("%s: MAC address %s\n", sc->sc_dev.dv_xname, 320 ether_sprintf(sc->sc_enaddr)); 321 322 /* Soft Reset the MAC */ 323 EPE_WRITE(SelfCtl, SelfCtl_RESET); 324 while(EPE_READ(SelfCtl) & SelfCtl_RESET); 325 326 /* suggested magic initialization values from datasheet */ 327 EPE_WRITE(RXBufThrshld, 0x800040); 328 EPE_WRITE(TXBufThrshld, 0x200010); 329 EPE_WRITE(RXStsThrshld, 0x40002); 330 EPE_WRITE(TXStsThrshld, 0x40002); 331 EPE_WRITE(RXDThrshld, 0x40002); 332 EPE_WRITE(TXDThrshld, 0x40002); 333 334 /* Allocate a page of memory for descriptor and status queues */ 335 err = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, 0, PAGE_SIZE, 336 &segs, 1, &rsegs, BUS_DMA_WAITOK); 337 if (err == 0) { 338 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, PAGE_SIZE, 339 &sc->ctrlpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT)); 340 } 341 if (err == 0) { 342 err = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 343 0, BUS_DMA_WAITOK, &sc->ctrlpage_dmamap); 344 } 345 if (err == 0) { 346 err = bus_dmamap_load(sc->sc_dmat, sc->ctrlpage_dmamap, 347 sc->ctrlpage, PAGE_SIZE, NULL, BUS_DMA_WAITOK); 348 } 349 if (err != 0) { 350 panic("%s: Cannot get DMA memory", sc->sc_dev.dv_xname); 351 } 352 sc->ctrlpage_dsaddr = sc->ctrlpage_dmamap->dm_segs[0].ds_addr; 353 memset(sc->ctrlpage, 0, PAGE_SIZE); 354 355 /* Set up pointers to start of each queue in kernel addr space. 356 * Each descriptor queue or status queue entry uses 2 words 357 */ 358 sc->TXDQ = (u_int32_t *)sc->ctrlpage; 359 sc->TXDQ_cur = sc->TXDQ; 360 sc->TXDQ_avail = TX_QLEN - 1; 361 sc->TXStsQ = &sc->TXDQ[TX_QLEN * 2]; 362 sc->TXStsQ_cur = sc->TXStsQ; 363 sc->RXDQ = &sc->TXStsQ[TX_QLEN]; 364 sc->RXStsQ = &sc->RXDQ[RX_QLEN * 2]; 365 sc->RXStsQ_cur = sc->RXStsQ; 366 367 /* Program each queue's start addr, cur addr, and len registers 368 * with the physical addresses. 369 */ 370 addr = (char *)sc->ctrlpage_dmamap->dm_segs[0].ds_addr; 371 EPE_WRITE(TXDQBAdd, (u_int32_t)addr); 372 EPE_WRITE(TXDQCurAdd, (u_int32_t)addr); 373 EPE_WRITE(TXDQBLen, TX_QLEN * 2 * sizeof(u_int32_t)); 374 375 addr += (sc->TXStsQ - sc->TXDQ) * sizeof(u_int32_t); 376 EPE_WRITE(TXStsQBAdd, (u_int32_t)addr); 377 EPE_WRITE(TXStsQCurAdd, (u_int32_t)addr); 378 EPE_WRITE(TXStsQBLen, TX_QLEN * sizeof(u_int32_t)); 379 380 addr += (sc->RXDQ - sc->TXStsQ) * sizeof(u_int32_t); 381 EPE_WRITE(RXDQBAdd, (u_int32_t)addr); 382 EPE_WRITE(RXDCurAdd, (u_int32_t)addr); 383 EPE_WRITE(RXDQBLen, RX_QLEN * 2 * sizeof(u_int32_t)); 384 385 addr += (sc->RXStsQ - sc->RXDQ) * sizeof(u_int32_t); 386 EPE_WRITE(RXStsQBAdd, (u_int32_t)addr); 387 EPE_WRITE(RXStsQCurAdd, (u_int32_t)addr); 388 EPE_WRITE(RXStsQBLen, RX_QLEN * 2 * sizeof(u_int32_t)); 389 390 /* Populate the RXDQ with mbufs */ 391 for(i = 0; i < RX_QLEN; i++) { 392 struct mbuf *m; 393 394 bus_dmamap_create(sc->sc_dmat, MCLBYTES, TX_QLEN/4, MCLBYTES, 0, 395 BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 396 MGETHDR(m, M_WAIT, MT_DATA); 397 MCLGET(m, M_WAIT); 398 sc->rxq[i].m = m; 399 bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 400 m->m_ext.ext_buf, MCLBYTES, NULL, 401 BUS_DMA_WAITOK); 402 403 sc->RXDQ[i * 2] = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr; 404 sc->RXDQ[i * 2 + 1] = (i << 16) | MCLBYTES; 405 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 406 MCLBYTES, BUS_DMASYNC_PREREAD); 407 } 408 409 for(i = 0; i < TX_QLEN; i++) { 410 bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 411 (BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW), 412 &sc->txq[i].m_dmamap); 413 sc->txq[i].m = NULL; 414 sc->TXDQ[i * 2 + 1] = (i << 16); 415 } 416 417 /* Divide HCLK by 32 for MDC clock */ 418 if (device_cfdata(&sc->sc_dev)->cf_flags) 419 mdcdiv = device_cfdata(&sc->sc_dev)->cf_flags; 420 EPE_WRITE(SelfCtl, (SelfCtl_MDCDIV(mdcdiv)|SelfCtl_PSPRS)); 421 422 sc->sc_mii.mii_ifp = ifp; 423 sc->sc_mii.mii_readreg = epe_mii_readreg; 424 sc->sc_mii.mii_writereg = epe_mii_writereg; 425 sc->sc_mii.mii_statchg = epe_statchg; 426 sc->sc_ec.ec_mii = &sc->sc_mii; 427 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, epe_mediachange, 428 ether_mediastatus); 429 mii_attach((struct device *)sc, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 430 MII_OFFSET_ANY, 0); 431 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 432 433 EPE_WRITE(BMCtl, BMCtl_RxEn|BMCtl_TxEn); 434 EPE_WRITE(IntEn, IntEn_REOFIE); 435 /* maximum valid max frame length */ 436 EPE_WRITE(MaxFrmLen, (0x7ff << 16)|MHLEN); 437 /* wait for receiver ready */ 438 while((EPE_READ(BMSts) & BMSts_RxAct) == 0); 439 /* enqueue the entries in RXStsQ and RXDQ */ 440 CTRLPAGE_DMASYNC(0, sc->ctrlpage_dmamap->dm_mapsize, 441 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 442 EPE_WRITE(RXDEnq, RX_QLEN - 1); 443 EPE_WRITE(RXStsEnq, RX_QLEN - 1); 444 445 /* 446 * We can support 802.1Q VLAN-sized frames. 447 */ 448 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 449 450 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 451 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 452 ifp->if_ioctl = epe_ifioctl; 453 ifp->if_start = epe_ifstart; 454 ifp->if_watchdog = epe_ifwatchdog; 455 ifp->if_init = epe_ifinit; 456 ifp->if_stop = epe_ifstop; 457 ifp->if_timer = 0; 458 ifp->if_softc = sc; 459 IFQ_SET_READY(&ifp->if_snd); 460 if_attach(ifp); 461 ether_ifattach(ifp, (sc)->sc_enaddr); 462 } 463 464 static int 465 epe_mediachange(struct ifnet *ifp) 466 { 467 if (ifp->if_flags & IFF_UP) 468 epe_ifinit(ifp); 469 return (0); 470 } 471 472 int 473 epe_mii_readreg(struct device *self, int phy, int reg) 474 { 475 u_int32_t d, v; 476 struct epe_softc *sc; 477 478 sc = (struct epe_softc *)self; 479 d = EPE_READ(SelfCtl); 480 EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */ 481 EPE_WRITE(MIICmd, (MIICmd_READ | (phy << 5) | reg)); 482 while(EPE_READ(MIISts) & MIISts_BUSY); 483 v = EPE_READ(MIIData); 484 EPE_WRITE(SelfCtl, d); /* restore old value */ 485 return v; 486 } 487 488 void 489 epe_mii_writereg(struct device *self, int phy, int reg, int val) 490 { 491 struct epe_softc *sc; 492 u_int32_t d; 493 494 sc = (struct epe_softc *)self; 495 d = EPE_READ(SelfCtl); 496 EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */ 497 EPE_WRITE(MIIData, val); 498 EPE_WRITE(MIICmd, (MIICmd_WRITE | (phy << 5) | reg)); 499 while(EPE_READ(MIISts) & MIISts_BUSY); 500 EPE_WRITE(SelfCtl, d); /* restore old value */ 501 } 502 503 504 void 505 epe_statchg(struct device *self) 506 { 507 struct epe_softc *sc = (struct epe_softc *)self; 508 u_int32_t reg; 509 510 /* 511 * We must keep the MAC and the PHY in sync as 512 * to the status of full-duplex! 513 */ 514 reg = EPE_READ(TestCtl); 515 if (sc->sc_mii.mii_media_active & IFM_FDX) 516 reg |= TestCtl_MFDX; 517 else 518 reg &= ~TestCtl_MFDX; 519 EPE_WRITE(TestCtl, reg); 520 } 521 522 void 523 epe_tick(void *arg) 524 { 525 struct epe_softc* sc = (struct epe_softc *)arg; 526 struct ifnet * ifp = &sc->sc_ec.ec_if; 527 int s; 528 u_int32_t misses; 529 530 ifp->if_collisions += EPE_READ(TXCollCnt); 531 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 532 misses = EPE_READ(RXMissCnt); 533 if (misses > 0) 534 printf("%s: %d rx misses\n", sc->sc_dev.dv_xname, misses); 535 536 s = splnet(); 537 if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 538 epe_ifstart(ifp); 539 } 540 splx(s); 541 542 mii_tick(&sc->sc_mii); 543 callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc); 544 } 545 546 547 static int 548 epe_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 549 { 550 int s, error; 551 552 s = splnet(); 553 error = ether_ioctl(ifp, cmd, data); 554 if (error == ENETRESET) { 555 if (ifp->if_flags & IFF_RUNNING) 556 epe_setaddr(ifp); 557 error = 0; 558 } 559 splx(s); 560 return error; 561 } 562 563 static void 564 epe_ifstart(struct ifnet *ifp) 565 { 566 struct epe_softc *sc = (struct epe_softc *)ifp->if_softc; 567 struct mbuf *m; 568 bus_dma_segment_t *segs; 569 int s, bi, err, nsegs, ndq; 570 571 s = splnet(); 572 start: 573 ndq = 0; 574 if (sc->TXDQ_avail == 0) { 575 if (epe_gctx(sc) == 0) { 576 /* Enable End-Of-TX-Chain interrupt */ 577 EPE_WRITE(IntEn, IntEn_REOFIE|IntEn_ECIE); 578 ifp->if_flags |= IFF_OACTIVE; 579 ifp->if_timer = 10; 580 splx(s); 581 return; 582 } 583 } 584 585 bi = sc->TXDQ_cur - sc->TXDQ; 586 587 IFQ_POLL(&ifp->if_snd, m); 588 if (m == NULL) { 589 splx(s); 590 return; 591 } 592 more: 593 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 594 BUS_DMA_NOWAIT)) || 595 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 596 sc->txq[bi].m_dmamap->dm_nsegs > (sc->TXDQ_avail - ndq)) { 597 /* Copy entire mbuf chain to new and 32-bit aligned storage */ 598 struct mbuf *mn; 599 600 if (err == 0) 601 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 602 603 MGETHDR(mn, M_DONTWAIT, MT_DATA); 604 if (mn == NULL) goto stop; 605 if (m->m_pkthdr.len > (MHLEN & (~0x3))) { 606 MCLGET(mn, M_DONTWAIT); 607 if ((mn->m_flags & M_EXT) == 0) { 608 m_freem(mn); 609 goto stop; 610 } 611 } 612 mn->m_data = (void *)(((u_int32_t)mn->m_data + 0x3) & (~0x3)); 613 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 614 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 615 IFQ_DEQUEUE(&ifp->if_snd, m); 616 m_freem(m); 617 m = mn; 618 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 619 BUS_DMA_NOWAIT); 620 } else { 621 IFQ_DEQUEUE(&ifp->if_snd, m); 622 } 623 624 #if NBPFILTER > 0 625 if (ifp->if_bpf) 626 bpf_mtap(ifp->if_bpf, m); 627 #endif /* NBPFILTER > 0 */ 628 629 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 630 segs = sc->txq[bi].m_dmamap->dm_segs; 631 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 632 sc->txq[bi].m_dmamap->dm_mapsize, 633 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 634 635 /* XXX: This driver hasn't been tested w/nsegs > 1 */ 636 while (nsegs > 0) { 637 nsegs--; 638 sc->txq[bi].m = m; 639 sc->TXDQ[bi * 2] = segs->ds_addr; 640 if (nsegs == 0) 641 sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16) | 642 (1 << 31); 643 else 644 sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16); 645 segs++; 646 bi = (bi + 1) % TX_QLEN; 647 ndq++; 648 } 649 650 651 /* 652 * Enqueue another. Don't do more than half the available 653 * descriptors before telling the MAC about them 654 */ 655 if ((sc->TXDQ_avail - ndq) > 0 && ndq < TX_QLEN / 2) { 656 IFQ_POLL(&ifp->if_snd, m); 657 if (m != NULL) { 658 goto more; 659 } 660 } 661 stop: 662 if (ndq > 0) { 663 sc->TXDQ_avail -= ndq; 664 sc->TXDQ_cur = &sc->TXDQ[bi]; 665 CTRLPAGE_DMASYNC(0, TX_QLEN * 2 * sizeof(u_int32_t), 666 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 667 EPE_WRITE(TXDEnq, ndq); 668 } 669 670 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 671 goto start; 672 673 splx(s); 674 return; 675 } 676 677 static void 678 epe_ifwatchdog(struct ifnet *ifp) 679 { 680 struct epe_softc *sc = (struct epe_softc *)ifp->if_softc; 681 682 if ((ifp->if_flags & IFF_RUNNING) == 0) 683 return; 684 printf("%s: device timeout, BMCtl = 0x%08x, BMSts = 0x%08x\n", 685 sc->sc_dev.dv_xname, EPE_READ(BMCtl), EPE_READ(BMSts)); 686 } 687 688 static int 689 epe_ifinit(struct ifnet *ifp) 690 { 691 struct epe_softc *sc = ifp->if_softc; 692 int rc, s = splnet(); 693 694 callout_stop(&sc->epe_tick_ch); 695 EPE_WRITE(RXCtl, RXCtl_IA0|RXCtl_BA|RXCtl_RCRCA|RXCtl_SRxON); 696 EPE_WRITE(TXCtl, TXCtl_STxON); 697 EPE_WRITE(GIIntMsk, GIIntMsk_INT); /* start interrupting */ 698 699 if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 700 rc = 0; 701 else if (rc != 0) 702 goto out; 703 704 callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc); 705 ifp->if_flags |= IFF_RUNNING; 706 out: 707 splx(s); 708 return 0; 709 } 710 711 static void 712 epe_ifstop(struct ifnet *ifp, int disable) 713 { 714 struct epe_softc *sc = ifp->if_softc; 715 716 717 EPE_WRITE(RXCtl, 0); 718 EPE_WRITE(TXCtl, 0); 719 EPE_WRITE(GIIntMsk, 0); 720 callout_stop(&sc->epe_tick_ch); 721 722 /* Down the MII. */ 723 mii_down(&sc->sc_mii); 724 725 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 726 ifp->if_timer = 0; 727 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 728 } 729 730 static void 731 epe_setaddr(struct ifnet *ifp) 732 { 733 struct epe_softc *sc = ifp->if_softc; 734 struct ethercom *ac = &sc->sc_ec; 735 struct ether_multi *enm; 736 struct ether_multistep step; 737 u_int8_t ias[2][ETHER_ADDR_LEN]; 738 u_int32_t h, nma = 0, hashes[2] = { 0, 0 }; 739 u_int32_t rxctl = EPE_READ(RXCtl); 740 741 /* disable receiver temporarily */ 742 EPE_WRITE(RXCtl, rxctl & ~RXCtl_SRxON); 743 744 rxctl &= ~(RXCtl_MA|RXCtl_PA|RXCtl_IA2|RXCtl_IA3); 745 746 if (ifp->if_flags & IFF_PROMISC) { 747 rxctl |= RXCtl_PA; 748 } 749 750 ifp->if_flags &= ~IFF_ALLMULTI; 751 752 ETHER_FIRST_MULTI(step, ac, enm); 753 while (enm != NULL) { 754 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 755 /* 756 * We must listen to a range of multicast addresses. 757 * For now, just accept all multicasts, rather than 758 * trying to set only those filter bits needed to match 759 * the range. (At this time, the only use of address 760 * ranges is for IP multicast routing, for which the 761 * range is big enough to require all bits set.) 762 */ 763 rxctl &= ~(RXCtl_IA2|RXCtl_IA3); 764 rxctl |= RXCtl_MA; 765 hashes[0] = 0xffffffffUL; 766 hashes[1] = 0xffffffffUL; 767 ifp->if_flags |= IFF_ALLMULTI; 768 break; 769 } 770 771 if (nma < 2) { 772 /* We can program 2 perfect address filters for mcast */ 773 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 774 rxctl |= (1 << (nma + 2)); 775 } else { 776 /* 777 * XXX: Datasheet is not very clear here, I'm not sure 778 * if I'm doing this right. --joff 779 */ 780 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 781 782 /* Just want the 6 most-significant bits. */ 783 h = h >> 26; 784 785 hashes[ h / 32 ] |= (1 << (h % 32)); 786 rxctl |= RXCtl_MA; 787 } 788 ETHER_NEXT_MULTI(step, enm); 789 nma++; 790 } 791 792 EPE_WRITE(AFP, 0); 793 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 794 sc->sc_enaddr, ETHER_ADDR_LEN); 795 if (rxctl & RXCtl_IA2) { 796 EPE_WRITE(AFP, 2); 797 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 798 ias[0], ETHER_ADDR_LEN); 799 } 800 if (rxctl & RXCtl_IA3) { 801 EPE_WRITE(AFP, 3); 802 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 803 ias[1], ETHER_ADDR_LEN); 804 } 805 if (hashes[0] != 0 && hashes[1] != 0) { 806 EPE_WRITE(AFP, 7); 807 EPE_WRITE(HashTbl, hashes[0]); 808 EPE_WRITE(HashTbl + 4, hashes[1]); 809 } 810 EPE_WRITE(RXCtl, rxctl); 811 } 812
Indexes created Tue Sep 30 11:09:46 GMT 2025