epe.c revision 1.24
1 /* $NetBSD: epe.c,v 1.24 2010/01/22 08:56:04 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Jesse Off 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: epe.c,v 1.24 2010/01/22 08:56:04 martin Exp $"); 31 32 #include <sys/types.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/ioctl.h> 36 #include <sys/kernel.h> 37 #include <sys/proc.h> 38 #include <sys/malloc.h> 39 #include <sys/time.h> 40 #include <sys/device.h> 41 #include <uvm/uvm_extern.h> 42 43 #include <machine/bus.h> 44 #include <machine/intr.h> 45 46 #include <arm/cpufunc.h> 47 48 #include <arm/ep93xx/epsocvar.h> 49 #include <arm/ep93xx/ep93xxvar.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_types.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #include <dev/mii/mii.h> 58 #include <dev/mii/miivar.h> 59 60 #ifdef INET 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/in_var.h> 64 #include <netinet/ip.h> 65 #include <netinet/if_inarp.h> 66 #endif 67 68 #ifdef NS 69 #include <netns/ns.h> 70 #include <netns/ns_if.h> 71 #endif 72 73 #include <net/bpf.h> 74 #include <net/bpfdesc.h> 75 76 #include <arm/ep93xx/ep93xxreg.h> 77 #include <arm/ep93xx/epereg.h> 78 #include <arm/ep93xx/epevar.h> 79 80 #define DEFAULT_MDCDIV 32 81 82 #ifndef EPE_FAST 83 #define EPE_FAST 84 #endif 85 86 #ifndef EPE_FAST 87 #define EPE_READ(x) \ 88 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x)) 89 #define EPE_WRITE(x, y) \ 90 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x), (y)) 91 #define CTRLPAGE_DMASYNC(x, y, z) \ 92 bus_dmamap_sync(sc->sc_dmat, sc->ctrlpage_dmamap, (x), (y), (z)) 93 #else 94 #define EPE_READ(x) *(volatile u_int32_t *) \ 95 (EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x)) 96 #define EPE_WRITE(x, y) *(volatile u_int32_t *) \ 97 (EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x)) = y 98 #define CTRLPAGE_DMASYNC(x, y, z) 99 #endif /* ! EPE_FAST */ 100 101 static int epe_match(struct device *, struct cfdata *, void *); 102 static void epe_attach(struct device *, struct device *, void *); 103 static void epe_init(struct epe_softc *); 104 static int epe_intr(void* arg); 105 static int epe_gctx(struct epe_softc *); 106 static int epe_mediachange(struct ifnet *); 107 int epe_mii_readreg (struct device *, int, int); 108 void epe_mii_writereg (struct device *, int, int, int); 109 void epe_statchg (struct device *); 110 void epe_tick (void *); 111 static int epe_ifioctl (struct ifnet *, u_long, void *); 112 static void epe_ifstart (struct ifnet *); 113 static void epe_ifwatchdog (struct ifnet *); 114 static int epe_ifinit (struct ifnet *); 115 static void epe_ifstop (struct ifnet *, int); 116 static void epe_setaddr (struct ifnet *); 117 118 CFATTACH_DECL(epe, sizeof(struct epe_softc), 119 epe_match, epe_attach, NULL, NULL); 120 121 static int 122 epe_match(struct device *parent, struct cfdata *match, void *aux) 123 { 124 return 2; 125 } 126 127 static void 128 epe_attach(struct device *parent, struct device *self, void *aux) 129 { 130 struct epe_softc *sc; 131 struct epsoc_attach_args *sa; 132 prop_data_t enaddr; 133 134 printf("\n"); 135 sc = (struct epe_softc*) self; 136 sa = aux; 137 sc->sc_iot = sa->sa_iot; 138 sc->sc_intr = sa->sa_intr; 139 sc->sc_dmat = sa->sa_dmat; 140 141 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 142 0, &sc->sc_ioh)) 143 panic("%s: Cannot map registers", self->dv_xname); 144 145 /* Fetch the Ethernet address from property if set. */ 146 enaddr = prop_dictionary_get(device_properties(self), "mac-address"); 147 if (enaddr != NULL) { 148 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 149 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 150 memcpy(sc->sc_enaddr, prop_data_data_nocopy(enaddr), 151 ETHER_ADDR_LEN); 152 bus_space_write_4(sc->sc_iot, sc->sc_ioh, EPE_AFP, 0); 153 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 154 sc->sc_enaddr, ETHER_ADDR_LEN); 155 } 156 157 ep93xx_intr_establish(sc->sc_intr, IPL_NET, epe_intr, sc); 158 epe_init(sc); 159 } 160 161 static int 162 epe_gctx(struct epe_softc *sc) 163 { 164 struct ifnet * ifp = &sc->sc_ec.ec_if; 165 u_int32_t *cur, ndq = 0; 166 167 /* Handle transmit completions */ 168 cur = (u_int32_t *)(EPE_READ(TXStsQCurAdd) - 169 sc->ctrlpage_dsaddr + (char*)sc->ctrlpage); 170 171 if (sc->TXStsQ_cur != cur) { 172 CTRLPAGE_DMASYNC(TX_QLEN * 2 * sizeof(u_int32_t), 173 TX_QLEN * sizeof(u_int32_t), BUS_DMASYNC_PREREAD); 174 } else { 175 return 0; 176 } 177 178 do { 179 u_int32_t tbi = *sc->TXStsQ_cur & 0x7fff; 180 struct mbuf *m = sc->txq[tbi].m; 181 182 if ((*sc->TXStsQ_cur & TXStsQ_TxWE) == 0) { 183 ifp->if_oerrors++; 184 } 185 bus_dmamap_unload(sc->sc_dmat, sc->txq[tbi].m_dmamap); 186 m_freem(m); 187 do { 188 sc->txq[tbi].m = NULL; 189 ndq++; 190 tbi = (tbi + 1) % TX_QLEN; 191 } while (sc->txq[tbi].m == m); 192 193 ifp->if_opackets++; 194 sc->TXStsQ_cur++; 195 if (sc->TXStsQ_cur >= sc->TXStsQ + TX_QLEN) { 196 sc->TXStsQ_cur = sc->TXStsQ; 197 } 198 } while (sc->TXStsQ_cur != cur); 199 200 sc->TXDQ_avail += ndq; 201 if (ifp->if_flags & IFF_OACTIVE) { 202 ifp->if_flags &= ~IFF_OACTIVE; 203 /* Disable end-of-tx-chain interrupt */ 204 EPE_WRITE(IntEn, IntEn_REOFIE); 205 } 206 return ndq; 207 } 208 209 static int 210 epe_intr(void *arg) 211 { 212 struct epe_softc *sc = (struct epe_softc *)arg; 213 struct ifnet * ifp = &sc->sc_ec.ec_if; 214 u_int32_t ndq = 0, irq, *cur; 215 216 irq = EPE_READ(IntStsC); 217 begin: 218 cur = (u_int32_t *)(EPE_READ(RXStsQCurAdd) - 219 sc->ctrlpage_dsaddr + (char*)sc->ctrlpage); 220 CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(u_int32_t), 221 RX_QLEN * 4 * sizeof(u_int32_t), 222 BUS_DMASYNC_PREREAD); 223 while (sc->RXStsQ_cur != cur) { 224 if ((sc->RXStsQ_cur[0] & (RXStsQ_RWE|RXStsQ_RFP|RXStsQ_EOB)) == 225 (RXStsQ_RWE|RXStsQ_RFP|RXStsQ_EOB)) { 226 u_int32_t bi = (sc->RXStsQ_cur[1] >> 16) & 0x7fff; 227 u_int32_t fl = sc->RXStsQ_cur[1] & 0xffff; 228 struct mbuf *m; 229 230 MGETHDR(m, M_DONTWAIT, MT_DATA); 231 if (m != NULL) MCLGET(m, M_DONTWAIT); 232 if (m != NULL && (m->m_flags & M_EXT)) { 233 bus_dmamap_unload(sc->sc_dmat, 234 sc->rxq[bi].m_dmamap); 235 sc->rxq[bi].m->m_pkthdr.rcvif = ifp; 236 sc->rxq[bi].m->m_pkthdr.len = 237 sc->rxq[bi].m->m_len = fl; 238 if (ifp->if_bpf) 239 bpf_ops->bpf_mtap(ifp->if_bpf, sc->rxq[bi].m); 240 (*ifp->if_input)(ifp, sc->rxq[bi].m); 241 sc->rxq[bi].m = m; 242 bus_dmamap_load(sc->sc_dmat, 243 sc->rxq[bi].m_dmamap, 244 m->m_ext.ext_buf, MCLBYTES, 245 NULL, BUS_DMA_NOWAIT); 246 sc->RXDQ[bi * 2] = 247 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr; 248 } else { 249 /* Drop packets until we can get replacement 250 * empty mbufs for the RXDQ. 251 */ 252 if (m != NULL) { 253 m_freem(m); 254 } 255 ifp->if_ierrors++; 256 } 257 } else { 258 ifp->if_ierrors++; 259 } 260 261 ndq++; 262 263 sc->RXStsQ_cur += 2; 264 if (sc->RXStsQ_cur >= sc->RXStsQ + (RX_QLEN * 2)) { 265 sc->RXStsQ_cur = sc->RXStsQ; 266 } 267 } 268 269 if (ndq > 0) { 270 ifp->if_ipackets += ndq; 271 CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(u_int32_t), 272 RX_QLEN * 4 * sizeof(u_int32_t), 273 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 274 EPE_WRITE(RXStsEnq, ndq); 275 EPE_WRITE(RXDEnq, ndq); 276 ndq = 0; 277 } 278 279 if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 280 epe_ifstart(ifp); 281 } 282 283 irq = EPE_READ(IntStsC); 284 if ((irq & (IntSts_RxSQ|IntSts_ECI)) != 0) 285 goto begin; 286 287 return (1); 288 } 289 290 291 static void 292 epe_init(struct epe_softc *sc) 293 { 294 bus_dma_segment_t segs; 295 char *addr; 296 int rsegs, err, i; 297 struct ifnet * ifp = &sc->sc_ec.ec_if; 298 int mdcdiv = DEFAULT_MDCDIV; 299 300 callout_init(&sc->epe_tick_ch, 0); 301 302 /* Select primary Individual Address in Address Filter Pointer */ 303 EPE_WRITE(AFP, 0); 304 /* Read ethernet MAC, should already be set by bootrom */ 305 bus_space_read_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 306 sc->sc_enaddr, ETHER_ADDR_LEN); 307 printf("%s: MAC address %s\n", sc->sc_dev.dv_xname, 308 ether_sprintf(sc->sc_enaddr)); 309 310 /* Soft Reset the MAC */ 311 EPE_WRITE(SelfCtl, SelfCtl_RESET); 312 while(EPE_READ(SelfCtl) & SelfCtl_RESET); 313 314 /* suggested magic initialization values from datasheet */ 315 EPE_WRITE(RXBufThrshld, 0x800040); 316 EPE_WRITE(TXBufThrshld, 0x200010); 317 EPE_WRITE(RXStsThrshld, 0x40002); 318 EPE_WRITE(TXStsThrshld, 0x40002); 319 EPE_WRITE(RXDThrshld, 0x40002); 320 EPE_WRITE(TXDThrshld, 0x40002); 321 322 /* Allocate a page of memory for descriptor and status queues */ 323 err = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, 0, PAGE_SIZE, 324 &segs, 1, &rsegs, BUS_DMA_WAITOK); 325 if (err == 0) { 326 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, PAGE_SIZE, 327 &sc->ctrlpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT)); 328 } 329 if (err == 0) { 330 err = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 331 0, BUS_DMA_WAITOK, &sc->ctrlpage_dmamap); 332 } 333 if (err == 0) { 334 err = bus_dmamap_load(sc->sc_dmat, sc->ctrlpage_dmamap, 335 sc->ctrlpage, PAGE_SIZE, NULL, BUS_DMA_WAITOK); 336 } 337 if (err != 0) { 338 panic("%s: Cannot get DMA memory", sc->sc_dev.dv_xname); 339 } 340 sc->ctrlpage_dsaddr = sc->ctrlpage_dmamap->dm_segs[0].ds_addr; 341 memset(sc->ctrlpage, 0, PAGE_SIZE); 342 343 /* Set up pointers to start of each queue in kernel addr space. 344 * Each descriptor queue or status queue entry uses 2 words 345 */ 346 sc->TXDQ = (u_int32_t *)sc->ctrlpage; 347 sc->TXDQ_cur = sc->TXDQ; 348 sc->TXDQ_avail = TX_QLEN - 1; 349 sc->TXStsQ = &sc->TXDQ[TX_QLEN * 2]; 350 sc->TXStsQ_cur = sc->TXStsQ; 351 sc->RXDQ = &sc->TXStsQ[TX_QLEN]; 352 sc->RXStsQ = &sc->RXDQ[RX_QLEN * 2]; 353 sc->RXStsQ_cur = sc->RXStsQ; 354 355 /* Program each queue's start addr, cur addr, and len registers 356 * with the physical addresses. 357 */ 358 addr = (char *)sc->ctrlpage_dmamap->dm_segs[0].ds_addr; 359 EPE_WRITE(TXDQBAdd, (u_int32_t)addr); 360 EPE_WRITE(TXDQCurAdd, (u_int32_t)addr); 361 EPE_WRITE(TXDQBLen, TX_QLEN * 2 * sizeof(u_int32_t)); 362 363 addr += (sc->TXStsQ - sc->TXDQ) * sizeof(u_int32_t); 364 EPE_WRITE(TXStsQBAdd, (u_int32_t)addr); 365 EPE_WRITE(TXStsQCurAdd, (u_int32_t)addr); 366 EPE_WRITE(TXStsQBLen, TX_QLEN * sizeof(u_int32_t)); 367 368 addr += (sc->RXDQ - sc->TXStsQ) * sizeof(u_int32_t); 369 EPE_WRITE(RXDQBAdd, (u_int32_t)addr); 370 EPE_WRITE(RXDCurAdd, (u_int32_t)addr); 371 EPE_WRITE(RXDQBLen, RX_QLEN * 2 * sizeof(u_int32_t)); 372 373 addr += (sc->RXStsQ - sc->RXDQ) * sizeof(u_int32_t); 374 EPE_WRITE(RXStsQBAdd, (u_int32_t)addr); 375 EPE_WRITE(RXStsQCurAdd, (u_int32_t)addr); 376 EPE_WRITE(RXStsQBLen, RX_QLEN * 2 * sizeof(u_int32_t)); 377 378 /* Populate the RXDQ with mbufs */ 379 for(i = 0; i < RX_QLEN; i++) { 380 struct mbuf *m; 381 382 bus_dmamap_create(sc->sc_dmat, MCLBYTES, TX_QLEN/4, MCLBYTES, 0, 383 BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 384 MGETHDR(m, M_WAIT, MT_DATA); 385 MCLGET(m, M_WAIT); 386 sc->rxq[i].m = m; 387 bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 388 m->m_ext.ext_buf, MCLBYTES, NULL, 389 BUS_DMA_WAITOK); 390 391 sc->RXDQ[i * 2] = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr; 392 sc->RXDQ[i * 2 + 1] = (i << 16) | MCLBYTES; 393 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 394 MCLBYTES, BUS_DMASYNC_PREREAD); 395 } 396 397 for(i = 0; i < TX_QLEN; i++) { 398 bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 399 (BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW), 400 &sc->txq[i].m_dmamap); 401 sc->txq[i].m = NULL; 402 sc->TXDQ[i * 2 + 1] = (i << 16); 403 } 404 405 /* Divide HCLK by 32 for MDC clock */ 406 if (device_cfdata(&sc->sc_dev)->cf_flags) 407 mdcdiv = device_cfdata(&sc->sc_dev)->cf_flags; 408 EPE_WRITE(SelfCtl, (SelfCtl_MDCDIV(mdcdiv)|SelfCtl_PSPRS)); 409 410 sc->sc_mii.mii_ifp = ifp; 411 sc->sc_mii.mii_readreg = epe_mii_readreg; 412 sc->sc_mii.mii_writereg = epe_mii_writereg; 413 sc->sc_mii.mii_statchg = epe_statchg; 414 sc->sc_ec.ec_mii = &sc->sc_mii; 415 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, epe_mediachange, 416 ether_mediastatus); 417 mii_attach((struct device *)sc, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 418 MII_OFFSET_ANY, 0); 419 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 420 421 EPE_WRITE(BMCtl, BMCtl_RxEn|BMCtl_TxEn); 422 EPE_WRITE(IntEn, IntEn_REOFIE); 423 /* maximum valid max frame length */ 424 EPE_WRITE(MaxFrmLen, (0x7ff << 16)|MHLEN); 425 /* wait for receiver ready */ 426 while((EPE_READ(BMSts) & BMSts_RxAct) == 0); 427 /* enqueue the entries in RXStsQ and RXDQ */ 428 CTRLPAGE_DMASYNC(0, sc->ctrlpage_dmamap->dm_mapsize, 429 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 430 EPE_WRITE(RXDEnq, RX_QLEN - 1); 431 EPE_WRITE(RXStsEnq, RX_QLEN - 1); 432 433 /* 434 * We can support 802.1Q VLAN-sized frames. 435 */ 436 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 437 438 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 439 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 440 ifp->if_ioctl = epe_ifioctl; 441 ifp->if_start = epe_ifstart; 442 ifp->if_watchdog = epe_ifwatchdog; 443 ifp->if_init = epe_ifinit; 444 ifp->if_stop = epe_ifstop; 445 ifp->if_timer = 0; 446 ifp->if_softc = sc; 447 IFQ_SET_READY(&ifp->if_snd); 448 if_attach(ifp); 449 ether_ifattach(ifp, (sc)->sc_enaddr); 450 } 451 452 static int 453 epe_mediachange(struct ifnet *ifp) 454 { 455 if (ifp->if_flags & IFF_UP) 456 epe_ifinit(ifp); 457 return (0); 458 } 459 460 int 461 epe_mii_readreg(struct device *self, int phy, int reg) 462 { 463 u_int32_t d, v; 464 struct epe_softc *sc; 465 466 sc = (struct epe_softc *)self; 467 d = EPE_READ(SelfCtl); 468 EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */ 469 EPE_WRITE(MIICmd, (MIICmd_READ | (phy << 5) | reg)); 470 while(EPE_READ(MIISts) & MIISts_BUSY); 471 v = EPE_READ(MIIData); 472 EPE_WRITE(SelfCtl, d); /* restore old value */ 473 return v; 474 } 475 476 void 477 epe_mii_writereg(struct device *self, int phy, int reg, int val) 478 { 479 struct epe_softc *sc; 480 u_int32_t d; 481 482 sc = (struct epe_softc *)self; 483 d = EPE_READ(SelfCtl); 484 EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */ 485 EPE_WRITE(MIIData, val); 486 EPE_WRITE(MIICmd, (MIICmd_WRITE | (phy << 5) | reg)); 487 while(EPE_READ(MIISts) & MIISts_BUSY); 488 EPE_WRITE(SelfCtl, d); /* restore old value */ 489 } 490 491 492 void 493 epe_statchg(struct device *self) 494 { 495 struct epe_softc *sc = (struct epe_softc *)self; 496 u_int32_t reg; 497 498 /* 499 * We must keep the MAC and the PHY in sync as 500 * to the status of full-duplex! 501 */ 502 reg = EPE_READ(TestCtl); 503 if (sc->sc_mii.mii_media_active & IFM_FDX) 504 reg |= TestCtl_MFDX; 505 else 506 reg &= ~TestCtl_MFDX; 507 EPE_WRITE(TestCtl, reg); 508 } 509 510 void 511 epe_tick(void *arg) 512 { 513 struct epe_softc* sc = (struct epe_softc *)arg; 514 struct ifnet * ifp = &sc->sc_ec.ec_if; 515 int s; 516 u_int32_t misses; 517 518 ifp->if_collisions += EPE_READ(TXCollCnt); 519 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 520 misses = EPE_READ(RXMissCnt); 521 if (misses > 0) 522 printf("%s: %d rx misses\n", sc->sc_dev.dv_xname, misses); 523 524 s = splnet(); 525 if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 526 epe_ifstart(ifp); 527 } 528 splx(s); 529 530 mii_tick(&sc->sc_mii); 531 callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc); 532 } 533 534 535 static int 536 epe_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 537 { 538 int s, error; 539 540 s = splnet(); 541 error = ether_ioctl(ifp, cmd, data); 542 if (error == ENETRESET) { 543 if (ifp->if_flags & IFF_RUNNING) 544 epe_setaddr(ifp); 545 error = 0; 546 } 547 splx(s); 548 return error; 549 } 550 551 static void 552 epe_ifstart(struct ifnet *ifp) 553 { 554 struct epe_softc *sc = (struct epe_softc *)ifp->if_softc; 555 struct mbuf *m; 556 bus_dma_segment_t *segs; 557 int s, bi, err, nsegs, ndq; 558 559 s = splnet(); 560 start: 561 ndq = 0; 562 if (sc->TXDQ_avail == 0) { 563 if (epe_gctx(sc) == 0) { 564 /* Enable End-Of-TX-Chain interrupt */ 565 EPE_WRITE(IntEn, IntEn_REOFIE|IntEn_ECIE); 566 ifp->if_flags |= IFF_OACTIVE; 567 ifp->if_timer = 10; 568 splx(s); 569 return; 570 } 571 } 572 573 bi = sc->TXDQ_cur - sc->TXDQ; 574 575 IFQ_POLL(&ifp->if_snd, m); 576 if (m == NULL) { 577 splx(s); 578 return; 579 } 580 more: 581 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 582 BUS_DMA_NOWAIT)) || 583 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 584 sc->txq[bi].m_dmamap->dm_nsegs > (sc->TXDQ_avail - ndq)) { 585 /* Copy entire mbuf chain to new and 32-bit aligned storage */ 586 struct mbuf *mn; 587 588 if (err == 0) 589 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 590 591 MGETHDR(mn, M_DONTWAIT, MT_DATA); 592 if (mn == NULL) goto stop; 593 if (m->m_pkthdr.len > (MHLEN & (~0x3))) { 594 MCLGET(mn, M_DONTWAIT); 595 if ((mn->m_flags & M_EXT) == 0) { 596 m_freem(mn); 597 goto stop; 598 } 599 } 600 mn->m_data = (void *)(((u_int32_t)mn->m_data + 0x3) & (~0x3)); 601 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 602 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 603 IFQ_DEQUEUE(&ifp->if_snd, m); 604 m_freem(m); 605 m = mn; 606 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 607 BUS_DMA_NOWAIT); 608 } else { 609 IFQ_DEQUEUE(&ifp->if_snd, m); 610 } 611 612 if (ifp->if_bpf) 613 bpf_ops->bpf_mtap(ifp->if_bpf, m); 614 615 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 616 segs = sc->txq[bi].m_dmamap->dm_segs; 617 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 618 sc->txq[bi].m_dmamap->dm_mapsize, 619 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 620 621 /* XXX: This driver hasn't been tested w/nsegs > 1 */ 622 while (nsegs > 0) { 623 nsegs--; 624 sc->txq[bi].m = m; 625 sc->TXDQ[bi * 2] = segs->ds_addr; 626 if (nsegs == 0) 627 sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16) | 628 (1 << 31); 629 else 630 sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16); 631 segs++; 632 bi = (bi + 1) % TX_QLEN; 633 ndq++; 634 } 635 636 637 /* 638 * Enqueue another. Don't do more than half the available 639 * descriptors before telling the MAC about them 640 */ 641 if ((sc->TXDQ_avail - ndq) > 0 && ndq < TX_QLEN / 2) { 642 IFQ_POLL(&ifp->if_snd, m); 643 if (m != NULL) { 644 goto more; 645 } 646 } 647 stop: 648 if (ndq > 0) { 649 sc->TXDQ_avail -= ndq; 650 sc->TXDQ_cur = &sc->TXDQ[bi]; 651 CTRLPAGE_DMASYNC(0, TX_QLEN * 2 * sizeof(u_int32_t), 652 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 653 EPE_WRITE(TXDEnq, ndq); 654 } 655 656 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 657 goto start; 658 659 splx(s); 660 return; 661 } 662 663 static void 664 epe_ifwatchdog(struct ifnet *ifp) 665 { 666 struct epe_softc *sc = (struct epe_softc *)ifp->if_softc; 667 668 if ((ifp->if_flags & IFF_RUNNING) == 0) 669 return; 670 printf("%s: device timeout, BMCtl = 0x%08x, BMSts = 0x%08x\n", 671 sc->sc_dev.dv_xname, EPE_READ(BMCtl), EPE_READ(BMSts)); 672 } 673 674 static int 675 epe_ifinit(struct ifnet *ifp) 676 { 677 struct epe_softc *sc = ifp->if_softc; 678 int rc, s = splnet(); 679 680 callout_stop(&sc->epe_tick_ch); 681 EPE_WRITE(RXCtl, RXCtl_IA0|RXCtl_BA|RXCtl_RCRCA|RXCtl_SRxON); 682 EPE_WRITE(TXCtl, TXCtl_STxON); 683 EPE_WRITE(GIIntMsk, GIIntMsk_INT); /* start interrupting */ 684 685 if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 686 rc = 0; 687 else if (rc != 0) 688 goto out; 689 690 callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc); 691 ifp->if_flags |= IFF_RUNNING; 692 out: 693 splx(s); 694 return 0; 695 } 696 697 static void 698 epe_ifstop(struct ifnet *ifp, int disable) 699 { 700 struct epe_softc *sc = ifp->if_softc; 701 702 703 EPE_WRITE(RXCtl, 0); 704 EPE_WRITE(TXCtl, 0); 705 EPE_WRITE(GIIntMsk, 0); 706 callout_stop(&sc->epe_tick_ch); 707 708 /* Down the MII. */ 709 mii_down(&sc->sc_mii); 710 711 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 712 ifp->if_timer = 0; 713 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 714 } 715 716 static void 717 epe_setaddr(struct ifnet *ifp) 718 { 719 struct epe_softc *sc = ifp->if_softc; 720 struct ethercom *ac = &sc->sc_ec; 721 struct ether_multi *enm; 722 struct ether_multistep step; 723 u_int8_t ias[2][ETHER_ADDR_LEN]; 724 u_int32_t h, nma = 0, hashes[2] = { 0, 0 }; 725 u_int32_t rxctl = EPE_READ(RXCtl); 726 727 /* disable receiver temporarily */ 728 EPE_WRITE(RXCtl, rxctl & ~RXCtl_SRxON); 729 730 rxctl &= ~(RXCtl_MA|RXCtl_PA|RXCtl_IA2|RXCtl_IA3); 731 732 if (ifp->if_flags & IFF_PROMISC) { 733 rxctl |= RXCtl_PA; 734 } 735 736 ifp->if_flags &= ~IFF_ALLMULTI; 737 738 ETHER_FIRST_MULTI(step, ac, enm); 739 while (enm != NULL) { 740 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 741 /* 742 * We must listen to a range of multicast addresses. 743 * For now, just accept all multicasts, rather than 744 * trying to set only those filter bits needed to match 745 * the range. (At this time, the only use of address 746 * ranges is for IP multicast routing, for which the 747 * range is big enough to require all bits set.) 748 */ 749 rxctl &= ~(RXCtl_IA2|RXCtl_IA3); 750 rxctl |= RXCtl_MA; 751 hashes[0] = 0xffffffffUL; 752 hashes[1] = 0xffffffffUL; 753 ifp->if_flags |= IFF_ALLMULTI; 754 break; 755 } 756 757 if (nma < 2) { 758 /* We can program 2 perfect address filters for mcast */ 759 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 760 rxctl |= (1 << (nma + 2)); 761 } else { 762 /* 763 * XXX: Datasheet is not very clear here, I'm not sure 764 * if I'm doing this right. --joff 765 */ 766 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 767 768 /* Just want the 6 most-significant bits. */ 769 h = h >> 26; 770 771 hashes[ h / 32 ] |= (1 << (h % 32)); 772 rxctl |= RXCtl_MA; 773 } 774 ETHER_NEXT_MULTI(step, enm); 775 nma++; 776 } 777 778 EPE_WRITE(AFP, 0); 779 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 780 sc->sc_enaddr, ETHER_ADDR_LEN); 781 if (rxctl & RXCtl_IA2) { 782 EPE_WRITE(AFP, 2); 783 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 784 ias[0], ETHER_ADDR_LEN); 785 } 786 if (rxctl & RXCtl_IA3) { 787 EPE_WRITE(AFP, 3); 788 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 789 ias[1], ETHER_ADDR_LEN); 790 } 791 if (hashes[0] != 0 && hashes[1] != 0) { 792 EPE_WRITE(AFP, 7); 793 EPE_WRITE(HashTbl, hashes[0]); 794 EPE_WRITE(HashTbl + 4, hashes[1]); 795 } 796 EPE_WRITE(RXCtl, rxctl); 797 } 798
Indexes created Tue Sep 30 11:09:46 GMT 2025