epe.c revision 1.26
1 /* $NetBSD: epe.c,v 1.26 2011/07/01 19:31:17 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Jesse Off 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: epe.c,v 1.26 2011/07/01 19:31:17 dyoung Exp $"); 31 32 #include <sys/types.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/ioctl.h> 36 #include <sys/kernel.h> 37 #include <sys/proc.h> 38 #include <sys/malloc.h> 39 #include <sys/time.h> 40 #include <sys/device.h> 41 #include <uvm/uvm_extern.h> 42 43 #include <sys/bus.h> 44 #include <machine/intr.h> 45 46 #include <arm/cpufunc.h> 47 48 #include <arm/ep93xx/epsocvar.h> 49 #include <arm/ep93xx/ep93xxvar.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_types.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #include <dev/mii/mii.h> 58 #include <dev/mii/miivar.h> 59 60 #ifdef INET 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/in_var.h> 64 #include <netinet/ip.h> 65 #include <netinet/if_inarp.h> 66 #endif 67 68 #ifdef NS 69 #include <netns/ns.h> 70 #include <netns/ns_if.h> 71 #endif 72 73 #include <net/bpf.h> 74 #include <net/bpfdesc.h> 75 76 #include <arm/ep93xx/ep93xxreg.h> 77 #include <arm/ep93xx/epereg.h> 78 #include <arm/ep93xx/epevar.h> 79 80 #define DEFAULT_MDCDIV 32 81 82 #ifndef EPE_FAST 83 #define EPE_FAST 84 #endif 85 86 #ifndef EPE_FAST 87 #define EPE_READ(x) \ 88 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x)) 89 #define EPE_WRITE(x, y) \ 90 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x), (y)) 91 #define CTRLPAGE_DMASYNC(x, y, z) \ 92 bus_dmamap_sync(sc->sc_dmat, sc->ctrlpage_dmamap, (x), (y), (z)) 93 #else 94 #define EPE_READ(x) *(volatile u_int32_t *) \ 95 (EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x)) 96 #define EPE_WRITE(x, y) *(volatile u_int32_t *) \ 97 (EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x)) = y 98 #define CTRLPAGE_DMASYNC(x, y, z) 99 #endif /* ! EPE_FAST */ 100 101 static int epe_match(struct device *, struct cfdata *, void *); 102 static void epe_attach(struct device *, struct device *, void *); 103 static void epe_init(struct epe_softc *); 104 static int epe_intr(void* arg); 105 static int epe_gctx(struct epe_softc *); 106 static int epe_mediachange(struct ifnet *); 107 int epe_mii_readreg (struct device *, int, int); 108 void epe_mii_writereg (struct device *, int, int, int); 109 void epe_statchg (struct device *); 110 void epe_tick (void *); 111 static int epe_ifioctl (struct ifnet *, u_long, void *); 112 static void epe_ifstart (struct ifnet *); 113 static void epe_ifwatchdog (struct ifnet *); 114 static int epe_ifinit (struct ifnet *); 115 static void epe_ifstop (struct ifnet *, int); 116 static void epe_setaddr (struct ifnet *); 117 118 CFATTACH_DECL(epe, sizeof(struct epe_softc), 119 epe_match, epe_attach, NULL, NULL); 120 121 static int 122 epe_match(struct device *parent, struct cfdata *match, void *aux) 123 { 124 return 2; 125 } 126 127 static void 128 epe_attach(struct device *parent, struct device *self, void *aux) 129 { 130 struct epe_softc *sc; 131 struct epsoc_attach_args *sa; 132 prop_data_t enaddr; 133 134 printf("\n"); 135 sc = (struct epe_softc*) self; 136 sa = aux; 137 sc->sc_iot = sa->sa_iot; 138 sc->sc_intr = sa->sa_intr; 139 sc->sc_dmat = sa->sa_dmat; 140 141 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 142 0, &sc->sc_ioh)) 143 panic("%s: Cannot map registers", self->dv_xname); 144 145 /* Fetch the Ethernet address from property if set. */ 146 enaddr = prop_dictionary_get(device_properties(self), "mac-address"); 147 if (enaddr != NULL) { 148 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 149 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 150 memcpy(sc->sc_enaddr, prop_data_data_nocopy(enaddr), 151 ETHER_ADDR_LEN); 152 bus_space_write_4(sc->sc_iot, sc->sc_ioh, EPE_AFP, 0); 153 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 154 sc->sc_enaddr, ETHER_ADDR_LEN); 155 } 156 157 ep93xx_intr_establish(sc->sc_intr, IPL_NET, epe_intr, sc); 158 epe_init(sc); 159 } 160 161 static int 162 epe_gctx(struct epe_softc *sc) 163 { 164 struct ifnet * ifp = &sc->sc_ec.ec_if; 165 u_int32_t *cur, ndq = 0; 166 167 /* Handle transmit completions */ 168 cur = (u_int32_t *)(EPE_READ(TXStsQCurAdd) - 169 sc->ctrlpage_dsaddr + (char*)sc->ctrlpage); 170 171 if (sc->TXStsQ_cur != cur) { 172 CTRLPAGE_DMASYNC(TX_QLEN * 2 * sizeof(u_int32_t), 173 TX_QLEN * sizeof(u_int32_t), BUS_DMASYNC_PREREAD); 174 } else { 175 return 0; 176 } 177 178 do { 179 u_int32_t tbi = *sc->TXStsQ_cur & 0x7fff; 180 struct mbuf *m = sc->txq[tbi].m; 181 182 if ((*sc->TXStsQ_cur & TXStsQ_TxWE) == 0) { 183 ifp->if_oerrors++; 184 } 185 bus_dmamap_unload(sc->sc_dmat, sc->txq[tbi].m_dmamap); 186 m_freem(m); 187 do { 188 sc->txq[tbi].m = NULL; 189 ndq++; 190 tbi = (tbi + 1) % TX_QLEN; 191 } while (sc->txq[tbi].m == m); 192 193 ifp->if_opackets++; 194 sc->TXStsQ_cur++; 195 if (sc->TXStsQ_cur >= sc->TXStsQ + TX_QLEN) { 196 sc->TXStsQ_cur = sc->TXStsQ; 197 } 198 } while (sc->TXStsQ_cur != cur); 199 200 sc->TXDQ_avail += ndq; 201 if (ifp->if_flags & IFF_OACTIVE) { 202 ifp->if_flags &= ~IFF_OACTIVE; 203 /* Disable end-of-tx-chain interrupt */ 204 EPE_WRITE(IntEn, IntEn_REOFIE); 205 } 206 return ndq; 207 } 208 209 static int 210 epe_intr(void *arg) 211 { 212 struct epe_softc *sc = (struct epe_softc *)arg; 213 struct ifnet * ifp = &sc->sc_ec.ec_if; 214 u_int32_t ndq = 0, irq, *cur; 215 216 irq = EPE_READ(IntStsC); 217 begin: 218 cur = (u_int32_t *)(EPE_READ(RXStsQCurAdd) - 219 sc->ctrlpage_dsaddr + (char*)sc->ctrlpage); 220 CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(u_int32_t), 221 RX_QLEN * 4 * sizeof(u_int32_t), 222 BUS_DMASYNC_PREREAD); 223 while (sc->RXStsQ_cur != cur) { 224 if ((sc->RXStsQ_cur[0] & (RXStsQ_RWE|RXStsQ_RFP|RXStsQ_EOB)) == 225 (RXStsQ_RWE|RXStsQ_RFP|RXStsQ_EOB)) { 226 u_int32_t bi = (sc->RXStsQ_cur[1] >> 16) & 0x7fff; 227 u_int32_t fl = sc->RXStsQ_cur[1] & 0xffff; 228 struct mbuf *m; 229 230 MGETHDR(m, M_DONTWAIT, MT_DATA); 231 if (m != NULL) MCLGET(m, M_DONTWAIT); 232 if (m != NULL && (m->m_flags & M_EXT)) { 233 bus_dmamap_unload(sc->sc_dmat, 234 sc->rxq[bi].m_dmamap); 235 sc->rxq[bi].m->m_pkthdr.rcvif = ifp; 236 sc->rxq[bi].m->m_pkthdr.len = 237 sc->rxq[bi].m->m_len = fl; 238 bpf_mtap(ifp, sc->rxq[bi].m); 239 (*ifp->if_input)(ifp, sc->rxq[bi].m); 240 sc->rxq[bi].m = m; 241 bus_dmamap_load(sc->sc_dmat, 242 sc->rxq[bi].m_dmamap, 243 m->m_ext.ext_buf, MCLBYTES, 244 NULL, BUS_DMA_NOWAIT); 245 sc->RXDQ[bi * 2] = 246 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr; 247 } else { 248 /* Drop packets until we can get replacement 249 * empty mbufs for the RXDQ. 250 */ 251 if (m != NULL) { 252 m_freem(m); 253 } 254 ifp->if_ierrors++; 255 } 256 } else { 257 ifp->if_ierrors++; 258 } 259 260 ndq++; 261 262 sc->RXStsQ_cur += 2; 263 if (sc->RXStsQ_cur >= sc->RXStsQ + (RX_QLEN * 2)) { 264 sc->RXStsQ_cur = sc->RXStsQ; 265 } 266 } 267 268 if (ndq > 0) { 269 ifp->if_ipackets += ndq; 270 CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(u_int32_t), 271 RX_QLEN * 4 * sizeof(u_int32_t), 272 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 273 EPE_WRITE(RXStsEnq, ndq); 274 EPE_WRITE(RXDEnq, ndq); 275 ndq = 0; 276 } 277 278 if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 279 epe_ifstart(ifp); 280 } 281 282 irq = EPE_READ(IntStsC); 283 if ((irq & (IntSts_RxSQ|IntSts_ECI)) != 0) 284 goto begin; 285 286 return (1); 287 } 288 289 290 static void 291 epe_init(struct epe_softc *sc) 292 { 293 bus_dma_segment_t segs; 294 char *addr; 295 int rsegs, err, i; 296 struct ifnet * ifp = &sc->sc_ec.ec_if; 297 int mdcdiv = DEFAULT_MDCDIV; 298 299 callout_init(&sc->epe_tick_ch, 0); 300 301 /* Select primary Individual Address in Address Filter Pointer */ 302 EPE_WRITE(AFP, 0); 303 /* Read ethernet MAC, should already be set by bootrom */ 304 bus_space_read_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 305 sc->sc_enaddr, ETHER_ADDR_LEN); 306 printf("%s: MAC address %s\n", sc->sc_dev.dv_xname, 307 ether_sprintf(sc->sc_enaddr)); 308 309 /* Soft Reset the MAC */ 310 EPE_WRITE(SelfCtl, SelfCtl_RESET); 311 while(EPE_READ(SelfCtl) & SelfCtl_RESET); 312 313 /* suggested magic initialization values from datasheet */ 314 EPE_WRITE(RXBufThrshld, 0x800040); 315 EPE_WRITE(TXBufThrshld, 0x200010); 316 EPE_WRITE(RXStsThrshld, 0x40002); 317 EPE_WRITE(TXStsThrshld, 0x40002); 318 EPE_WRITE(RXDThrshld, 0x40002); 319 EPE_WRITE(TXDThrshld, 0x40002); 320 321 /* Allocate a page of memory for descriptor and status queues */ 322 err = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, 0, PAGE_SIZE, 323 &segs, 1, &rsegs, BUS_DMA_WAITOK); 324 if (err == 0) { 325 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, PAGE_SIZE, 326 &sc->ctrlpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT)); 327 } 328 if (err == 0) { 329 err = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 330 0, BUS_DMA_WAITOK, &sc->ctrlpage_dmamap); 331 } 332 if (err == 0) { 333 err = bus_dmamap_load(sc->sc_dmat, sc->ctrlpage_dmamap, 334 sc->ctrlpage, PAGE_SIZE, NULL, BUS_DMA_WAITOK); 335 } 336 if (err != 0) { 337 panic("%s: Cannot get DMA memory", sc->sc_dev.dv_xname); 338 } 339 sc->ctrlpage_dsaddr = sc->ctrlpage_dmamap->dm_segs[0].ds_addr; 340 memset(sc->ctrlpage, 0, PAGE_SIZE); 341 342 /* Set up pointers to start of each queue in kernel addr space. 343 * Each descriptor queue or status queue entry uses 2 words 344 */ 345 sc->TXDQ = (u_int32_t *)sc->ctrlpage; 346 sc->TXDQ_cur = sc->TXDQ; 347 sc->TXDQ_avail = TX_QLEN - 1; 348 sc->TXStsQ = &sc->TXDQ[TX_QLEN * 2]; 349 sc->TXStsQ_cur = sc->TXStsQ; 350 sc->RXDQ = &sc->TXStsQ[TX_QLEN]; 351 sc->RXStsQ = &sc->RXDQ[RX_QLEN * 2]; 352 sc->RXStsQ_cur = sc->RXStsQ; 353 354 /* Program each queue's start addr, cur addr, and len registers 355 * with the physical addresses. 356 */ 357 addr = (char *)sc->ctrlpage_dmamap->dm_segs[0].ds_addr; 358 EPE_WRITE(TXDQBAdd, (u_int32_t)addr); 359 EPE_WRITE(TXDQCurAdd, (u_int32_t)addr); 360 EPE_WRITE(TXDQBLen, TX_QLEN * 2 * sizeof(u_int32_t)); 361 362 addr += (sc->TXStsQ - sc->TXDQ) * sizeof(u_int32_t); 363 EPE_WRITE(TXStsQBAdd, (u_int32_t)addr); 364 EPE_WRITE(TXStsQCurAdd, (u_int32_t)addr); 365 EPE_WRITE(TXStsQBLen, TX_QLEN * sizeof(u_int32_t)); 366 367 addr += (sc->RXDQ - sc->TXStsQ) * sizeof(u_int32_t); 368 EPE_WRITE(RXDQBAdd, (u_int32_t)addr); 369 EPE_WRITE(RXDCurAdd, (u_int32_t)addr); 370 EPE_WRITE(RXDQBLen, RX_QLEN * 2 * sizeof(u_int32_t)); 371 372 addr += (sc->RXStsQ - sc->RXDQ) * sizeof(u_int32_t); 373 EPE_WRITE(RXStsQBAdd, (u_int32_t)addr); 374 EPE_WRITE(RXStsQCurAdd, (u_int32_t)addr); 375 EPE_WRITE(RXStsQBLen, RX_QLEN * 2 * sizeof(u_int32_t)); 376 377 /* Populate the RXDQ with mbufs */ 378 for(i = 0; i < RX_QLEN; i++) { 379 struct mbuf *m; 380 381 bus_dmamap_create(sc->sc_dmat, MCLBYTES, TX_QLEN/4, MCLBYTES, 0, 382 BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 383 MGETHDR(m, M_WAIT, MT_DATA); 384 MCLGET(m, M_WAIT); 385 sc->rxq[i].m = m; 386 bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 387 m->m_ext.ext_buf, MCLBYTES, NULL, 388 BUS_DMA_WAITOK); 389 390 sc->RXDQ[i * 2] = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr; 391 sc->RXDQ[i * 2 + 1] = (i << 16) | MCLBYTES; 392 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 393 MCLBYTES, BUS_DMASYNC_PREREAD); 394 } 395 396 for(i = 0; i < TX_QLEN; i++) { 397 bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 398 (BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW), 399 &sc->txq[i].m_dmamap); 400 sc->txq[i].m = NULL; 401 sc->TXDQ[i * 2 + 1] = (i << 16); 402 } 403 404 /* Divide HCLK by 32 for MDC clock */ 405 if (device_cfdata(&sc->sc_dev)->cf_flags) 406 mdcdiv = device_cfdata(&sc->sc_dev)->cf_flags; 407 EPE_WRITE(SelfCtl, (SelfCtl_MDCDIV(mdcdiv)|SelfCtl_PSPRS)); 408 409 sc->sc_mii.mii_ifp = ifp; 410 sc->sc_mii.mii_readreg = epe_mii_readreg; 411 sc->sc_mii.mii_writereg = epe_mii_writereg; 412 sc->sc_mii.mii_statchg = epe_statchg; 413 sc->sc_ec.ec_mii = &sc->sc_mii; 414 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, epe_mediachange, 415 ether_mediastatus); 416 mii_attach((struct device *)sc, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 417 MII_OFFSET_ANY, 0); 418 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 419 420 EPE_WRITE(BMCtl, BMCtl_RxEn|BMCtl_TxEn); 421 EPE_WRITE(IntEn, IntEn_REOFIE); 422 /* maximum valid max frame length */ 423 EPE_WRITE(MaxFrmLen, (0x7ff << 16)|MHLEN); 424 /* wait for receiver ready */ 425 while((EPE_READ(BMSts) & BMSts_RxAct) == 0); 426 /* enqueue the entries in RXStsQ and RXDQ */ 427 CTRLPAGE_DMASYNC(0, sc->ctrlpage_dmamap->dm_mapsize, 428 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 429 EPE_WRITE(RXDEnq, RX_QLEN - 1); 430 EPE_WRITE(RXStsEnq, RX_QLEN - 1); 431 432 /* 433 * We can support 802.1Q VLAN-sized frames. 434 */ 435 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 436 437 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 438 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 439 ifp->if_ioctl = epe_ifioctl; 440 ifp->if_start = epe_ifstart; 441 ifp->if_watchdog = epe_ifwatchdog; 442 ifp->if_init = epe_ifinit; 443 ifp->if_stop = epe_ifstop; 444 ifp->if_timer = 0; 445 ifp->if_softc = sc; 446 IFQ_SET_READY(&ifp->if_snd); 447 if_attach(ifp); 448 ether_ifattach(ifp, (sc)->sc_enaddr); 449 } 450 451 static int 452 epe_mediachange(struct ifnet *ifp) 453 { 454 if (ifp->if_flags & IFF_UP) 455 epe_ifinit(ifp); 456 return (0); 457 } 458 459 int 460 epe_mii_readreg(struct device *self, int phy, int reg) 461 { 462 u_int32_t d, v; 463 struct epe_softc *sc; 464 465 sc = (struct epe_softc *)self; 466 d = EPE_READ(SelfCtl); 467 EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */ 468 EPE_WRITE(MIICmd, (MIICmd_READ | (phy << 5) | reg)); 469 while(EPE_READ(MIISts) & MIISts_BUSY); 470 v = EPE_READ(MIIData); 471 EPE_WRITE(SelfCtl, d); /* restore old value */ 472 return v; 473 } 474 475 void 476 epe_mii_writereg(struct device *self, int phy, int reg, int val) 477 { 478 struct epe_softc *sc; 479 u_int32_t d; 480 481 sc = (struct epe_softc *)self; 482 d = EPE_READ(SelfCtl); 483 EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */ 484 EPE_WRITE(MIIData, val); 485 EPE_WRITE(MIICmd, (MIICmd_WRITE | (phy << 5) | reg)); 486 while(EPE_READ(MIISts) & MIISts_BUSY); 487 EPE_WRITE(SelfCtl, d); /* restore old value */ 488 } 489 490 491 void 492 epe_statchg(struct device *self) 493 { 494 struct epe_softc *sc = (struct epe_softc *)self; 495 u_int32_t reg; 496 497 /* 498 * We must keep the MAC and the PHY in sync as 499 * to the status of full-duplex! 500 */ 501 reg = EPE_READ(TestCtl); 502 if (sc->sc_mii.mii_media_active & IFM_FDX) 503 reg |= TestCtl_MFDX; 504 else 505 reg &= ~TestCtl_MFDX; 506 EPE_WRITE(TestCtl, reg); 507 } 508 509 void 510 epe_tick(void *arg) 511 { 512 struct epe_softc* sc = (struct epe_softc *)arg; 513 struct ifnet * ifp = &sc->sc_ec.ec_if; 514 int s; 515 u_int32_t misses; 516 517 ifp->if_collisions += EPE_READ(TXCollCnt); 518 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 519 misses = EPE_READ(RXMissCnt); 520 if (misses > 0) 521 printf("%s: %d rx misses\n", sc->sc_dev.dv_xname, misses); 522 523 s = splnet(); 524 if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 525 epe_ifstart(ifp); 526 } 527 splx(s); 528 529 mii_tick(&sc->sc_mii); 530 callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc); 531 } 532 533 534 static int 535 epe_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 536 { 537 int s, error; 538 539 s = splnet(); 540 error = ether_ioctl(ifp, cmd, data); 541 if (error == ENETRESET) { 542 if (ifp->if_flags & IFF_RUNNING) 543 epe_setaddr(ifp); 544 error = 0; 545 } 546 splx(s); 547 return error; 548 } 549 550 static void 551 epe_ifstart(struct ifnet *ifp) 552 { 553 struct epe_softc *sc = (struct epe_softc *)ifp->if_softc; 554 struct mbuf *m; 555 bus_dma_segment_t *segs; 556 int s, bi, err, nsegs, ndq; 557 558 s = splnet(); 559 start: 560 ndq = 0; 561 if (sc->TXDQ_avail == 0) { 562 if (epe_gctx(sc) == 0) { 563 /* Enable End-Of-TX-Chain interrupt */ 564 EPE_WRITE(IntEn, IntEn_REOFIE|IntEn_ECIE); 565 ifp->if_flags |= IFF_OACTIVE; 566 ifp->if_timer = 10; 567 splx(s); 568 return; 569 } 570 } 571 572 bi = sc->TXDQ_cur - sc->TXDQ; 573 574 IFQ_POLL(&ifp->if_snd, m); 575 if (m == NULL) { 576 splx(s); 577 return; 578 } 579 more: 580 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 581 BUS_DMA_NOWAIT)) || 582 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 583 sc->txq[bi].m_dmamap->dm_nsegs > (sc->TXDQ_avail - ndq)) { 584 /* Copy entire mbuf chain to new and 32-bit aligned storage */ 585 struct mbuf *mn; 586 587 if (err == 0) 588 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 589 590 MGETHDR(mn, M_DONTWAIT, MT_DATA); 591 if (mn == NULL) goto stop; 592 if (m->m_pkthdr.len > (MHLEN & (~0x3))) { 593 MCLGET(mn, M_DONTWAIT); 594 if ((mn->m_flags & M_EXT) == 0) { 595 m_freem(mn); 596 goto stop; 597 } 598 } 599 mn->m_data = (void *)(((u_int32_t)mn->m_data + 0x3) & (~0x3)); 600 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 601 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 602 IFQ_DEQUEUE(&ifp->if_snd, m); 603 m_freem(m); 604 m = mn; 605 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 606 BUS_DMA_NOWAIT); 607 } else { 608 IFQ_DEQUEUE(&ifp->if_snd, m); 609 } 610 611 bpf_mtap(ifp, m); 612 613 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 614 segs = sc->txq[bi].m_dmamap->dm_segs; 615 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 616 sc->txq[bi].m_dmamap->dm_mapsize, 617 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 618 619 /* XXX: This driver hasn't been tested w/nsegs > 1 */ 620 while (nsegs > 0) { 621 nsegs--; 622 sc->txq[bi].m = m; 623 sc->TXDQ[bi * 2] = segs->ds_addr; 624 if (nsegs == 0) 625 sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16) | 626 (1 << 31); 627 else 628 sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16); 629 segs++; 630 bi = (bi + 1) % TX_QLEN; 631 ndq++; 632 } 633 634 635 /* 636 * Enqueue another. Don't do more than half the available 637 * descriptors before telling the MAC about them 638 */ 639 if ((sc->TXDQ_avail - ndq) > 0 && ndq < TX_QLEN / 2) { 640 IFQ_POLL(&ifp->if_snd, m); 641 if (m != NULL) { 642 goto more; 643 } 644 } 645 stop: 646 if (ndq > 0) { 647 sc->TXDQ_avail -= ndq; 648 sc->TXDQ_cur = &sc->TXDQ[bi]; 649 CTRLPAGE_DMASYNC(0, TX_QLEN * 2 * sizeof(u_int32_t), 650 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 651 EPE_WRITE(TXDEnq, ndq); 652 } 653 654 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 655 goto start; 656 657 splx(s); 658 return; 659 } 660 661 static void 662 epe_ifwatchdog(struct ifnet *ifp) 663 { 664 struct epe_softc *sc = (struct epe_softc *)ifp->if_softc; 665 666 if ((ifp->if_flags & IFF_RUNNING) == 0) 667 return; 668 printf("%s: device timeout, BMCtl = 0x%08x, BMSts = 0x%08x\n", 669 sc->sc_dev.dv_xname, EPE_READ(BMCtl), EPE_READ(BMSts)); 670 } 671 672 static int 673 epe_ifinit(struct ifnet *ifp) 674 { 675 struct epe_softc *sc = ifp->if_softc; 676 int rc, s = splnet(); 677 678 callout_stop(&sc->epe_tick_ch); 679 EPE_WRITE(RXCtl, RXCtl_IA0|RXCtl_BA|RXCtl_RCRCA|RXCtl_SRxON); 680 EPE_WRITE(TXCtl, TXCtl_STxON); 681 EPE_WRITE(GIIntMsk, GIIntMsk_INT); /* start interrupting */ 682 683 if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 684 rc = 0; 685 else if (rc != 0) 686 goto out; 687 688 callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc); 689 ifp->if_flags |= IFF_RUNNING; 690 out: 691 splx(s); 692 return 0; 693 } 694 695 static void 696 epe_ifstop(struct ifnet *ifp, int disable) 697 { 698 struct epe_softc *sc = ifp->if_softc; 699 700 701 EPE_WRITE(RXCtl, 0); 702 EPE_WRITE(TXCtl, 0); 703 EPE_WRITE(GIIntMsk, 0); 704 callout_stop(&sc->epe_tick_ch); 705 706 /* Down the MII. */ 707 mii_down(&sc->sc_mii); 708 709 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 710 ifp->if_timer = 0; 711 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 712 } 713 714 static void 715 epe_setaddr(struct ifnet *ifp) 716 { 717 struct epe_softc *sc = ifp->if_softc; 718 struct ethercom *ac = &sc->sc_ec; 719 struct ether_multi *enm; 720 struct ether_multistep step; 721 u_int8_t ias[2][ETHER_ADDR_LEN]; 722 u_int32_t h, nma = 0, hashes[2] = { 0, 0 }; 723 u_int32_t rxctl = EPE_READ(RXCtl); 724 725 /* disable receiver temporarily */ 726 EPE_WRITE(RXCtl, rxctl & ~RXCtl_SRxON); 727 728 rxctl &= ~(RXCtl_MA|RXCtl_PA|RXCtl_IA2|RXCtl_IA3); 729 730 if (ifp->if_flags & IFF_PROMISC) { 731 rxctl |= RXCtl_PA; 732 } 733 734 ifp->if_flags &= ~IFF_ALLMULTI; 735 736 ETHER_FIRST_MULTI(step, ac, enm); 737 while (enm != NULL) { 738 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 739 /* 740 * We must listen to a range of multicast addresses. 741 * For now, just accept all multicasts, rather than 742 * trying to set only those filter bits needed to match 743 * the range. (At this time, the only use of address 744 * ranges is for IP multicast routing, for which the 745 * range is big enough to require all bits set.) 746 */ 747 rxctl &= ~(RXCtl_IA2|RXCtl_IA3); 748 rxctl |= RXCtl_MA; 749 hashes[0] = 0xffffffffUL; 750 hashes[1] = 0xffffffffUL; 751 ifp->if_flags |= IFF_ALLMULTI; 752 break; 753 } 754 755 if (nma < 2) { 756 /* We can program 2 perfect address filters for mcast */ 757 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 758 rxctl |= (1 << (nma + 2)); 759 } else { 760 /* 761 * XXX: Datasheet is not very clear here, I'm not sure 762 * if I'm doing this right. --joff 763 */ 764 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 765 766 /* Just want the 6 most-significant bits. */ 767 h = h >> 26; 768 769 hashes[ h / 32 ] |= (1 << (h % 32)); 770 rxctl |= RXCtl_MA; 771 } 772 ETHER_NEXT_MULTI(step, enm); 773 nma++; 774 } 775 776 EPE_WRITE(AFP, 0); 777 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 778 sc->sc_enaddr, ETHER_ADDR_LEN); 779 if (rxctl & RXCtl_IA2) { 780 EPE_WRITE(AFP, 2); 781 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 782 ias[0], ETHER_ADDR_LEN); 783 } 784 if (rxctl & RXCtl_IA3) { 785 EPE_WRITE(AFP, 3); 786 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 787 ias[1], ETHER_ADDR_LEN); 788 } 789 if (hashes[0] != 0 && hashes[1] != 0) { 790 EPE_WRITE(AFP, 7); 791 EPE_WRITE(HashTbl, hashes[0]); 792 EPE_WRITE(HashTbl + 4, hashes[1]); 793 } 794 EPE_WRITE(RXCtl, rxctl); 795 } 796
Indexes created Tue Sep 30 11:09:46 GMT 2025