epe.c revision 1.3
1 /* $NetBSD: epe.c,v 1.3 2005/10/19 14:01:49 hamajima Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Jesse Off 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: epe.c,v 1.3 2005/10/19 14:01:49 hamajima Exp $"); 38 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/ioctl.h> 43 #include <sys/kernel.h> 44 #include <sys/proc.h> 45 #include <sys/malloc.h> 46 #include <sys/time.h> 47 #include <sys/device.h> 48 #include <uvm/uvm_extern.h> 49 50 #include <machine/bus.h> 51 #include <machine/intr.h> 52 53 #include <arm/cpufunc.h> 54 55 #include <arm/ep93xx/epsocvar.h> 56 #include <arm/ep93xx/ep93xxvar.h> 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_types.h> 61 #include <net/if_media.h> 62 #include <net/if_ether.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #ifdef INET 68 #include <netinet/in.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/in_var.h> 71 #include <netinet/ip.h> 72 #include <netinet/if_inarp.h> 73 #endif 74 75 #ifdef NS 76 #include <netns/ns.h> 77 #include <netns/ns_if.h> 78 #endif 79 80 #include "bpfilter.h" 81 #if NBPFILTER > 0 82 #include <net/bpf.h> 83 #include <net/bpfdesc.h> 84 #endif 85 86 #include <machine/bus.h> 87 88 #ifdef IPKDB_EP93XX 89 #include <ipkdb/ipkdb.h> 90 #endif 91 92 #include <arm/ep93xx/ep93xxreg.h> 93 #include <arm/ep93xx/epereg.h> 94 #include <arm/ep93xx/epevar.h> 95 96 #ifndef EPE_FAST 97 #define EPE_FAST 98 #endif 99 100 #ifndef EPE_FAST 101 #define EPE_READ(x) \ 102 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x)) 103 #define EPE_WRITE(x, y) \ 104 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x), (y)) 105 #define CTRLPAGE_DMASYNC(x, y, z) \ 106 bus_dmamap_sync(sc->sc_dmat, sc->ctrlpage_dmamap, (x), (y), (z)) 107 #else 108 #define EPE_READ(x) *(__volatile u_int32_t *) \ 109 (EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x)) 110 #define EPE_WRITE(x, y) *(__volatile u_int32_t *) \ 111 (EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x)) = y 112 #define CTRLPAGE_DMASYNC(x, y, z) 113 #endif /* ! EPE_FAST */ 114 115 static int epe_match(struct device *, struct cfdata *, void *); 116 static void epe_attach(struct device *, struct device *, void *); 117 static void epe_init(struct epe_softc *); 118 static int epe_intr(void* arg); 119 static int epe_gctx(struct epe_softc *); 120 static int epe_mediachange(struct ifnet *); 121 static void epe_mediastatus(struct ifnet *, struct ifmediareq *); 122 int epe_mii_readreg (struct device *, int, int); 123 void epe_mii_writereg (struct device *, int, int, int); 124 void epe_statchg (struct device *); 125 void epe_tick (void *); 126 static int epe_ifioctl (struct ifnet *, u_long, caddr_t); 127 static void epe_ifstart (struct ifnet *); 128 static void epe_ifwatchdog (struct ifnet *); 129 static int epe_ifinit (struct ifnet *); 130 static void epe_ifstop (struct ifnet *, int); 131 static void epe_setaddr (struct ifnet *); 132 133 CFATTACH_DECL(epe, sizeof(struct epe_softc), 134 epe_match, epe_attach, NULL, NULL); 135 136 static int 137 epe_match(struct device *parent, struct cfdata *match, void *aux) 138 { 139 return 2; 140 } 141 142 static void 143 epe_attach(struct device *parent, struct device *self, void *aux) 144 { 145 struct epe_softc *sc; 146 struct epsoc_attach_args *sa; 147 148 printf("\n"); 149 sc = (struct epe_softc*) self; 150 sa = aux; 151 sc->sc_iot = sa->sa_iot; 152 sc->sc_intr = sa->sa_intr; 153 sc->sc_dmat = sa->sa_dmat; 154 155 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 156 0, &sc->sc_ioh)) 157 panic("%s: Cannot map registers", self->dv_xname); 158 159 ep93xx_intr_establish(sc->sc_intr, IPL_NET, epe_intr, sc); 160 epe_init(sc); 161 } 162 163 static int 164 epe_gctx(struct epe_softc *sc) 165 { 166 struct ifnet * ifp = &sc->sc_ec.ec_if; 167 u_int32_t *cur, ndq = 0; 168 169 /* Handle transmit completions */ 170 cur = (u_int32_t *)(EPE_READ(TXStsQCurAdd) - 171 sc->ctrlpage_dsaddr + sc->ctrlpage); 172 173 if (sc->TXStsQ_cur != cur) { 174 CTRLPAGE_DMASYNC(TX_QLEN * 2 * sizeof(u_int32_t), 175 TX_QLEN * sizeof(u_int32_t), BUS_DMASYNC_PREREAD); 176 } else { 177 return 0; 178 } 179 180 do { 181 u_int32_t tbi = *sc->TXStsQ_cur & 0x7fff; 182 struct mbuf *m = sc->txq[tbi].m; 183 184 if ((*sc->TXStsQ_cur & TXStsQ_TxWE) == 0) { 185 ifp->if_oerrors++; 186 } 187 bus_dmamap_unload(sc->sc_dmat, sc->txq[tbi].m_dmamap); 188 m_freem(m); 189 do { 190 sc->txq[tbi].m = NULL; 191 ndq++; 192 tbi = (tbi + 1) % TX_QLEN; 193 } while (sc->txq[tbi].m == m); 194 195 ifp->if_opackets++; 196 sc->TXStsQ_cur++; 197 if (sc->TXStsQ_cur >= sc->TXStsQ + TX_QLEN) { 198 sc->TXStsQ_cur = sc->TXStsQ; 199 } 200 } while (sc->TXStsQ_cur != cur); 201 202 sc->TXDQ_avail += ndq; 203 if (ifp->if_flags & IFF_OACTIVE) { 204 ifp->if_flags &= ~IFF_OACTIVE; 205 /* Disable end-of-tx-chain interrupt */ 206 EPE_WRITE(IntEn, IntEn_REOFIE); 207 } 208 return ndq; 209 } 210 211 static int 212 epe_intr(void *arg) 213 { 214 struct epe_softc *sc = (struct epe_softc *)arg; 215 struct ifnet * ifp = &sc->sc_ec.ec_if; 216 u_int32_t ndq = 0, irq, *cur; 217 218 irq = EPE_READ(IntStsC); 219 begin: 220 cur = (u_int32_t *)(EPE_READ(RXStsQCurAdd) - 221 sc->ctrlpage_dsaddr + sc->ctrlpage); 222 CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(u_int32_t), 223 RX_QLEN * 4 * sizeof(u_int32_t), 224 BUS_DMASYNC_PREREAD); 225 while (sc->RXStsQ_cur != cur) { 226 if ((sc->RXStsQ_cur[0] & (RXStsQ_RWE|RXStsQ_RFP|RXStsQ_EOB)) == 227 (RXStsQ_RWE|RXStsQ_RFP|RXStsQ_EOB)) { 228 u_int32_t bi = (sc->RXStsQ_cur[1] >> 16) & 0x7fff; 229 u_int32_t fl = sc->RXStsQ_cur[1] & 0xffff; 230 struct mbuf *m; 231 232 MGETHDR(m, M_DONTWAIT, MT_DATA); 233 if (m != NULL) MCLGET(m, M_DONTWAIT); 234 if (m != NULL && (m->m_flags & M_EXT)) { 235 bus_dmamap_unload(sc->sc_dmat, 236 sc->rxq[bi].m_dmamap); 237 sc->rxq[bi].m->m_pkthdr.rcvif = ifp; 238 sc->rxq[bi].m->m_pkthdr.len = 239 sc->rxq[bi].m->m_len = fl; 240 #if NBPFILTER > 0 241 if (ifp->if_bpf) 242 bpf_mtap(ifp->if_bpf, sc->rxq[bi].m); 243 #endif /* NBPFILTER > 0 */ 244 (*ifp->if_input)(ifp, sc->rxq[bi].m); 245 sc->rxq[bi].m = m; 246 bus_dmamap_load(sc->sc_dmat, 247 sc->rxq[bi].m_dmamap, 248 m->m_ext.ext_buf, MCLBYTES, 249 NULL, BUS_DMA_NOWAIT); 250 sc->RXDQ[bi * 2] = 251 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr; 252 } else { 253 /* Drop packets until we can get replacement 254 * empty mbufs for the RXDQ. 255 */ 256 if (m != NULL) { 257 m_freem(m); 258 } 259 ifp->if_ierrors++; 260 } 261 } else { 262 ifp->if_ierrors++; 263 } 264 265 ndq++; 266 267 sc->RXStsQ_cur += 2; 268 if (sc->RXStsQ_cur >= sc->RXStsQ + (RX_QLEN * 2)) { 269 sc->RXStsQ_cur = sc->RXStsQ; 270 } 271 } 272 273 if (ndq > 0) { 274 ifp->if_ipackets += ndq; 275 CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(u_int32_t), 276 RX_QLEN * 4 * sizeof(u_int32_t), 277 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 278 EPE_WRITE(RXStsEnq, ndq); 279 EPE_WRITE(RXDEnq, ndq); 280 ndq = 0; 281 } 282 283 if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 284 epe_ifstart(ifp); 285 } 286 287 irq = EPE_READ(IntStsC); 288 if ((irq & (IntSts_RxSQ|IntSts_ECI)) != 0) 289 goto begin; 290 291 return (1); 292 } 293 294 295 static void 296 epe_init(struct epe_softc *sc) 297 { 298 bus_dma_segment_t segs; 299 caddr_t addr; 300 int rsegs, err, i; 301 struct ifnet * ifp = &sc->sc_ec.ec_if; 302 303 callout_init(&sc->epe_tick_ch); 304 305 /* Select primary Individual Address in Address Filter Pointer */ 306 EPE_WRITE(AFP, 0); 307 /* Read ethernet MAC, should already be set by bootrom */ 308 bus_space_read_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 309 sc->sc_enaddr, ETHER_ADDR_LEN); 310 printf("%s: MAC address %s\n", sc->sc_dev.dv_xname, 311 ether_sprintf(sc->sc_enaddr)); 312 313 /* Soft Reset the MAC */ 314 EPE_WRITE(SelfCtl, SelfCtl_RESET); 315 while(EPE_READ(SelfCtl) & SelfCtl_RESET); 316 317 /* suggested magic initialization values from datasheet */ 318 EPE_WRITE(RXBufThrshld, 0x800040); 319 EPE_WRITE(TXBufThrshld, 0x200010); 320 EPE_WRITE(RXStsThrshld, 0x40002); 321 EPE_WRITE(TXStsThrshld, 0x40002); 322 EPE_WRITE(RXDThrshld, 0x40002); 323 EPE_WRITE(TXDThrshld, 0x40002); 324 325 /* Allocate a page of memory for descriptor and status queues */ 326 err = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, 0, PAGE_SIZE, 327 &segs, 1, &rsegs, BUS_DMA_WAITOK); 328 if (err == 0) { 329 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, PAGE_SIZE, 330 &sc->ctrlpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT)); 331 } 332 if (err == 0) { 333 err = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 334 0, BUS_DMA_WAITOK, &sc->ctrlpage_dmamap); 335 } 336 if (err == 0) { 337 err = bus_dmamap_load(sc->sc_dmat, sc->ctrlpage_dmamap, 338 sc->ctrlpage, PAGE_SIZE, NULL, BUS_DMA_WAITOK); 339 } 340 if (err != 0) { 341 panic("%s: Cannot get DMA memory", sc->sc_dev.dv_xname); 342 } 343 sc->ctrlpage_dsaddr = sc->ctrlpage_dmamap->dm_segs[0].ds_addr; 344 bzero(sc->ctrlpage, PAGE_SIZE); 345 346 /* Set up pointers to start of each queue in kernel addr space. 347 * Each descriptor queue or status queue entry uses 2 words 348 */ 349 sc->TXDQ = (u_int32_t *)sc->ctrlpage; 350 sc->TXDQ_cur = sc->TXDQ; 351 sc->TXDQ_avail = TX_QLEN - 1; 352 sc->TXStsQ = &sc->TXDQ[TX_QLEN * 2]; 353 sc->TXStsQ_cur = sc->TXStsQ; 354 sc->RXDQ = &sc->TXStsQ[TX_QLEN]; 355 sc->RXStsQ = &sc->RXDQ[RX_QLEN * 2]; 356 sc->RXStsQ_cur = sc->RXStsQ; 357 358 /* Program each queue's start addr, cur addr, and len registers 359 * with the physical addresses. 360 */ 361 addr = (caddr_t)sc->ctrlpage_dmamap->dm_segs[0].ds_addr; 362 EPE_WRITE(TXDQBAdd, (u_int32_t)addr); 363 EPE_WRITE(TXDQCurAdd, (u_int32_t)addr); 364 EPE_WRITE(TXDQBLen, TX_QLEN * 2 * sizeof(u_int32_t)); 365 366 addr += (sc->TXStsQ - sc->TXDQ) * sizeof(u_int32_t); 367 EPE_WRITE(TXStsQBAdd, (u_int32_t)addr); 368 EPE_WRITE(TXStsQCurAdd, (u_int32_t)addr); 369 EPE_WRITE(TXStsQBLen, TX_QLEN * sizeof(u_int32_t)); 370 371 addr += (sc->RXDQ - sc->TXStsQ) * sizeof(u_int32_t); 372 EPE_WRITE(RXDQBAdd, (u_int32_t)addr); 373 EPE_WRITE(RXDCurAdd, (u_int32_t)addr); 374 EPE_WRITE(RXDQBLen, RX_QLEN * 2 * sizeof(u_int32_t)); 375 376 addr += (sc->RXStsQ - sc->RXDQ) * sizeof(u_int32_t); 377 EPE_WRITE(RXStsQBAdd, (u_int32_t)addr); 378 EPE_WRITE(RXStsQCurAdd, (u_int32_t)addr); 379 EPE_WRITE(RXStsQBLen, RX_QLEN * 2 * sizeof(u_int32_t)); 380 381 /* Populate the RXDQ with mbufs */ 382 for(i = 0; i < RX_QLEN; i++) { 383 struct mbuf *m; 384 385 bus_dmamap_create(sc->sc_dmat, MCLBYTES, TX_QLEN/4, MCLBYTES, 0, 386 BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 387 MGETHDR(m, M_WAIT, MT_DATA); 388 MCLGET(m, M_WAIT); 389 sc->rxq[i].m = m; 390 bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 391 m->m_ext.ext_buf, MCLBYTES, NULL, 392 BUS_DMA_WAITOK); 393 394 sc->RXDQ[i * 2] = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr; 395 sc->RXDQ[i * 2 + 1] = (i << 16) | MCLBYTES; 396 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 397 MCLBYTES, BUS_DMASYNC_PREREAD); 398 } 399 400 for(i = 0; i < TX_QLEN; i++) { 401 bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 402 (BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW), 403 &sc->txq[i].m_dmamap); 404 sc->txq[i].m = NULL; 405 sc->TXDQ[i * 2 + 1] = (i << 16); 406 } 407 408 /* Divide HCLK by 32 for MDC clock */ 409 EPE_WRITE(SelfCtl, (SelfCtl_MDCDIV(32)|SelfCtl_PSPRS)); 410 411 sc->sc_mii.mii_ifp = ifp; 412 sc->sc_mii.mii_readreg = epe_mii_readreg; 413 sc->sc_mii.mii_writereg = epe_mii_writereg; 414 sc->sc_mii.mii_statchg = epe_statchg; 415 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, epe_mediachange, 416 epe_mediastatus); 417 mii_attach((struct device *)sc, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 418 MII_OFFSET_ANY, 0); 419 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 420 421 EPE_WRITE(BMCtl, BMCtl_RxEn|BMCtl_TxEn); 422 EPE_WRITE(IntEn, IntEn_REOFIE); 423 /* maximum valid max frame length */ 424 EPE_WRITE(MaxFrmLen, (0x7ff << 16)|MHLEN); 425 /* wait for receiver ready */ 426 while((EPE_READ(BMSts) & BMSts_RxAct) == 0); 427 /* enqueue the entries in RXStsQ and RXDQ */ 428 CTRLPAGE_DMASYNC(0, sc->ctrlpage_dmamap->dm_mapsize, 429 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 430 EPE_WRITE(RXDEnq, RX_QLEN - 1); 431 EPE_WRITE(RXStsEnq, RX_QLEN - 1); 432 433 /* 434 * We can support 802.1Q VLAN-sized frames. 435 */ 436 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 437 438 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 439 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 440 ifp->if_ioctl = epe_ifioctl; 441 ifp->if_start = epe_ifstart; 442 ifp->if_watchdog = epe_ifwatchdog; 443 ifp->if_init = epe_ifinit; 444 ifp->if_stop = epe_ifstop; 445 ifp->if_timer = 0; 446 ifp->if_softc = sc; 447 IFQ_SET_READY(&ifp->if_snd); 448 if_attach(ifp); 449 ether_ifattach(ifp, (sc)->sc_enaddr); 450 } 451 452 static int 453 epe_mediachange(ifp) 454 struct ifnet *ifp; 455 { 456 if (ifp->if_flags & IFF_UP) 457 epe_ifinit(ifp); 458 return (0); 459 } 460 461 static void 462 epe_mediastatus(ifp, ifmr) 463 struct ifnet *ifp; 464 struct ifmediareq *ifmr; 465 { 466 struct epe_softc *sc = ifp->if_softc; 467 468 mii_pollstat(&sc->sc_mii); 469 ifmr->ifm_active = sc->sc_mii.mii_media_active; 470 ifmr->ifm_status = sc->sc_mii.mii_media_status; 471 } 472 473 474 int 475 epe_mii_readreg(self, phy, reg) 476 struct device *self; 477 int phy, reg; 478 { 479 u_int32_t d, v; 480 struct epe_softc *sc; 481 482 sc = (struct epe_softc *)self; 483 d = EPE_READ(SelfCtl); 484 EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */ 485 EPE_WRITE(MIICmd, (MIICmd_READ | (phy << 5) | reg)); 486 while(EPE_READ(MIISts) & MIISts_BUSY); 487 v = EPE_READ(MIIData); 488 EPE_WRITE(SelfCtl, d); /* restore old value */ 489 return v; 490 } 491 492 void 493 epe_mii_writereg(self, phy, reg, val) 494 struct device *self; 495 int phy, reg, val; 496 { 497 struct epe_softc *sc; 498 u_int32_t d; 499 500 sc = (struct epe_softc *)self; 501 d = EPE_READ(SelfCtl); 502 EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */ 503 EPE_WRITE(MIIData, val); 504 EPE_WRITE(MIICmd, (MIICmd_WRITE | (phy << 5) | reg)); 505 while(EPE_READ(MIISts) & MIISts_BUSY); 506 EPE_WRITE(SelfCtl, d); /* restore old value */ 507 } 508 509 510 void 511 epe_statchg(self) 512 struct device *self; 513 { 514 struct epe_softc *sc = (struct epe_softc *)self; 515 u_int32_t reg; 516 517 /* 518 * We must keep the MAC and the PHY in sync as 519 * to the status of full-duplex! 520 */ 521 reg = EPE_READ(TestCtl); 522 if (sc->sc_mii.mii_media_active & IFM_FDX) 523 reg |= TestCtl_MFDX; 524 else 525 reg &= ~TestCtl_MFDX; 526 EPE_WRITE(TestCtl, reg); 527 } 528 529 void 530 epe_tick(arg) 531 void *arg; 532 { 533 struct epe_softc* sc = (struct epe_softc *)arg; 534 struct ifnet * ifp = &sc->sc_ec.ec_if; 535 int s; 536 u_int32_t misses; 537 538 ifp->if_collisions += EPE_READ(TXCollCnt); 539 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 540 misses = EPE_READ(RXMissCnt); 541 if (misses > 0) 542 printf("%s: %d rx misses\n", sc->sc_dev.dv_xname, misses); 543 544 s = splnet(); 545 if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 546 epe_ifstart(ifp); 547 } 548 splx(s); 549 550 mii_tick(&sc->sc_mii); 551 callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc); 552 } 553 554 555 static int 556 epe_ifioctl(ifp, cmd, data) 557 struct ifnet *ifp; 558 u_long cmd; 559 caddr_t data; 560 { 561 struct epe_softc *sc = ifp->if_softc; 562 struct ifreq *ifr = (struct ifreq *)data; 563 int s, error; 564 565 s = splnet(); 566 switch(cmd) { 567 case SIOCSIFMEDIA: 568 case SIOCGIFMEDIA: 569 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 570 break; 571 default: 572 error = ether_ioctl(ifp, cmd, data); 573 if (error == ENETRESET) { 574 if (ifp->if_flags & IFF_RUNNING) 575 epe_setaddr(ifp); 576 error = 0; 577 } 578 } 579 splx(s); 580 return error; 581 } 582 583 static void 584 epe_ifstart(ifp) 585 struct ifnet *ifp; 586 { 587 struct epe_softc *sc = (struct epe_softc *)ifp->if_softc; 588 struct mbuf *m; 589 bus_dma_segment_t *segs; 590 int s, bi, err, nsegs, ndq; 591 592 s = splnet(); 593 start: 594 ndq = 0; 595 if (sc->TXDQ_avail == 0) { 596 if (epe_gctx(sc) == 0) { 597 /* Enable End-Of-TX-Chain interrupt */ 598 EPE_WRITE(IntEn, IntEn_REOFIE|IntEn_ECIE); 599 ifp->if_flags |= IFF_OACTIVE; 600 ifp->if_timer = 10; 601 splx(s); 602 return; 603 } 604 } 605 606 bi = sc->TXDQ_cur - sc->TXDQ; 607 608 IFQ_POLL(&ifp->if_snd, m); 609 if (m == NULL) { 610 splx(s); 611 return; 612 } 613 more: 614 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 615 BUS_DMA_NOWAIT)) || 616 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 617 sc->txq[bi].m_dmamap->dm_nsegs > (sc->TXDQ_avail - ndq)) { 618 /* Copy entire mbuf chain to new and 32-bit aligned storage */ 619 struct mbuf *mn; 620 621 if (err == 0) 622 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 623 624 MGETHDR(mn, M_DONTWAIT, MT_DATA); 625 if (mn == NULL) goto stop; 626 if (m->m_pkthdr.len > (MHLEN & (~0x3))) { 627 MCLGET(mn, M_DONTWAIT); 628 if ((mn->m_flags & M_EXT) == 0) { 629 m_freem(mn); 630 goto stop; 631 } 632 } 633 mn->m_data = (caddr_t)(((u_int32_t)mn->m_data + 0x3) & (~0x3)); 634 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, caddr_t)); 635 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 636 IFQ_DEQUEUE(&ifp->if_snd, m); 637 m_freem(m); 638 m = mn; 639 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 640 BUS_DMA_NOWAIT); 641 } else { 642 IFQ_DEQUEUE(&ifp->if_snd, m); 643 } 644 645 #if NBPFILTER > 0 646 if (ifp->if_bpf) 647 bpf_mtap(ifp->if_bpf, m); 648 #endif /* NBPFILTER > 0 */ 649 650 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 651 segs = sc->txq[bi].m_dmamap->dm_segs; 652 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 653 sc->txq[bi].m_dmamap->dm_mapsize, 654 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 655 656 /* XXX: This driver hasn't been tested w/nsegs > 1 */ 657 while (nsegs > 0) { 658 nsegs--; 659 sc->txq[bi].m = m; 660 sc->TXDQ[bi * 2] = segs->ds_addr; 661 if (nsegs == 0) 662 sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16) | 663 (1 << 31); 664 else 665 sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16); 666 segs++; 667 bi = (bi + 1) % TX_QLEN; 668 ndq++; 669 } 670 671 672 /* 673 * Enqueue another. Don't do more than half the available 674 * descriptors before telling the MAC about them 675 */ 676 if ((sc->TXDQ_avail - ndq) > 0 && ndq < TX_QLEN / 2) { 677 IFQ_POLL(&ifp->if_snd, m); 678 if (m != NULL) { 679 goto more; 680 } 681 } 682 stop: 683 if (ndq > 0) { 684 sc->TXDQ_avail -= ndq; 685 sc->TXDQ_cur = &sc->TXDQ[bi]; 686 CTRLPAGE_DMASYNC(0, TX_QLEN * 2 * sizeof(u_int32_t), 687 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 688 EPE_WRITE(TXDEnq, ndq); 689 } 690 691 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 692 goto start; 693 694 splx(s); 695 return; 696 } 697 698 static void 699 epe_ifwatchdog(ifp) 700 struct ifnet *ifp; 701 { 702 struct epe_softc *sc = (struct epe_softc *)ifp->if_softc; 703 704 if ((ifp->if_flags & IFF_RUNNING) == 0) 705 return; 706 printf("%s: device timeout, BMCtl = 0x%08x, BMSts = 0x%08x\n", 707 sc->sc_dev.dv_xname, EPE_READ(BMCtl), EPE_READ(BMSts)); 708 } 709 710 static int 711 epe_ifinit(ifp) 712 struct ifnet *ifp; 713 { 714 struct epe_softc *sc = ifp->if_softc; 715 int s = splnet(); 716 717 callout_stop(&sc->epe_tick_ch); 718 EPE_WRITE(RXCtl, RXCtl_IA0|RXCtl_BA|RXCtl_RCRCA|RXCtl_SRxON); 719 EPE_WRITE(TXCtl, TXCtl_STxON); 720 EPE_WRITE(GIIntMsk, GIIntMsk_INT); /* start interrupting */ 721 mii_mediachg(&sc->sc_mii); 722 callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc); 723 ifp->if_flags |= IFF_RUNNING; 724 splx(s); 725 return 0; 726 } 727 728 static void 729 epe_ifstop(ifp, disable) 730 struct ifnet *ifp; 731 int disable; 732 { 733 struct epe_softc *sc = ifp->if_softc; 734 735 736 EPE_WRITE(RXCtl, 0); 737 EPE_WRITE(TXCtl, 0); 738 EPE_WRITE(GIIntMsk, 0); 739 callout_stop(&sc->epe_tick_ch); 740 741 /* Down the MII. */ 742 mii_down(&sc->sc_mii); 743 744 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 745 ifp->if_timer = 0; 746 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 747 } 748 749 static void 750 epe_setaddr(ifp) 751 struct ifnet *ifp; 752 { 753 struct epe_softc *sc = ifp->if_softc; 754 struct ethercom *ac = &sc->sc_ec; 755 struct ether_multi *enm; 756 struct ether_multistep step; 757 u_int8_t ias[2][ETHER_ADDR_LEN]; 758 u_int32_t h, nma = 0, hashes[2] = { 0, 0 }; 759 u_int32_t rxctl = EPE_READ(RXCtl); 760 761 /* disable receiver temporarily */ 762 EPE_WRITE(RXCtl, rxctl & ~RXCtl_SRxON); 763 764 rxctl &= ~(RXCtl_MA|RXCtl_PA|RXCtl_IA2|RXCtl_IA3); 765 766 if (ifp->if_flags & IFF_PROMISC) { 767 rxctl |= RXCtl_PA; 768 } 769 770 ifp->if_flags &= ~IFF_ALLMULTI; 771 772 ETHER_FIRST_MULTI(step, ac, enm); 773 while (enm != NULL) { 774 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 775 /* 776 * We must listen to a range of multicast addresses. 777 * For now, just accept all multicasts, rather than 778 * trying to set only those filter bits needed to match 779 * the range. (At this time, the only use of address 780 * ranges is for IP multicast routing, for which the 781 * range is big enough to require all bits set.) 782 */ 783 rxctl &= ~(RXCtl_IA2|RXCtl_IA3); 784 rxctl |= RXCtl_MA; 785 hashes[0] = 0xffffffffUL; 786 hashes[1] = 0xffffffffUL; 787 ifp->if_flags |= IFF_ALLMULTI; 788 break; 789 } 790 791 if (nma < 2) { 792 /* We can program 2 perfect address filters for mcast */ 793 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 794 rxctl |= (1 << (nma + 2)); 795 } else { 796 /* 797 * XXX: Datasheet is not very clear here, I'm not sure 798 * if I'm doing this right. --joff 799 */ 800 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 801 802 /* Just want the 6 most-significant bits. */ 803 h = h >> 26; 804 805 hashes[ h / 32 ] |= (1 << (h % 32)); 806 rxctl |= RXCtl_MA; 807 } 808 ETHER_NEXT_MULTI(step, enm); 809 nma++; 810 } 811 812 EPE_WRITE(AFP, 0); 813 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 814 sc->sc_enaddr, ETHER_ADDR_LEN); 815 if (rxctl & RXCtl_IA2) { 816 EPE_WRITE(AFP, 2); 817 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 818 ias[0], ETHER_ADDR_LEN); 819 } 820 if (rxctl & RXCtl_IA3) { 821 EPE_WRITE(AFP, 3); 822 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 823 ias[1], ETHER_ADDR_LEN); 824 } 825 if (hashes[0] != 0 && hashes[1] != 0) { 826 EPE_WRITE(AFP, 7); 827 EPE_WRITE(HashTbl, hashes[0]); 828 EPE_WRITE(HashTbl + 4, hashes[1]); 829 } 830 EPE_WRITE(RXCtl, rxctl); 831 } 832
Indexes created Tue Sep 30 11:09:46 GMT 2025