epe.c revision 1.31.6.1
1 /* $NetBSD: epe.c,v 1.31.6.1 2015/06/06 14:39:55 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Jesse Off 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: epe.c,v 1.31.6.1 2015/06/06 14:39:55 skrll Exp $"); 31 32 #include <sys/types.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/ioctl.h> 36 #include <sys/kernel.h> 37 #include <sys/proc.h> 38 #include <sys/malloc.h> 39 #include <sys/time.h> 40 #include <sys/device.h> 41 #include <uvm/uvm_extern.h> 42 43 #include <sys/bus.h> 44 #include <machine/intr.h> 45 46 #include <arm/cpufunc.h> 47 48 #include <arm/ep93xx/epsocvar.h> 49 #include <arm/ep93xx/ep93xxvar.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_types.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #include <dev/mii/mii.h> 58 #include <dev/mii/miivar.h> 59 60 #ifdef INET 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/in_var.h> 64 #include <netinet/ip.h> 65 #include <netinet/if_inarp.h> 66 #endif 67 68 #include <net/bpf.h> 69 #include <net/bpfdesc.h> 70 71 #include <arm/ep93xx/ep93xxreg.h> 72 #include <arm/ep93xx/epereg.h> 73 #include <arm/ep93xx/epevar.h> 74 75 #define DEFAULT_MDCDIV 32 76 77 #ifndef EPE_FAST 78 #define EPE_FAST 79 #endif 80 81 #ifndef EPE_FAST 82 #define EPE_READ(x) \ 83 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x)) 84 #define EPE_WRITE(x, y) \ 85 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x), (y)) 86 #define CTRLPAGE_DMASYNC(x, y, z) \ 87 bus_dmamap_sync(sc->sc_dmat, sc->ctrlpage_dmamap, (x), (y), (z)) 88 #else 89 #define EPE_READ(x) *(volatile uint32_t *) \ 90 (EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x)) 91 #define EPE_WRITE(x, y) *(volatile uint32_t *) \ 92 (EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x)) = y 93 #define CTRLPAGE_DMASYNC(x, y, z) 94 #endif /* ! EPE_FAST */ 95 96 static int epe_match(device_t , cfdata_t, void *); 97 static void epe_attach(device_t, device_t, void *); 98 static void epe_init(struct epe_softc *); 99 static int epe_intr(void* arg); 100 static int epe_gctx(struct epe_softc *); 101 static int epe_mediachange(struct ifnet *); 102 int epe_mii_readreg (device_t, int, int); 103 void epe_mii_writereg (device_t, int, int, int); 104 void epe_statchg (struct ifnet *); 105 void epe_tick (void *); 106 static int epe_ifioctl (struct ifnet *, u_long, void *); 107 static void epe_ifstart (struct ifnet *); 108 static void epe_ifwatchdog (struct ifnet *); 109 static int epe_ifinit (struct ifnet *); 110 static void epe_ifstop (struct ifnet *, int); 111 static void epe_setaddr (struct ifnet *); 112 113 CFATTACH_DECL_NEW(epe, sizeof(struct epe_softc), 114 epe_match, epe_attach, NULL, NULL); 115 116 static int 117 epe_match(device_t parent, cfdata_t match, void *aux) 118 { 119 return 2; 120 } 121 122 static void 123 epe_attach(device_t parent, device_t self, void *aux) 124 { 125 struct epe_softc *sc = device_private(self); 126 struct epsoc_attach_args *sa; 127 prop_data_t enaddr; 128 129 aprint_normal("\n"); 130 sa = aux; 131 sc->sc_dev = self; 132 sc->sc_iot = sa->sa_iot; 133 sc->sc_intr = sa->sa_intr; 134 sc->sc_dmat = sa->sa_dmat; 135 136 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 137 0, &sc->sc_ioh)) 138 panic("%s: Cannot map registers", device_xname(self)); 139 140 /* Fetch the Ethernet address from property if set. */ 141 enaddr = prop_dictionary_get(device_properties(self), "mac-address"); 142 if (enaddr != NULL) { 143 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 144 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 145 memcpy(sc->sc_enaddr, prop_data_data_nocopy(enaddr), 146 ETHER_ADDR_LEN); 147 bus_space_write_4(sc->sc_iot, sc->sc_ioh, EPE_AFP, 0); 148 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 149 sc->sc_enaddr, ETHER_ADDR_LEN); 150 } 151 152 ep93xx_intr_establish(sc->sc_intr, IPL_NET, epe_intr, sc); 153 epe_init(sc); 154 } 155 156 static int 157 epe_gctx(struct epe_softc *sc) 158 { 159 struct ifnet * ifp = &sc->sc_ec.ec_if; 160 uint32_t *cur, ndq = 0; 161 162 /* Handle transmit completions */ 163 cur = (uint32_t *)(EPE_READ(TXStsQCurAdd) - 164 sc->ctrlpage_dsaddr + (char*)sc->ctrlpage); 165 166 if (sc->TXStsQ_cur != cur) { 167 CTRLPAGE_DMASYNC(TX_QLEN * 2 * sizeof(uint32_t), 168 TX_QLEN * sizeof(uint32_t), BUS_DMASYNC_PREREAD); 169 } else { 170 return 0; 171 } 172 173 do { 174 uint32_t tbi = *sc->TXStsQ_cur & 0x7fff; 175 struct mbuf *m = sc->txq[tbi].m; 176 177 if ((*sc->TXStsQ_cur & TXStsQ_TxWE) == 0) { 178 ifp->if_oerrors++; 179 } 180 bus_dmamap_unload(sc->sc_dmat, sc->txq[tbi].m_dmamap); 181 m_freem(m); 182 do { 183 sc->txq[tbi].m = NULL; 184 ndq++; 185 tbi = (tbi + 1) % TX_QLEN; 186 } while (sc->txq[tbi].m == m); 187 188 ifp->if_opackets++; 189 sc->TXStsQ_cur++; 190 if (sc->TXStsQ_cur >= sc->TXStsQ + TX_QLEN) { 191 sc->TXStsQ_cur = sc->TXStsQ; 192 } 193 } while (sc->TXStsQ_cur != cur); 194 195 sc->TXDQ_avail += ndq; 196 if (ifp->if_flags & IFF_OACTIVE) { 197 ifp->if_flags &= ~IFF_OACTIVE; 198 /* Disable end-of-tx-chain interrupt */ 199 EPE_WRITE(IntEn, IntEn_REOFIE); 200 } 201 return ndq; 202 } 203 204 static int 205 epe_intr(void *arg) 206 { 207 struct epe_softc *sc = (struct epe_softc *)arg; 208 struct ifnet * ifp = &sc->sc_ec.ec_if; 209 uint32_t ndq = 0, irq, *cur; 210 211 irq = EPE_READ(IntStsC); 212 begin: 213 cur = (uint32_t *)(EPE_READ(RXStsQCurAdd) - 214 sc->ctrlpage_dsaddr + (char*)sc->ctrlpage); 215 CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(uint32_t), 216 RX_QLEN * 4 * sizeof(uint32_t), 217 BUS_DMASYNC_PREREAD); 218 while (sc->RXStsQ_cur != cur) { 219 if ((sc->RXStsQ_cur[0] & (RXStsQ_RWE|RXStsQ_RFP|RXStsQ_EOB)) == 220 (RXStsQ_RWE|RXStsQ_RFP|RXStsQ_EOB)) { 221 uint32_t bi = (sc->RXStsQ_cur[1] >> 16) & 0x7fff; 222 uint32_t fl = sc->RXStsQ_cur[1] & 0xffff; 223 struct mbuf *m; 224 225 MGETHDR(m, M_DONTWAIT, MT_DATA); 226 if (m != NULL) MCLGET(m, M_DONTWAIT); 227 if (m != NULL && (m->m_flags & M_EXT)) { 228 bus_dmamap_unload(sc->sc_dmat, 229 sc->rxq[bi].m_dmamap); 230 sc->rxq[bi].m->m_pkthdr.rcvif = ifp; 231 sc->rxq[bi].m->m_pkthdr.len = 232 sc->rxq[bi].m->m_len = fl; 233 bpf_mtap(ifp, sc->rxq[bi].m); 234 (*ifp->if_input)(ifp, sc->rxq[bi].m); 235 sc->rxq[bi].m = m; 236 bus_dmamap_load(sc->sc_dmat, 237 sc->rxq[bi].m_dmamap, 238 m->m_ext.ext_buf, MCLBYTES, 239 NULL, BUS_DMA_NOWAIT); 240 sc->RXDQ[bi * 2] = 241 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr; 242 } else { 243 /* Drop packets until we can get replacement 244 * empty mbufs for the RXDQ. 245 */ 246 if (m != NULL) { 247 m_freem(m); 248 } 249 ifp->if_ierrors++; 250 } 251 } else { 252 ifp->if_ierrors++; 253 } 254 255 ndq++; 256 257 sc->RXStsQ_cur += 2; 258 if (sc->RXStsQ_cur >= sc->RXStsQ + (RX_QLEN * 2)) { 259 sc->RXStsQ_cur = sc->RXStsQ; 260 } 261 } 262 263 if (ndq > 0) { 264 ifp->if_ipackets += ndq; 265 CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(uint32_t), 266 RX_QLEN * 4 * sizeof(uint32_t), 267 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 268 EPE_WRITE(RXStsEnq, ndq); 269 EPE_WRITE(RXDEnq, ndq); 270 ndq = 0; 271 } 272 273 if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 274 epe_ifstart(ifp); 275 } 276 277 irq = EPE_READ(IntStsC); 278 if ((irq & (IntSts_RxSQ|IntSts_ECI)) != 0) 279 goto begin; 280 281 return (1); 282 } 283 284 285 static void 286 epe_init(struct epe_softc *sc) 287 { 288 bus_dma_segment_t segs; 289 char *addr; 290 int rsegs, err, i; 291 struct ifnet * ifp = &sc->sc_ec.ec_if; 292 int mdcdiv = DEFAULT_MDCDIV; 293 294 callout_init(&sc->epe_tick_ch, 0); 295 296 /* Select primary Individual Address in Address Filter Pointer */ 297 EPE_WRITE(AFP, 0); 298 /* Read ethernet MAC, should already be set by bootrom */ 299 bus_space_read_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 300 sc->sc_enaddr, ETHER_ADDR_LEN); 301 aprint_normal_dev(sc->sc_dev, "MAC address %s\n", 302 ether_sprintf(sc->sc_enaddr)); 303 304 /* Soft Reset the MAC */ 305 EPE_WRITE(SelfCtl, SelfCtl_RESET); 306 while(EPE_READ(SelfCtl) & SelfCtl_RESET); 307 308 /* suggested magic initialization values from datasheet */ 309 EPE_WRITE(RXBufThrshld, 0x800040); 310 EPE_WRITE(TXBufThrshld, 0x200010); 311 EPE_WRITE(RXStsThrshld, 0x40002); 312 EPE_WRITE(TXStsThrshld, 0x40002); 313 EPE_WRITE(RXDThrshld, 0x40002); 314 EPE_WRITE(TXDThrshld, 0x40002); 315 316 /* Allocate a page of memory for descriptor and status queues */ 317 err = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, 0, PAGE_SIZE, 318 &segs, 1, &rsegs, BUS_DMA_WAITOK); 319 if (err == 0) { 320 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, PAGE_SIZE, 321 &sc->ctrlpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT)); 322 } 323 if (err == 0) { 324 err = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 325 0, BUS_DMA_WAITOK, &sc->ctrlpage_dmamap); 326 } 327 if (err == 0) { 328 err = bus_dmamap_load(sc->sc_dmat, sc->ctrlpage_dmamap, 329 sc->ctrlpage, PAGE_SIZE, NULL, BUS_DMA_WAITOK); 330 } 331 if (err != 0) { 332 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 333 } 334 sc->ctrlpage_dsaddr = sc->ctrlpage_dmamap->dm_segs[0].ds_addr; 335 memset(sc->ctrlpage, 0, PAGE_SIZE); 336 337 /* Set up pointers to start of each queue in kernel addr space. 338 * Each descriptor queue or status queue entry uses 2 words 339 */ 340 sc->TXDQ = (uint32_t *)sc->ctrlpage; 341 sc->TXDQ_cur = sc->TXDQ; 342 sc->TXDQ_avail = TX_QLEN - 1; 343 sc->TXStsQ = &sc->TXDQ[TX_QLEN * 2]; 344 sc->TXStsQ_cur = sc->TXStsQ; 345 sc->RXDQ = &sc->TXStsQ[TX_QLEN]; 346 sc->RXStsQ = &sc->RXDQ[RX_QLEN * 2]; 347 sc->RXStsQ_cur = sc->RXStsQ; 348 349 /* Program each queue's start addr, cur addr, and len registers 350 * with the physical addresses. 351 */ 352 addr = (char *)sc->ctrlpage_dmamap->dm_segs[0].ds_addr; 353 EPE_WRITE(TXDQBAdd, (uint32_t)addr); 354 EPE_WRITE(TXDQCurAdd, (uint32_t)addr); 355 EPE_WRITE(TXDQBLen, TX_QLEN * 2 * sizeof(uint32_t)); 356 357 addr += (sc->TXStsQ - sc->TXDQ) * sizeof(uint32_t); 358 EPE_WRITE(TXStsQBAdd, (uint32_t)addr); 359 EPE_WRITE(TXStsQCurAdd, (uint32_t)addr); 360 EPE_WRITE(TXStsQBLen, TX_QLEN * sizeof(uint32_t)); 361 362 addr += (sc->RXDQ - sc->TXStsQ) * sizeof(uint32_t); 363 EPE_WRITE(RXDQBAdd, (uint32_t)addr); 364 EPE_WRITE(RXDCurAdd, (uint32_t)addr); 365 EPE_WRITE(RXDQBLen, RX_QLEN * 2 * sizeof(uint32_t)); 366 367 addr += (sc->RXStsQ - sc->RXDQ) * sizeof(uint32_t); 368 EPE_WRITE(RXStsQBAdd, (uint32_t)addr); 369 EPE_WRITE(RXStsQCurAdd, (uint32_t)addr); 370 EPE_WRITE(RXStsQBLen, RX_QLEN * 2 * sizeof(uint32_t)); 371 372 /* Populate the RXDQ with mbufs */ 373 for(i = 0; i < RX_QLEN; i++) { 374 struct mbuf *m; 375 376 bus_dmamap_create(sc->sc_dmat, MCLBYTES, TX_QLEN/4, MCLBYTES, 0, 377 BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 378 MGETHDR(m, M_WAIT, MT_DATA); 379 MCLGET(m, M_WAIT); 380 sc->rxq[i].m = m; 381 bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 382 m->m_ext.ext_buf, MCLBYTES, NULL, 383 BUS_DMA_WAITOK); 384 385 sc->RXDQ[i * 2] = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr; 386 sc->RXDQ[i * 2 + 1] = (i << 16) | MCLBYTES; 387 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 388 MCLBYTES, BUS_DMASYNC_PREREAD); 389 } 390 391 for(i = 0; i < TX_QLEN; i++) { 392 bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 393 (BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW), 394 &sc->txq[i].m_dmamap); 395 sc->txq[i].m = NULL; 396 sc->TXDQ[i * 2 + 1] = (i << 16); 397 } 398 399 /* Divide HCLK by 32 for MDC clock */ 400 if (device_cfdata(sc->sc_dev)->cf_flags) 401 mdcdiv = device_cfdata(sc->sc_dev)->cf_flags; 402 EPE_WRITE(SelfCtl, (SelfCtl_MDCDIV(mdcdiv)|SelfCtl_PSPRS)); 403 404 sc->sc_mii.mii_ifp = ifp; 405 sc->sc_mii.mii_readreg = epe_mii_readreg; 406 sc->sc_mii.mii_writereg = epe_mii_writereg; 407 sc->sc_mii.mii_statchg = epe_statchg; 408 sc->sc_ec.ec_mii = &sc->sc_mii; 409 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, epe_mediachange, 410 ether_mediastatus); 411 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 412 MII_OFFSET_ANY, 0); 413 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 414 415 EPE_WRITE(BMCtl, BMCtl_RxEn|BMCtl_TxEn); 416 EPE_WRITE(IntEn, IntEn_REOFIE); 417 /* maximum valid max frame length */ 418 EPE_WRITE(MaxFrmLen, (0x7ff << 16)|MHLEN); 419 /* wait for receiver ready */ 420 while((EPE_READ(BMSts) & BMSts_RxAct) == 0) 421 continue; 422 /* enqueue the entries in RXStsQ and RXDQ */ 423 CTRLPAGE_DMASYNC(0, sc->ctrlpage_dmamap->dm_mapsize, 424 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 425 EPE_WRITE(RXDEnq, RX_QLEN - 1); 426 EPE_WRITE(RXStsEnq, RX_QLEN - 1); 427 428 /* 429 * We can support 802.1Q VLAN-sized frames. 430 */ 431 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 432 433 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 434 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 435 ifp->if_ioctl = epe_ifioctl; 436 ifp->if_start = epe_ifstart; 437 ifp->if_watchdog = epe_ifwatchdog; 438 ifp->if_init = epe_ifinit; 439 ifp->if_stop = epe_ifstop; 440 ifp->if_timer = 0; 441 ifp->if_softc = sc; 442 IFQ_SET_READY(&ifp->if_snd); 443 if_attach(ifp); 444 ether_ifattach(ifp, (sc)->sc_enaddr); 445 } 446 447 static int 448 epe_mediachange(struct ifnet *ifp) 449 { 450 if (ifp->if_flags & IFF_UP) 451 epe_ifinit(ifp); 452 return (0); 453 } 454 455 int 456 epe_mii_readreg(device_t self, int phy, int reg) 457 { 458 uint32_t d, v; 459 460 d = EPE_READ(SelfCtl); 461 EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */ 462 EPE_WRITE(MIICmd, (MIICmd_READ | (phy << 5) | reg)); 463 while(EPE_READ(MIISts) & MIISts_BUSY); 464 v = EPE_READ(MIIData); 465 EPE_WRITE(SelfCtl, d); /* restore old value */ 466 return v; 467 } 468 469 void 470 epe_mii_writereg(device_t self, int phy, int reg, int val) 471 { 472 uint32_t d; 473 474 d = EPE_READ(SelfCtl); 475 EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */ 476 EPE_WRITE(MIIData, val); 477 EPE_WRITE(MIICmd, (MIICmd_WRITE | (phy << 5) | reg)); 478 while(EPE_READ(MIISts) & MIISts_BUSY); 479 EPE_WRITE(SelfCtl, d); /* restore old value */ 480 } 481 482 483 void 484 epe_statchg(struct ifnet *ifp) 485 { 486 struct epe_softc *sc = ifp->if_softc; 487 uint32_t reg; 488 489 /* 490 * We must keep the MAC and the PHY in sync as 491 * to the status of full-duplex! 492 */ 493 reg = EPE_READ(TestCtl); 494 if (sc->sc_mii.mii_media_active & IFM_FDX) 495 reg |= TestCtl_MFDX; 496 else 497 reg &= ~TestCtl_MFDX; 498 EPE_WRITE(TestCtl, reg); 499 } 500 501 void 502 epe_tick(void *arg) 503 { 504 struct epe_softc* sc = (struct epe_softc *)arg; 505 struct ifnet * ifp = &sc->sc_ec.ec_if; 506 int s; 507 uint32_t misses; 508 509 ifp->if_collisions += EPE_READ(TXCollCnt); 510 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 511 misses = EPE_READ(RXMissCnt); 512 if (misses > 0) 513 printf("%s: %d rx misses\n", device_xname(sc->sc_dev), misses); 514 515 s = splnet(); 516 if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 517 epe_ifstart(ifp); 518 } 519 splx(s); 520 521 mii_tick(&sc->sc_mii); 522 callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc); 523 } 524 525 526 static int 527 epe_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 528 { 529 int s, error; 530 531 s = splnet(); 532 error = ether_ioctl(ifp, cmd, data); 533 if (error == ENETRESET) { 534 if (ifp->if_flags & IFF_RUNNING) 535 epe_setaddr(ifp); 536 error = 0; 537 } 538 splx(s); 539 return error; 540 } 541 542 static void 543 epe_ifstart(struct ifnet *ifp) 544 { 545 struct epe_softc *sc = (struct epe_softc *)ifp->if_softc; 546 struct mbuf *m; 547 bus_dma_segment_t *segs; 548 int s, bi, err, nsegs, ndq; 549 550 s = splnet(); 551 start: 552 ndq = 0; 553 if (sc->TXDQ_avail == 0) { 554 if (epe_gctx(sc) == 0) { 555 /* Enable End-Of-TX-Chain interrupt */ 556 EPE_WRITE(IntEn, IntEn_REOFIE|IntEn_ECIE); 557 ifp->if_flags |= IFF_OACTIVE; 558 ifp->if_timer = 10; 559 splx(s); 560 return; 561 } 562 } 563 564 bi = sc->TXDQ_cur - sc->TXDQ; 565 566 IFQ_POLL(&ifp->if_snd, m); 567 if (m == NULL) { 568 splx(s); 569 return; 570 } 571 more: 572 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 573 BUS_DMA_NOWAIT)) || 574 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 575 sc->txq[bi].m_dmamap->dm_nsegs > (sc->TXDQ_avail - ndq)) { 576 /* Copy entire mbuf chain to new and 32-bit aligned storage */ 577 struct mbuf *mn; 578 579 if (err == 0) 580 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 581 582 MGETHDR(mn, M_DONTWAIT, MT_DATA); 583 if (mn == NULL) goto stop; 584 if (m->m_pkthdr.len > (MHLEN & (~0x3))) { 585 MCLGET(mn, M_DONTWAIT); 586 if ((mn->m_flags & M_EXT) == 0) { 587 m_freem(mn); 588 goto stop; 589 } 590 } 591 mn->m_data = (void *)(((uint32_t)mn->m_data + 0x3) & (~0x3)); 592 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 593 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 594 IFQ_DEQUEUE(&ifp->if_snd, m); 595 m_freem(m); 596 m = mn; 597 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 598 BUS_DMA_NOWAIT); 599 } else { 600 IFQ_DEQUEUE(&ifp->if_snd, m); 601 } 602 603 bpf_mtap(ifp, m); 604 605 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 606 segs = sc->txq[bi].m_dmamap->dm_segs; 607 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 608 sc->txq[bi].m_dmamap->dm_mapsize, 609 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 610 611 /* XXX: This driver hasn't been tested w/nsegs > 1 */ 612 while (nsegs > 0) { 613 nsegs--; 614 sc->txq[bi].m = m; 615 sc->TXDQ[bi * 2] = segs->ds_addr; 616 if (nsegs == 0) 617 sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16) | 618 (1 << 31); 619 else 620 sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16); 621 segs++; 622 bi = (bi + 1) % TX_QLEN; 623 ndq++; 624 } 625 626 627 /* 628 * Enqueue another. Don't do more than half the available 629 * descriptors before telling the MAC about them 630 */ 631 if ((sc->TXDQ_avail - ndq) > 0 && ndq < TX_QLEN / 2) { 632 IFQ_POLL(&ifp->if_snd, m); 633 if (m != NULL) { 634 goto more; 635 } 636 } 637 stop: 638 if (ndq > 0) { 639 sc->TXDQ_avail -= ndq; 640 sc->TXDQ_cur = &sc->TXDQ[bi]; 641 CTRLPAGE_DMASYNC(0, TX_QLEN * 2 * sizeof(uint32_t), 642 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 643 EPE_WRITE(TXDEnq, ndq); 644 } 645 646 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 647 goto start; 648 649 splx(s); 650 return; 651 } 652 653 static void 654 epe_ifwatchdog(struct ifnet *ifp) 655 { 656 struct epe_softc *sc = (struct epe_softc *)ifp->if_softc; 657 658 if ((ifp->if_flags & IFF_RUNNING) == 0) 659 return; 660 printf("%s: device timeout, BMCtl = 0x%08x, BMSts = 0x%08x\n", 661 device_xname(sc->sc_dev), EPE_READ(BMCtl), EPE_READ(BMSts)); 662 } 663 664 static int 665 epe_ifinit(struct ifnet *ifp) 666 { 667 struct epe_softc *sc = ifp->if_softc; 668 int rc, s = splnet(); 669 670 callout_stop(&sc->epe_tick_ch); 671 EPE_WRITE(RXCtl, RXCtl_IA0|RXCtl_BA|RXCtl_RCRCA|RXCtl_SRxON); 672 EPE_WRITE(TXCtl, TXCtl_STxON); 673 EPE_WRITE(GIIntMsk, GIIntMsk_INT); /* start interrupting */ 674 675 if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 676 rc = 0; 677 else if (rc != 0) 678 goto out; 679 680 callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc); 681 ifp->if_flags |= IFF_RUNNING; 682 out: 683 splx(s); 684 return 0; 685 } 686 687 static void 688 epe_ifstop(struct ifnet *ifp, int disable) 689 { 690 struct epe_softc *sc = ifp->if_softc; 691 692 693 EPE_WRITE(RXCtl, 0); 694 EPE_WRITE(TXCtl, 0); 695 EPE_WRITE(GIIntMsk, 0); 696 callout_stop(&sc->epe_tick_ch); 697 698 /* Down the MII. */ 699 mii_down(&sc->sc_mii); 700 701 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 702 ifp->if_timer = 0; 703 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 704 } 705 706 static void 707 epe_setaddr(struct ifnet *ifp) 708 { 709 struct epe_softc *sc = ifp->if_softc; 710 struct ethercom *ac = &sc->sc_ec; 711 struct ether_multi *enm; 712 struct ether_multistep step; 713 uint8_t ias[2][ETHER_ADDR_LEN]; 714 uint32_t h, nma = 0, hashes[2] = { 0, 0 }; 715 uint32_t rxctl = EPE_READ(RXCtl); 716 717 /* disable receiver temporarily */ 718 EPE_WRITE(RXCtl, rxctl & ~RXCtl_SRxON); 719 720 rxctl &= ~(RXCtl_MA|RXCtl_PA|RXCtl_IA2|RXCtl_IA3); 721 722 if (ifp->if_flags & IFF_PROMISC) { 723 rxctl |= RXCtl_PA; 724 } 725 726 ifp->if_flags &= ~IFF_ALLMULTI; 727 728 ETHER_FIRST_MULTI(step, ac, enm); 729 while (enm != NULL) { 730 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 731 /* 732 * We must listen to a range of multicast addresses. 733 * For now, just accept all multicasts, rather than 734 * trying to set only those filter bits needed to match 735 * the range. (At this time, the only use of address 736 * ranges is for IP multicast routing, for which the 737 * range is big enough to require all bits set.) 738 */ 739 rxctl &= ~(RXCtl_IA2|RXCtl_IA3); 740 rxctl |= RXCtl_MA; 741 hashes[0] = 0xffffffffUL; 742 hashes[1] = 0xffffffffUL; 743 ifp->if_flags |= IFF_ALLMULTI; 744 break; 745 } 746 747 if (nma < 2) { 748 /* We can program 2 perfect address filters for mcast */ 749 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 750 rxctl |= (1 << (nma + 2)); 751 } else { 752 /* 753 * XXX: Datasheet is not very clear here, I'm not sure 754 * if I'm doing this right. --joff 755 */ 756 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 757 758 /* Just want the 6 most-significant bits. */ 759 h = h >> 26; 760 761 hashes[ h / 32 ] |= (1 << (h % 32)); 762 rxctl |= RXCtl_MA; 763 } 764 ETHER_NEXT_MULTI(step, enm); 765 nma++; 766 } 767 768 EPE_WRITE(AFP, 0); 769 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 770 sc->sc_enaddr, ETHER_ADDR_LEN); 771 if (rxctl & RXCtl_IA2) { 772 EPE_WRITE(AFP, 2); 773 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 774 ias[0], ETHER_ADDR_LEN); 775 } 776 if (rxctl & RXCtl_IA3) { 777 EPE_WRITE(AFP, 3); 778 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 779 ias[1], ETHER_ADDR_LEN); 780 } 781 if (hashes[0] != 0 && hashes[1] != 0) { 782 EPE_WRITE(AFP, 7); 783 EPE_WRITE(HashTbl, hashes[0]); 784 EPE_WRITE(HashTbl + 4, hashes[1]); 785 } 786 EPE_WRITE(RXCtl, rxctl); 787 } 788
Indexes created Mon Oct 27 04:09:48 GMT 2025