epe.c revision 1.43
1 /* $NetBSD: epe.c,v 1.43 2019/05/28 07:41:46 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Jesse Off 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: epe.c,v 1.43 2019/05/28 07:41:46 msaitoh Exp $"); 31 32 #include <sys/types.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/ioctl.h> 36 #include <sys/kernel.h> 37 #include <sys/proc.h> 38 #include <sys/malloc.h> 39 #include <sys/time.h> 40 #include <sys/device.h> 41 #include <uvm/uvm_extern.h> 42 43 #include <sys/bus.h> 44 #include <machine/intr.h> 45 46 #include <arm/cpufunc.h> 47 48 #include <arm/ep93xx/epsocvar.h> 49 #include <arm/ep93xx/ep93xxvar.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_types.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 #include <net/bpf.h> 57 58 #include <dev/mii/mii.h> 59 #include <dev/mii/miivar.h> 60 61 #ifdef INET 62 #include <netinet/in.h> 63 #include <netinet/in_systm.h> 64 #include <netinet/in_var.h> 65 #include <netinet/ip.h> 66 #include <netinet/if_inarp.h> 67 #endif 68 69 #include <arm/ep93xx/ep93xxreg.h> 70 #include <arm/ep93xx/epereg.h> 71 #include <arm/ep93xx/epevar.h> 72 73 #define DEFAULT_MDCDIV 32 74 75 #ifndef EPE_FAST 76 #define EPE_FAST 77 #endif 78 79 #ifndef EPE_FAST 80 #define EPE_READ(x) \ 81 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x)) 82 #define EPE_WRITE(x, y) \ 83 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x), (y)) 84 #define CTRLPAGE_DMASYNC(x, y, z) \ 85 bus_dmamap_sync(sc->sc_dmat, sc->ctrlpage_dmamap, (x), (y), (z)) 86 #else 87 #define EPE_READ(x) *(volatile uint32_t *) \ 88 (EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x)) 89 #define EPE_WRITE(x, y) *(volatile uint32_t *) \ 90 (EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x)) = y 91 #define CTRLPAGE_DMASYNC(x, y, z) 92 #endif /* ! EPE_FAST */ 93 94 static int epe_match(device_t , cfdata_t, void *); 95 static void epe_attach(device_t, device_t, void *); 96 static void epe_init(struct epe_softc *); 97 static int epe_intr(void* arg); 98 static int epe_gctx(struct epe_softc *); 99 static int epe_mediachange(struct ifnet *); 100 int epe_mii_readreg (device_t, int, int, uint16_t *); 101 int epe_mii_writereg (device_t, int, int, uint16_t); 102 void epe_statchg (struct ifnet *); 103 void epe_tick (void *); 104 static int epe_ifioctl (struct ifnet *, u_long, void *); 105 static void epe_ifstart (struct ifnet *); 106 static void epe_ifwatchdog (struct ifnet *); 107 static int epe_ifinit (struct ifnet *); 108 static void epe_ifstop (struct ifnet *, int); 109 static void epe_setaddr (struct ifnet *); 110 111 CFATTACH_DECL_NEW(epe, sizeof(struct epe_softc), 112 epe_match, epe_attach, NULL, NULL); 113 114 static int 115 epe_match(device_t parent, cfdata_t match, void *aux) 116 { 117 return 2; 118 } 119 120 static void 121 epe_attach(device_t parent, device_t self, void *aux) 122 { 123 struct epe_softc *sc = device_private(self); 124 struct epsoc_attach_args *sa; 125 prop_data_t enaddr; 126 127 aprint_normal("\n"); 128 sa = aux; 129 sc->sc_dev = self; 130 sc->sc_iot = sa->sa_iot; 131 sc->sc_intr = sa->sa_intr; 132 sc->sc_dmat = sa->sa_dmat; 133 134 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 135 0, &sc->sc_ioh)) 136 panic("%s: Cannot map registers", device_xname(self)); 137 138 /* Fetch the Ethernet address from property if set. */ 139 enaddr = prop_dictionary_get(device_properties(self), "mac-address"); 140 if (enaddr != NULL) { 141 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 142 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 143 memcpy(sc->sc_enaddr, prop_data_data_nocopy(enaddr), 144 ETHER_ADDR_LEN); 145 bus_space_write_4(sc->sc_iot, sc->sc_ioh, EPE_AFP, 0); 146 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 147 sc->sc_enaddr, ETHER_ADDR_LEN); 148 } 149 150 ep93xx_intr_establish(sc->sc_intr, IPL_NET, epe_intr, sc); 151 epe_init(sc); 152 } 153 154 static int 155 epe_gctx(struct epe_softc *sc) 156 { 157 struct ifnet * ifp = &sc->sc_ec.ec_if; 158 uint32_t *cur, ndq = 0; 159 160 /* Handle transmit completions */ 161 cur = (uint32_t *)(EPE_READ(TXStsQCurAdd) - 162 sc->ctrlpage_dsaddr + (char*)sc->ctrlpage); 163 164 if (sc->TXStsQ_cur != cur) { 165 CTRLPAGE_DMASYNC(TX_QLEN * 2 * sizeof(uint32_t), 166 TX_QLEN * sizeof(uint32_t), BUS_DMASYNC_PREREAD); 167 } else 168 return 0; 169 170 do { 171 uint32_t tbi = *sc->TXStsQ_cur & 0x7fff; 172 struct mbuf *m = sc->txq[tbi].m; 173 174 if ((*sc->TXStsQ_cur & TXStsQ_TxWE) == 0) 175 ifp->if_oerrors++; 176 177 bus_dmamap_unload(sc->sc_dmat, sc->txq[tbi].m_dmamap); 178 m_freem(m); 179 do { 180 sc->txq[tbi].m = NULL; 181 ndq++; 182 tbi = (tbi + 1) % TX_QLEN; 183 } while (sc->txq[tbi].m == m); 184 185 ifp->if_opackets++; 186 sc->TXStsQ_cur++; 187 if (sc->TXStsQ_cur >= sc->TXStsQ + TX_QLEN) { 188 sc->TXStsQ_cur = sc->TXStsQ; 189 } 190 } while (sc->TXStsQ_cur != cur); 191 192 sc->TXDQ_avail += ndq; 193 if (ifp->if_flags & IFF_OACTIVE) { 194 ifp->if_flags &= ~IFF_OACTIVE; 195 /* Disable end-of-tx-chain interrupt */ 196 EPE_WRITE(IntEn, IntEn_REOFIE); 197 } 198 return ndq; 199 } 200 201 static int 202 epe_intr(void *arg) 203 { 204 struct epe_softc *sc = (struct epe_softc *)arg; 205 struct ifnet * ifp = &sc->sc_ec.ec_if; 206 uint32_t ndq = 0, irq, *cur; 207 208 irq = EPE_READ(IntStsC); 209 begin: 210 cur = (uint32_t *)(EPE_READ(RXStsQCurAdd) - 211 sc->ctrlpage_dsaddr + (char*)sc->ctrlpage); 212 CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(uint32_t), 213 RX_QLEN * 4 * sizeof(uint32_t), 214 BUS_DMASYNC_PREREAD); 215 while (sc->RXStsQ_cur != cur) { 216 if ((sc->RXStsQ_cur[0] & (RXStsQ_RWE | RXStsQ_RFP |RXStsQ_EOB)) 217 == (RXStsQ_RWE | RXStsQ_RFP | RXStsQ_EOB)) { 218 uint32_t bi = (sc->RXStsQ_cur[1] >> 16) & 0x7fff; 219 uint32_t fl = sc->RXStsQ_cur[1] & 0xffff; 220 struct mbuf *m; 221 222 MGETHDR(m, M_DONTWAIT, MT_DATA); 223 if (m != NULL) MCLGET(m, M_DONTWAIT); 224 if (m != NULL && (m->m_flags & M_EXT)) { 225 bus_dmamap_unload(sc->sc_dmat, 226 sc->rxq[bi].m_dmamap); 227 m_set_rcvif(sc->rxq[bi].m, ifp); 228 sc->rxq[bi].m->m_pkthdr.len = 229 sc->rxq[bi].m->m_len = fl; 230 if_percpuq_enqueue(ifp->if_percpuq, 231 sc->rxq[bi].m); 232 sc->rxq[bi].m = m; 233 bus_dmamap_load(sc->sc_dmat, 234 sc->rxq[bi].m_dmamap, 235 m->m_ext.ext_buf, MCLBYTES, 236 NULL, BUS_DMA_NOWAIT); 237 sc->RXDQ[bi * 2] = 238 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr; 239 } else { 240 /* Drop packets until we can get replacement 241 * empty mbufs for the RXDQ. 242 */ 243 if (m != NULL) 244 m_freem(m); 245 246 ifp->if_ierrors++; 247 } 248 } else 249 ifp->if_ierrors++; 250 251 ndq++; 252 253 sc->RXStsQ_cur += 2; 254 if (sc->RXStsQ_cur >= sc->RXStsQ + (RX_QLEN * 2)) 255 sc->RXStsQ_cur = sc->RXStsQ; 256 } 257 258 if (ndq > 0) { 259 ifp->if_ipackets += ndq; 260 CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(uint32_t), 261 RX_QLEN * 4 * sizeof(uint32_t), 262 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 263 EPE_WRITE(RXStsEnq, ndq); 264 EPE_WRITE(RXDEnq, ndq); 265 ndq = 0; 266 } 267 268 if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 269 if_schedule_deferred_start(ifp); 270 } 271 272 irq = EPE_READ(IntStsC); 273 if ((irq & (IntSts_RxSQ | IntSts_ECI)) != 0) 274 goto begin; 275 276 return 1; 277 } 278 279 280 static void 281 epe_init(struct epe_softc *sc) 282 { 283 bus_dma_segment_t segs; 284 char *addr; 285 int rsegs, err, i; 286 struct ifnet * ifp = &sc->sc_ec.ec_if; 287 int mdcdiv = DEFAULT_MDCDIV; 288 289 callout_init(&sc->epe_tick_ch, 0); 290 291 /* Select primary Individual Address in Address Filter Pointer */ 292 EPE_WRITE(AFP, 0); 293 /* Read ethernet MAC, should already be set by bootrom */ 294 bus_space_read_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 295 sc->sc_enaddr, ETHER_ADDR_LEN); 296 aprint_normal_dev(sc->sc_dev, "MAC address %s\n", 297 ether_sprintf(sc->sc_enaddr)); 298 299 /* Soft Reset the MAC */ 300 EPE_WRITE(SelfCtl, SelfCtl_RESET); 301 while (EPE_READ(SelfCtl) & SelfCtl_RESET) 302 ; 303 304 /* suggested magic initialization values from datasheet */ 305 EPE_WRITE(RXBufThrshld, 0x800040); 306 EPE_WRITE(TXBufThrshld, 0x200010); 307 EPE_WRITE(RXStsThrshld, 0x40002); 308 EPE_WRITE(TXStsThrshld, 0x40002); 309 EPE_WRITE(RXDThrshld, 0x40002); 310 EPE_WRITE(TXDThrshld, 0x40002); 311 312 /* Allocate a page of memory for descriptor and status queues */ 313 err = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, 0, PAGE_SIZE, 314 &segs, 1, &rsegs, BUS_DMA_WAITOK); 315 if (err == 0) { 316 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, PAGE_SIZE, 317 &sc->ctrlpage, (BUS_DMA_WAITOK | BUS_DMA_COHERENT)); 318 } 319 if (err == 0) { 320 err = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 321 0, BUS_DMA_WAITOK, &sc->ctrlpage_dmamap); 322 } 323 if (err == 0) { 324 err = bus_dmamap_load(sc->sc_dmat, sc->ctrlpage_dmamap, 325 sc->ctrlpage, PAGE_SIZE, NULL, BUS_DMA_WAITOK); 326 } 327 if (err != 0) { 328 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 329 } 330 sc->ctrlpage_dsaddr = sc->ctrlpage_dmamap->dm_segs[0].ds_addr; 331 memset(sc->ctrlpage, 0, PAGE_SIZE); 332 333 /* Set up pointers to start of each queue in kernel addr space. 334 * Each descriptor queue or status queue entry uses 2 words 335 */ 336 sc->TXDQ = (uint32_t *)sc->ctrlpage; 337 sc->TXDQ_cur = sc->TXDQ; 338 sc->TXDQ_avail = TX_QLEN - 1; 339 sc->TXStsQ = &sc->TXDQ[TX_QLEN * 2]; 340 sc->TXStsQ_cur = sc->TXStsQ; 341 sc->RXDQ = &sc->TXStsQ[TX_QLEN]; 342 sc->RXStsQ = &sc->RXDQ[RX_QLEN * 2]; 343 sc->RXStsQ_cur = sc->RXStsQ; 344 345 /* Program each queue's start addr, cur addr, and len registers 346 * with the physical addresses. 347 */ 348 addr = (char *)sc->ctrlpage_dmamap->dm_segs[0].ds_addr; 349 EPE_WRITE(TXDQBAdd, (uint32_t)addr); 350 EPE_WRITE(TXDQCurAdd, (uint32_t)addr); 351 EPE_WRITE(TXDQBLen, TX_QLEN * 2 * sizeof(uint32_t)); 352 353 addr += (sc->TXStsQ - sc->TXDQ) * sizeof(uint32_t); 354 EPE_WRITE(TXStsQBAdd, (uint32_t)addr); 355 EPE_WRITE(TXStsQCurAdd, (uint32_t)addr); 356 EPE_WRITE(TXStsQBLen, TX_QLEN * sizeof(uint32_t)); 357 358 addr += (sc->RXDQ - sc->TXStsQ) * sizeof(uint32_t); 359 EPE_WRITE(RXDQBAdd, (uint32_t)addr); 360 EPE_WRITE(RXDCurAdd, (uint32_t)addr); 361 EPE_WRITE(RXDQBLen, RX_QLEN * 2 * sizeof(uint32_t)); 362 363 addr += (sc->RXStsQ - sc->RXDQ) * sizeof(uint32_t); 364 EPE_WRITE(RXStsQBAdd, (uint32_t)addr); 365 EPE_WRITE(RXStsQCurAdd, (uint32_t)addr); 366 EPE_WRITE(RXStsQBLen, RX_QLEN * 2 * sizeof(uint32_t)); 367 368 /* Populate the RXDQ with mbufs */ 369 for (i = 0; i < RX_QLEN; i++) { 370 struct mbuf *m; 371 372 bus_dmamap_create(sc->sc_dmat, MCLBYTES, TX_QLEN/4, MCLBYTES, 373 0, BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 374 MGETHDR(m, M_WAIT, MT_DATA); 375 MCLGET(m, M_WAIT); 376 sc->rxq[i].m = m; 377 bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 378 m->m_ext.ext_buf, MCLBYTES, NULL, BUS_DMA_WAITOK); 379 380 sc->RXDQ[i * 2] = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr; 381 sc->RXDQ[i * 2 + 1] = (i << 16) | MCLBYTES; 382 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 383 MCLBYTES, BUS_DMASYNC_PREREAD); 384 } 385 386 for (i = 0; i < TX_QLEN; i++) { 387 bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 388 (BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW), 389 &sc->txq[i].m_dmamap); 390 sc->txq[i].m = NULL; 391 sc->TXDQ[i * 2 + 1] = (i << 16); 392 } 393 394 /* Divide HCLK by 32 for MDC clock */ 395 if (device_cfdata(sc->sc_dev)->cf_flags) 396 mdcdiv = device_cfdata(sc->sc_dev)->cf_flags; 397 EPE_WRITE(SelfCtl, (SelfCtl_MDCDIV(mdcdiv) | SelfCtl_PSPRS)); 398 399 sc->sc_mii.mii_ifp = ifp; 400 sc->sc_mii.mii_readreg = epe_mii_readreg; 401 sc->sc_mii.mii_writereg = epe_mii_writereg; 402 sc->sc_mii.mii_statchg = epe_statchg; 403 sc->sc_ec.ec_mii = &sc->sc_mii; 404 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, epe_mediachange, 405 ether_mediastatus); 406 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 407 MII_OFFSET_ANY, 0); 408 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 409 410 EPE_WRITE(BMCtl, BMCtl_RxEn | BMCtl_TxEn); 411 EPE_WRITE(IntEn, IntEn_REOFIE); 412 /* maximum valid max frame length */ 413 EPE_WRITE(MaxFrmLen, (0x7ff << 16) | MHLEN); 414 /* wait for receiver ready */ 415 while ((EPE_READ(BMSts) & BMSts_RxAct) == 0) 416 continue; 417 /* enqueue the entries in RXStsQ and RXDQ */ 418 CTRLPAGE_DMASYNC(0, sc->ctrlpage_dmamap->dm_mapsize, 419 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 420 EPE_WRITE(RXDEnq, RX_QLEN - 1); 421 EPE_WRITE(RXStsEnq, RX_QLEN - 1); 422 423 /* 424 * We can support 802.1Q VLAN-sized frames. 425 */ 426 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 427 428 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 429 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 430 ifp->if_ioctl = epe_ifioctl; 431 ifp->if_start = epe_ifstart; 432 ifp->if_watchdog = epe_ifwatchdog; 433 ifp->if_init = epe_ifinit; 434 ifp->if_stop = epe_ifstop; 435 ifp->if_timer = 0; 436 ifp->if_softc = sc; 437 IFQ_SET_READY(&ifp->if_snd); 438 if_attach(ifp); 439 if_deferred_start_init(ifp, NULL); 440 ether_ifattach(ifp, (sc)->sc_enaddr); 441 } 442 443 static int 444 epe_mediachange(struct ifnet *ifp) 445 { 446 if (ifp->if_flags & IFF_UP) 447 epe_ifinit(ifp); 448 return 0; 449 } 450 451 int 452 epe_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 453 { 454 uint32_t d; 455 456 d = EPE_READ(SelfCtl); 457 EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */ 458 EPE_WRITE(MIICmd, (MIICmd_READ | (phy << 5) | reg)); 459 while (EPE_READ(MIISts) & MIISts_BUSY) 460 ; 461 *val = EPE_READ(MIIData) & 0xffff; 462 EPE_WRITE(SelfCtl, d); /* restore old value */ 463 return 0; 464 } 465 466 int 467 epe_mii_writereg(device_t self, int phy, int reg, uint16_t val) 468 { 469 uint32_t d; 470 471 d = EPE_READ(SelfCtl); 472 EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */ 473 EPE_WRITE(MIIData, val); 474 EPE_WRITE(MIICmd, (MIICmd_WRITE | (phy << 5) | reg)); 475 while (EPE_READ(MIISts) & MIISts_BUSY) 476 ; 477 EPE_WRITE(SelfCtl, d); /* restore old value */ 478 479 return 0; 480 } 481 482 void 483 epe_statchg(struct ifnet *ifp) 484 { 485 struct epe_softc *sc = ifp->if_softc; 486 uint32_t reg; 487 488 /* 489 * We must keep the MAC and the PHY in sync as 490 * to the status of full-duplex! 491 */ 492 reg = EPE_READ(TestCtl); 493 if (sc->sc_mii.mii_media_active & IFM_FDX) 494 reg |= TestCtl_MFDX; 495 else 496 reg &= ~TestCtl_MFDX; 497 EPE_WRITE(TestCtl, reg); 498 } 499 500 void 501 epe_tick(void *arg) 502 { 503 struct epe_softc* sc = (struct epe_softc *)arg; 504 struct ifnet * ifp = &sc->sc_ec.ec_if; 505 int s; 506 uint32_t misses; 507 508 ifp->if_collisions += EPE_READ(TXCollCnt); 509 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 510 misses = EPE_READ(RXMissCnt); 511 if (misses > 0) 512 printf("%s: %d rx misses\n", device_xname(sc->sc_dev), misses); 513 514 s = splnet(); 515 if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 516 epe_ifstart(ifp); 517 } 518 splx(s); 519 520 mii_tick(&sc->sc_mii); 521 callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc); 522 } 523 524 525 static int 526 epe_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 527 { 528 int s, error; 529 530 s = splnet(); 531 error = ether_ioctl(ifp, cmd, data); 532 if (error == ENETRESET) { 533 if (ifp->if_flags & IFF_RUNNING) 534 epe_setaddr(ifp); 535 error = 0; 536 } 537 splx(s); 538 return error; 539 } 540 541 static void 542 epe_ifstart(struct ifnet *ifp) 543 { 544 struct epe_softc *sc = (struct epe_softc *)ifp->if_softc; 545 struct mbuf *m; 546 bus_dma_segment_t *segs; 547 int s, bi, err, nsegs, ndq; 548 549 s = splnet(); 550 start: 551 ndq = 0; 552 if (sc->TXDQ_avail == 0) { 553 if (epe_gctx(sc) == 0) { 554 /* Enable End-Of-TX-Chain interrupt */ 555 EPE_WRITE(IntEn, IntEn_REOFIE | IntEn_ECIE); 556 ifp->if_flags |= IFF_OACTIVE; 557 ifp->if_timer = 10; 558 splx(s); 559 return; 560 } 561 } 562 563 bi = sc->TXDQ_cur - sc->TXDQ; 564 565 IFQ_POLL(&ifp->if_snd, m); 566 if (m == NULL) { 567 splx(s); 568 return; 569 } 570 more: 571 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 572 BUS_DMA_NOWAIT)) || 573 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 574 sc->txq[bi].m_dmamap->dm_nsegs > (sc->TXDQ_avail - ndq)) { 575 /* Copy entire mbuf chain to new and 32-bit aligned storage */ 576 struct mbuf *mn; 577 578 if (err == 0) 579 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 580 581 MGETHDR(mn, M_DONTWAIT, MT_DATA); 582 if (mn == NULL) goto stop; 583 if (m->m_pkthdr.len > (MHLEN & (~0x3))) { 584 MCLGET(mn, M_DONTWAIT); 585 if ((mn->m_flags & M_EXT) == 0) { 586 m_freem(mn); 587 goto stop; 588 } 589 } 590 mn->m_data = (void *)(((uint32_t)mn->m_data + 0x3) & (~0x3)); 591 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 592 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 593 IFQ_DEQUEUE(&ifp->if_snd, m); 594 m_freem(m); 595 m = mn; 596 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 597 BUS_DMA_NOWAIT); 598 } else { 599 IFQ_DEQUEUE(&ifp->if_snd, m); 600 } 601 602 bpf_mtap(ifp, m, BPF_D_OUT); 603 604 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 605 segs = sc->txq[bi].m_dmamap->dm_segs; 606 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 607 sc->txq[bi].m_dmamap->dm_mapsize, 608 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 609 610 /* XXX: This driver hasn't been tested w/nsegs > 1 */ 611 while (nsegs > 0) { 612 nsegs--; 613 sc->txq[bi].m = m; 614 sc->TXDQ[bi * 2] = segs->ds_addr; 615 if (nsegs == 0) 616 sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16) | 617 (1 << 31); 618 else 619 sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16); 620 segs++; 621 bi = (bi + 1) % TX_QLEN; 622 ndq++; 623 } 624 625 626 /* 627 * Enqueue another. Don't do more than half the available 628 * descriptors before telling the MAC about them 629 */ 630 if ((sc->TXDQ_avail - ndq) > 0 && ndq < TX_QLEN / 2) { 631 IFQ_POLL(&ifp->if_snd, m); 632 if (m != NULL) 633 goto more; 634 } 635 stop: 636 if (ndq > 0) { 637 sc->TXDQ_avail -= ndq; 638 sc->TXDQ_cur = &sc->TXDQ[bi]; 639 CTRLPAGE_DMASYNC(0, TX_QLEN * 2 * sizeof(uint32_t), 640 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 641 EPE_WRITE(TXDEnq, ndq); 642 } 643 644 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 645 goto start; 646 647 splx(s); 648 return; 649 } 650 651 static void 652 epe_ifwatchdog(struct ifnet *ifp) 653 { 654 struct epe_softc *sc = (struct epe_softc *)ifp->if_softc; 655 656 if ((ifp->if_flags & IFF_RUNNING) == 0) 657 return; 658 printf("%s: device timeout, BMCtl = 0x%08x, BMSts = 0x%08x\n", 659 device_xname(sc->sc_dev), EPE_READ(BMCtl), EPE_READ(BMSts)); 660 } 661 662 static int 663 epe_ifinit(struct ifnet *ifp) 664 { 665 struct epe_softc *sc = ifp->if_softc; 666 int rc, s = splnet(); 667 668 callout_stop(&sc->epe_tick_ch); 669 EPE_WRITE(RXCtl, RXCtl_IA0 | RXCtl_BA | RXCtl_RCRCA | RXCtl_SRxON); 670 EPE_WRITE(TXCtl, TXCtl_STxON); 671 EPE_WRITE(GIIntMsk, GIIntMsk_INT); /* start interrupting */ 672 673 if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 674 rc = 0; 675 else if (rc != 0) 676 goto out; 677 678 callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc); 679 ifp->if_flags |= IFF_RUNNING; 680 out: 681 splx(s); 682 return 0; 683 } 684 685 static void 686 epe_ifstop(struct ifnet *ifp, int disable) 687 { 688 struct epe_softc *sc = ifp->if_softc; 689 690 691 EPE_WRITE(RXCtl, 0); 692 EPE_WRITE(TXCtl, 0); 693 EPE_WRITE(GIIntMsk, 0); 694 callout_stop(&sc->epe_tick_ch); 695 696 /* Down the MII. */ 697 mii_down(&sc->sc_mii); 698 699 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 700 ifp->if_timer = 0; 701 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 702 } 703 704 static void 705 epe_setaddr(struct ifnet *ifp) 706 { 707 struct epe_softc *sc = ifp->if_softc; 708 struct ethercom *ec = &sc->sc_ec; 709 struct ether_multi *enm; 710 struct ether_multistep step; 711 uint8_t ias[2][ETHER_ADDR_LEN]; 712 uint32_t h, nma = 0, hashes[2] = { 0, 0 }; 713 uint32_t rxctl = EPE_READ(RXCtl); 714 715 /* disable receiver temporarily */ 716 EPE_WRITE(RXCtl, rxctl & ~RXCtl_SRxON); 717 718 rxctl &= ~(RXCtl_MA | RXCtl_PA | RXCtl_IA2 | RXCtl_IA3); 719 720 if (ifp->if_flags & IFF_PROMISC) 721 rxctl |= RXCtl_PA; 722 723 ifp->if_flags &= ~IFF_ALLMULTI; 724 725 ETHER_LOCK(ec); 726 ETHER_FIRST_MULTI(step, ec, enm); 727 while (enm != NULL) { 728 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 729 /* 730 * We must listen to a range of multicast addresses. 731 * For now, just accept all multicasts, rather than 732 * trying to set only those filter bits needed to match 733 * the range. (At this time, the only use of address 734 * ranges is for IP multicast routing, for which the 735 * range is big enough to require all bits set.) 736 */ 737 rxctl &= ~(RXCtl_IA2 | RXCtl_IA3); 738 rxctl |= RXCtl_MA; 739 hashes[0] = 0xffffffffUL; 740 hashes[1] = 0xffffffffUL; 741 ifp->if_flags |= IFF_ALLMULTI; 742 break; 743 } 744 745 if (nma < 2) { 746 /* We can program 2 perfect address filters for mcast */ 747 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 748 rxctl |= (1 << (nma + 2)); 749 } else { 750 /* 751 * XXX: Datasheet is not very clear here, I'm not sure 752 * if I'm doing this right. --joff 753 */ 754 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 755 756 /* Just want the 6 most-significant bits. */ 757 h = h >> 26; 758 759 hashes[ h / 32 ] |= (1 << (h % 32)); 760 rxctl |= RXCtl_MA; 761 } 762 ETHER_NEXT_MULTI(step, enm); 763 nma++; 764 } 765 ETHER_UNLOCK(ec); 766 767 EPE_WRITE(AFP, 0); 768 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 769 sc->sc_enaddr, ETHER_ADDR_LEN); 770 if (rxctl & RXCtl_IA2) { 771 EPE_WRITE(AFP, 2); 772 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 773 ias[0], ETHER_ADDR_LEN); 774 } 775 if (rxctl & RXCtl_IA3) { 776 EPE_WRITE(AFP, 3); 777 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 778 ias[1], ETHER_ADDR_LEN); 779 } 780 if (hashes[0] != 0 && hashes[1] != 0) { 781 EPE_WRITE(AFP, 7); 782 EPE_WRITE(HashTbl, hashes[0]); 783 EPE_WRITE(HashTbl + 4, hashes[1]); 784 } 785 EPE_WRITE(RXCtl, rxctl); 786 } 787
Indexes created Tue Sep 30 11:09:46 GMT 2025