epe.c revision 1.44
1 /* $NetBSD: epe.c,v 1.44 2019/05/30 02:32:17 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Jesse Off 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: epe.c,v 1.44 2019/05/30 02:32:17 msaitoh Exp $"); 31 32 #include <sys/types.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/ioctl.h> 36 #include <sys/kernel.h> 37 #include <sys/proc.h> 38 #include <sys/malloc.h> 39 #include <sys/time.h> 40 #include <sys/device.h> 41 #include <uvm/uvm_extern.h> 42 43 #include <sys/bus.h> 44 #include <machine/intr.h> 45 46 #include <arm/cpufunc.h> 47 48 #include <arm/ep93xx/epsocvar.h> 49 #include <arm/ep93xx/ep93xxvar.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_types.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 #include <net/bpf.h> 57 58 #include <dev/mii/mii.h> 59 #include <dev/mii/miivar.h> 60 61 #ifdef INET 62 #include <netinet/in.h> 63 #include <netinet/in_systm.h> 64 #include <netinet/in_var.h> 65 #include <netinet/ip.h> 66 #include <netinet/if_inarp.h> 67 #endif 68 69 #include <arm/ep93xx/ep93xxreg.h> 70 #include <arm/ep93xx/epereg.h> 71 #include <arm/ep93xx/epevar.h> 72 73 #define DEFAULT_MDCDIV 32 74 75 #ifndef EPE_FAST 76 #define EPE_FAST 77 #endif 78 79 #ifndef EPE_FAST 80 #define EPE_READ(x) \ 81 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x)) 82 #define EPE_WRITE(x, y) \ 83 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x), (y)) 84 #define CTRLPAGE_DMASYNC(x, y, z) \ 85 bus_dmamap_sync(sc->sc_dmat, sc->ctrlpage_dmamap, (x), (y), (z)) 86 #else 87 #define EPE_READ(x) *(volatile uint32_t *) \ 88 (EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x)) 89 #define EPE_WRITE(x, y) *(volatile uint32_t *) \ 90 (EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x)) = y 91 #define CTRLPAGE_DMASYNC(x, y, z) 92 #endif /* ! EPE_FAST */ 93 94 static int epe_match(device_t , cfdata_t, void *); 95 static void epe_attach(device_t, device_t, void *); 96 static void epe_init(struct epe_softc *); 97 static int epe_intr(void* arg); 98 static int epe_gctx(struct epe_softc *); 99 static int epe_mediachange(struct ifnet *); 100 int epe_mii_readreg (device_t, int, int, uint16_t *); 101 int epe_mii_writereg (device_t, int, int, uint16_t); 102 void epe_statchg (struct ifnet *); 103 void epe_tick (void *); 104 static int epe_ifioctl (struct ifnet *, u_long, void *); 105 static void epe_ifstart (struct ifnet *); 106 static void epe_ifwatchdog (struct ifnet *); 107 static int epe_ifinit (struct ifnet *); 108 static void epe_ifstop (struct ifnet *, int); 109 static void epe_setaddr (struct ifnet *); 110 111 CFATTACH_DECL_NEW(epe, sizeof(struct epe_softc), 112 epe_match, epe_attach, NULL, NULL); 113 114 static int 115 epe_match(device_t parent, cfdata_t match, void *aux) 116 { 117 return 2; 118 } 119 120 static void 121 epe_attach(device_t parent, device_t self, void *aux) 122 { 123 struct epe_softc *sc = device_private(self); 124 struct epsoc_attach_args *sa; 125 prop_data_t enaddr; 126 127 aprint_normal("\n"); 128 sa = aux; 129 sc->sc_dev = self; 130 sc->sc_iot = sa->sa_iot; 131 sc->sc_intr = sa->sa_intr; 132 sc->sc_dmat = sa->sa_dmat; 133 134 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 135 0, &sc->sc_ioh)) 136 panic("%s: Cannot map registers", device_xname(self)); 137 138 /* Fetch the Ethernet address from property if set. */ 139 enaddr = prop_dictionary_get(device_properties(self), "mac-address"); 140 if (enaddr != NULL) { 141 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 142 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 143 memcpy(sc->sc_enaddr, prop_data_data_nocopy(enaddr), 144 ETHER_ADDR_LEN); 145 bus_space_write_4(sc->sc_iot, sc->sc_ioh, EPE_AFP, 0); 146 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 147 sc->sc_enaddr, ETHER_ADDR_LEN); 148 } 149 150 ep93xx_intr_establish(sc->sc_intr, IPL_NET, epe_intr, sc); 151 epe_init(sc); 152 } 153 154 static int 155 epe_gctx(struct epe_softc *sc) 156 { 157 struct ifnet * ifp = &sc->sc_ec.ec_if; 158 uint32_t *cur, ndq = 0; 159 160 /* Handle transmit completions */ 161 cur = (uint32_t *)(EPE_READ(TXStsQCurAdd) - 162 sc->ctrlpage_dsaddr + (char*)sc->ctrlpage); 163 164 if (sc->TXStsQ_cur != cur) { 165 CTRLPAGE_DMASYNC(TX_QLEN * 2 * sizeof(uint32_t), 166 TX_QLEN * sizeof(uint32_t), BUS_DMASYNC_PREREAD); 167 } else 168 return 0; 169 170 do { 171 uint32_t tbi = *sc->TXStsQ_cur & 0x7fff; 172 struct mbuf *m = sc->txq[tbi].m; 173 174 if ((*sc->TXStsQ_cur & TXStsQ_TxWE) == 0) 175 ifp->if_oerrors++; 176 177 bus_dmamap_unload(sc->sc_dmat, sc->txq[tbi].m_dmamap); 178 m_freem(m); 179 do { 180 sc->txq[tbi].m = NULL; 181 ndq++; 182 tbi = (tbi + 1) % TX_QLEN; 183 } while (sc->txq[tbi].m == m); 184 185 ifp->if_opackets++; 186 sc->TXStsQ_cur++; 187 if (sc->TXStsQ_cur >= sc->TXStsQ + TX_QLEN) { 188 sc->TXStsQ_cur = sc->TXStsQ; 189 } 190 } while (sc->TXStsQ_cur != cur); 191 192 sc->TXDQ_avail += ndq; 193 if (ifp->if_flags & IFF_OACTIVE) { 194 ifp->if_flags &= ~IFF_OACTIVE; 195 /* Disable end-of-tx-chain interrupt */ 196 EPE_WRITE(IntEn, IntEn_REOFIE); 197 } 198 return ndq; 199 } 200 201 static int 202 epe_intr(void *arg) 203 { 204 struct epe_softc *sc = (struct epe_softc *)arg; 205 struct ifnet * ifp = &sc->sc_ec.ec_if; 206 uint32_t ndq = 0, irq, *cur; 207 208 irq = EPE_READ(IntStsC); 209 begin: 210 cur = (uint32_t *)(EPE_READ(RXStsQCurAdd) - 211 sc->ctrlpage_dsaddr + (char*)sc->ctrlpage); 212 CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(uint32_t), 213 RX_QLEN * 4 * sizeof(uint32_t), 214 BUS_DMASYNC_PREREAD); 215 while (sc->RXStsQ_cur != cur) { 216 if ((sc->RXStsQ_cur[0] & (RXStsQ_RWE | RXStsQ_RFP |RXStsQ_EOB)) 217 == (RXStsQ_RWE | RXStsQ_RFP | RXStsQ_EOB)) { 218 uint32_t bi = (sc->RXStsQ_cur[1] >> 16) & 0x7fff; 219 uint32_t fl = sc->RXStsQ_cur[1] & 0xffff; 220 struct mbuf *m; 221 222 MGETHDR(m, M_DONTWAIT, MT_DATA); 223 if (m != NULL) MCLGET(m, M_DONTWAIT); 224 if (m != NULL && (m->m_flags & M_EXT)) { 225 bus_dmamap_unload(sc->sc_dmat, 226 sc->rxq[bi].m_dmamap); 227 m_set_rcvif(sc->rxq[bi].m, ifp); 228 sc->rxq[bi].m->m_pkthdr.len = 229 sc->rxq[bi].m->m_len = fl; 230 if_percpuq_enqueue(ifp->if_percpuq, 231 sc->rxq[bi].m); 232 sc->rxq[bi].m = m; 233 bus_dmamap_load(sc->sc_dmat, 234 sc->rxq[bi].m_dmamap, 235 m->m_ext.ext_buf, MCLBYTES, 236 NULL, BUS_DMA_NOWAIT); 237 sc->RXDQ[bi * 2] = 238 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr; 239 } else { 240 /* Drop packets until we can get replacement 241 * empty mbufs for the RXDQ. 242 */ 243 if (m != NULL) 244 m_freem(m); 245 246 ifp->if_ierrors++; 247 } 248 } else 249 ifp->if_ierrors++; 250 251 ndq++; 252 253 sc->RXStsQ_cur += 2; 254 if (sc->RXStsQ_cur >= sc->RXStsQ + (RX_QLEN * 2)) 255 sc->RXStsQ_cur = sc->RXStsQ; 256 } 257 258 if (ndq > 0) { 259 ifp->if_ipackets += ndq; 260 CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(uint32_t), 261 RX_QLEN * 4 * sizeof(uint32_t), 262 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 263 EPE_WRITE(RXStsEnq, ndq); 264 EPE_WRITE(RXDEnq, ndq); 265 ndq = 0; 266 } 267 268 if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 269 if_schedule_deferred_start(ifp); 270 } 271 272 irq = EPE_READ(IntStsC); 273 if ((irq & (IntSts_RxSQ | IntSts_ECI)) != 0) 274 goto begin; 275 276 return 1; 277 } 278 279 280 static void 281 epe_init(struct epe_softc *sc) 282 { 283 bus_dma_segment_t segs; 284 char *addr; 285 int rsegs, err, i; 286 struct ifnet * ifp = &sc->sc_ec.ec_if; 287 struct mii_data *mii = &sc->sc_mii; 288 int mdcdiv = DEFAULT_MDCDIV; 289 290 callout_init(&sc->epe_tick_ch, 0); 291 292 /* Select primary Individual Address in Address Filter Pointer */ 293 EPE_WRITE(AFP, 0); 294 /* Read ethernet MAC, should already be set by bootrom */ 295 bus_space_read_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 296 sc->sc_enaddr, ETHER_ADDR_LEN); 297 aprint_normal_dev(sc->sc_dev, "MAC address %s\n", 298 ether_sprintf(sc->sc_enaddr)); 299 300 /* Soft Reset the MAC */ 301 EPE_WRITE(SelfCtl, SelfCtl_RESET); 302 while (EPE_READ(SelfCtl) & SelfCtl_RESET) 303 ; 304 305 /* suggested magic initialization values from datasheet */ 306 EPE_WRITE(RXBufThrshld, 0x800040); 307 EPE_WRITE(TXBufThrshld, 0x200010); 308 EPE_WRITE(RXStsThrshld, 0x40002); 309 EPE_WRITE(TXStsThrshld, 0x40002); 310 EPE_WRITE(RXDThrshld, 0x40002); 311 EPE_WRITE(TXDThrshld, 0x40002); 312 313 /* Allocate a page of memory for descriptor and status queues */ 314 err = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, 0, PAGE_SIZE, 315 &segs, 1, &rsegs, BUS_DMA_WAITOK); 316 if (err == 0) { 317 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, PAGE_SIZE, 318 &sc->ctrlpage, (BUS_DMA_WAITOK | BUS_DMA_COHERENT)); 319 } 320 if (err == 0) { 321 err = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 322 0, BUS_DMA_WAITOK, &sc->ctrlpage_dmamap); 323 } 324 if (err == 0) { 325 err = bus_dmamap_load(sc->sc_dmat, sc->ctrlpage_dmamap, 326 sc->ctrlpage, PAGE_SIZE, NULL, BUS_DMA_WAITOK); 327 } 328 if (err != 0) { 329 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 330 } 331 sc->ctrlpage_dsaddr = sc->ctrlpage_dmamap->dm_segs[0].ds_addr; 332 memset(sc->ctrlpage, 0, PAGE_SIZE); 333 334 /* Set up pointers to start of each queue in kernel addr space. 335 * Each descriptor queue or status queue entry uses 2 words 336 */ 337 sc->TXDQ = (uint32_t *)sc->ctrlpage; 338 sc->TXDQ_cur = sc->TXDQ; 339 sc->TXDQ_avail = TX_QLEN - 1; 340 sc->TXStsQ = &sc->TXDQ[TX_QLEN * 2]; 341 sc->TXStsQ_cur = sc->TXStsQ; 342 sc->RXDQ = &sc->TXStsQ[TX_QLEN]; 343 sc->RXStsQ = &sc->RXDQ[RX_QLEN * 2]; 344 sc->RXStsQ_cur = sc->RXStsQ; 345 346 /* Program each queue's start addr, cur addr, and len registers 347 * with the physical addresses. 348 */ 349 addr = (char *)sc->ctrlpage_dmamap->dm_segs[0].ds_addr; 350 EPE_WRITE(TXDQBAdd, (uint32_t)addr); 351 EPE_WRITE(TXDQCurAdd, (uint32_t)addr); 352 EPE_WRITE(TXDQBLen, TX_QLEN * 2 * sizeof(uint32_t)); 353 354 addr += (sc->TXStsQ - sc->TXDQ) * sizeof(uint32_t); 355 EPE_WRITE(TXStsQBAdd, (uint32_t)addr); 356 EPE_WRITE(TXStsQCurAdd, (uint32_t)addr); 357 EPE_WRITE(TXStsQBLen, TX_QLEN * sizeof(uint32_t)); 358 359 addr += (sc->RXDQ - sc->TXStsQ) * sizeof(uint32_t); 360 EPE_WRITE(RXDQBAdd, (uint32_t)addr); 361 EPE_WRITE(RXDCurAdd, (uint32_t)addr); 362 EPE_WRITE(RXDQBLen, RX_QLEN * 2 * sizeof(uint32_t)); 363 364 addr += (sc->RXStsQ - sc->RXDQ) * sizeof(uint32_t); 365 EPE_WRITE(RXStsQBAdd, (uint32_t)addr); 366 EPE_WRITE(RXStsQCurAdd, (uint32_t)addr); 367 EPE_WRITE(RXStsQBLen, RX_QLEN * 2 * sizeof(uint32_t)); 368 369 /* Populate the RXDQ with mbufs */ 370 for (i = 0; i < RX_QLEN; i++) { 371 struct mbuf *m; 372 373 bus_dmamap_create(sc->sc_dmat, MCLBYTES, TX_QLEN/4, MCLBYTES, 374 0, BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 375 MGETHDR(m, M_WAIT, MT_DATA); 376 MCLGET(m, M_WAIT); 377 sc->rxq[i].m = m; 378 bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 379 m->m_ext.ext_buf, MCLBYTES, NULL, BUS_DMA_WAITOK); 380 381 sc->RXDQ[i * 2] = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr; 382 sc->RXDQ[i * 2 + 1] = (i << 16) | MCLBYTES; 383 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 384 MCLBYTES, BUS_DMASYNC_PREREAD); 385 } 386 387 for (i = 0; i < TX_QLEN; i++) { 388 bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 389 (BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW), 390 &sc->txq[i].m_dmamap); 391 sc->txq[i].m = NULL; 392 sc->TXDQ[i * 2 + 1] = (i << 16); 393 } 394 395 /* Divide HCLK by 32 for MDC clock */ 396 if (device_cfdata(sc->sc_dev)->cf_flags) 397 mdcdiv = device_cfdata(sc->sc_dev)->cf_flags; 398 EPE_WRITE(SelfCtl, (SelfCtl_MDCDIV(mdcdiv) | SelfCtl_PSPRS)); 399 400 mii->mii_ifp = ifp; 401 mii->mii_readreg = epe_mii_readreg; 402 mii->mii_writereg = epe_mii_writereg; 403 mii->mii_statchg = epe_statchg; 404 sc->sc_ec.ec_mii = mii; 405 ifmedia_init(&mii->mii_media, IFM_IMASK, epe_mediachange, 406 ether_mediastatus); 407 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 408 MII_OFFSET_ANY, 0); 409 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 410 411 EPE_WRITE(BMCtl, BMCtl_RxEn | BMCtl_TxEn); 412 EPE_WRITE(IntEn, IntEn_REOFIE); 413 /* maximum valid max frame length */ 414 EPE_WRITE(MaxFrmLen, (0x7ff << 16) | MHLEN); 415 /* wait for receiver ready */ 416 while ((EPE_READ(BMSts) & BMSts_RxAct) == 0) 417 continue; 418 /* enqueue the entries in RXStsQ and RXDQ */ 419 CTRLPAGE_DMASYNC(0, sc->ctrlpage_dmamap->dm_mapsize, 420 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 421 EPE_WRITE(RXDEnq, RX_QLEN - 1); 422 EPE_WRITE(RXStsEnq, RX_QLEN - 1); 423 424 /* 425 * We can support 802.1Q VLAN-sized frames. 426 */ 427 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 428 429 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 430 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 431 ifp->if_ioctl = epe_ifioctl; 432 ifp->if_start = epe_ifstart; 433 ifp->if_watchdog = epe_ifwatchdog; 434 ifp->if_init = epe_ifinit; 435 ifp->if_stop = epe_ifstop; 436 ifp->if_timer = 0; 437 ifp->if_softc = sc; 438 IFQ_SET_READY(&ifp->if_snd); 439 if_attach(ifp); 440 if_deferred_start_init(ifp, NULL); 441 ether_ifattach(ifp, (sc)->sc_enaddr); 442 } 443 444 static int 445 epe_mediachange(struct ifnet *ifp) 446 { 447 if (ifp->if_flags & IFF_UP) 448 epe_ifinit(ifp); 449 return 0; 450 } 451 452 int 453 epe_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 454 { 455 uint32_t d; 456 457 d = EPE_READ(SelfCtl); 458 EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */ 459 EPE_WRITE(MIICmd, (MIICmd_READ | (phy << 5) | reg)); 460 while (EPE_READ(MIISts) & MIISts_BUSY) 461 ; 462 *val = EPE_READ(MIIData) & 0xffff; 463 EPE_WRITE(SelfCtl, d); /* restore old value */ 464 return 0; 465 } 466 467 int 468 epe_mii_writereg(device_t self, int phy, int reg, uint16_t val) 469 { 470 uint32_t d; 471 472 d = EPE_READ(SelfCtl); 473 EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */ 474 EPE_WRITE(MIIData, val); 475 EPE_WRITE(MIICmd, (MIICmd_WRITE | (phy << 5) | reg)); 476 while (EPE_READ(MIISts) & MIISts_BUSY) 477 ; 478 EPE_WRITE(SelfCtl, d); /* restore old value */ 479 480 return 0; 481 } 482 483 void 484 epe_statchg(struct ifnet *ifp) 485 { 486 struct epe_softc *sc = ifp->if_softc; 487 uint32_t reg; 488 489 /* 490 * We must keep the MAC and the PHY in sync as 491 * to the status of full-duplex! 492 */ 493 reg = EPE_READ(TestCtl); 494 if (sc->sc_mii.mii_media_active & IFM_FDX) 495 reg |= TestCtl_MFDX; 496 else 497 reg &= ~TestCtl_MFDX; 498 EPE_WRITE(TestCtl, reg); 499 } 500 501 void 502 epe_tick(void *arg) 503 { 504 struct epe_softc* sc = (struct epe_softc *)arg; 505 struct ifnet * ifp = &sc->sc_ec.ec_if; 506 int s; 507 uint32_t misses; 508 509 ifp->if_collisions += EPE_READ(TXCollCnt); 510 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 511 misses = EPE_READ(RXMissCnt); 512 if (misses > 0) 513 printf("%s: %d rx misses\n", device_xname(sc->sc_dev), misses); 514 515 s = splnet(); 516 if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 517 epe_ifstart(ifp); 518 } 519 splx(s); 520 521 mii_tick(&sc->sc_mii); 522 callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc); 523 } 524 525 526 static int 527 epe_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 528 { 529 int s, error; 530 531 s = splnet(); 532 error = ether_ioctl(ifp, cmd, data); 533 if (error == ENETRESET) { 534 if (ifp->if_flags & IFF_RUNNING) 535 epe_setaddr(ifp); 536 error = 0; 537 } 538 splx(s); 539 return error; 540 } 541 542 static void 543 epe_ifstart(struct ifnet *ifp) 544 { 545 struct epe_softc *sc = (struct epe_softc *)ifp->if_softc; 546 struct mbuf *m; 547 bus_dma_segment_t *segs; 548 int s, bi, err, nsegs, ndq; 549 550 s = splnet(); 551 start: 552 ndq = 0; 553 if (sc->TXDQ_avail == 0) { 554 if (epe_gctx(sc) == 0) { 555 /* Enable End-Of-TX-Chain interrupt */ 556 EPE_WRITE(IntEn, IntEn_REOFIE | IntEn_ECIE); 557 ifp->if_flags |= IFF_OACTIVE; 558 ifp->if_timer = 10; 559 splx(s); 560 return; 561 } 562 } 563 564 bi = sc->TXDQ_cur - sc->TXDQ; 565 566 IFQ_POLL(&ifp->if_snd, m); 567 if (m == NULL) { 568 splx(s); 569 return; 570 } 571 more: 572 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 573 BUS_DMA_NOWAIT)) || 574 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 575 sc->txq[bi].m_dmamap->dm_nsegs > (sc->TXDQ_avail - ndq)) { 576 /* Copy entire mbuf chain to new and 32-bit aligned storage */ 577 struct mbuf *mn; 578 579 if (err == 0) 580 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 581 582 MGETHDR(mn, M_DONTWAIT, MT_DATA); 583 if (mn == NULL) goto stop; 584 if (m->m_pkthdr.len > (MHLEN & (~0x3))) { 585 MCLGET(mn, M_DONTWAIT); 586 if ((mn->m_flags & M_EXT) == 0) { 587 m_freem(mn); 588 goto stop; 589 } 590 } 591 mn->m_data = (void *)(((uint32_t)mn->m_data + 0x3) & (~0x3)); 592 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 593 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 594 IFQ_DEQUEUE(&ifp->if_snd, m); 595 m_freem(m); 596 m = mn; 597 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 598 BUS_DMA_NOWAIT); 599 } else { 600 IFQ_DEQUEUE(&ifp->if_snd, m); 601 } 602 603 bpf_mtap(ifp, m, BPF_D_OUT); 604 605 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 606 segs = sc->txq[bi].m_dmamap->dm_segs; 607 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 608 sc->txq[bi].m_dmamap->dm_mapsize, 609 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 610 611 /* XXX: This driver hasn't been tested w/nsegs > 1 */ 612 while (nsegs > 0) { 613 nsegs--; 614 sc->txq[bi].m = m; 615 sc->TXDQ[bi * 2] = segs->ds_addr; 616 if (nsegs == 0) 617 sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16) | 618 (1 << 31); 619 else 620 sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16); 621 segs++; 622 bi = (bi + 1) % TX_QLEN; 623 ndq++; 624 } 625 626 627 /* 628 * Enqueue another. Don't do more than half the available 629 * descriptors before telling the MAC about them 630 */ 631 if ((sc->TXDQ_avail - ndq) > 0 && ndq < TX_QLEN / 2) { 632 IFQ_POLL(&ifp->if_snd, m); 633 if (m != NULL) 634 goto more; 635 } 636 stop: 637 if (ndq > 0) { 638 sc->TXDQ_avail -= ndq; 639 sc->TXDQ_cur = &sc->TXDQ[bi]; 640 CTRLPAGE_DMASYNC(0, TX_QLEN * 2 * sizeof(uint32_t), 641 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 642 EPE_WRITE(TXDEnq, ndq); 643 } 644 645 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 646 goto start; 647 648 splx(s); 649 return; 650 } 651 652 static void 653 epe_ifwatchdog(struct ifnet *ifp) 654 { 655 struct epe_softc *sc = (struct epe_softc *)ifp->if_softc; 656 657 if ((ifp->if_flags & IFF_RUNNING) == 0) 658 return; 659 printf("%s: device timeout, BMCtl = 0x%08x, BMSts = 0x%08x\n", 660 device_xname(sc->sc_dev), EPE_READ(BMCtl), EPE_READ(BMSts)); 661 } 662 663 static int 664 epe_ifinit(struct ifnet *ifp) 665 { 666 struct epe_softc *sc = ifp->if_softc; 667 int rc, s = splnet(); 668 669 callout_stop(&sc->epe_tick_ch); 670 EPE_WRITE(RXCtl, RXCtl_IA0 | RXCtl_BA | RXCtl_RCRCA | RXCtl_SRxON); 671 EPE_WRITE(TXCtl, TXCtl_STxON); 672 EPE_WRITE(GIIntMsk, GIIntMsk_INT); /* start interrupting */ 673 674 if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 675 rc = 0; 676 else if (rc != 0) 677 goto out; 678 679 callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc); 680 ifp->if_flags |= IFF_RUNNING; 681 out: 682 splx(s); 683 return 0; 684 } 685 686 static void 687 epe_ifstop(struct ifnet *ifp, int disable) 688 { 689 struct epe_softc *sc = ifp->if_softc; 690 691 692 EPE_WRITE(RXCtl, 0); 693 EPE_WRITE(TXCtl, 0); 694 EPE_WRITE(GIIntMsk, 0); 695 callout_stop(&sc->epe_tick_ch); 696 697 /* Down the MII. */ 698 mii_down(&sc->sc_mii); 699 700 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 701 ifp->if_timer = 0; 702 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 703 } 704 705 static void 706 epe_setaddr(struct ifnet *ifp) 707 { 708 struct epe_softc *sc = ifp->if_softc; 709 struct ethercom *ec = &sc->sc_ec; 710 struct ether_multi *enm; 711 struct ether_multistep step; 712 uint8_t ias[2][ETHER_ADDR_LEN]; 713 uint32_t h, nma = 0, hashes[2] = { 0, 0 }; 714 uint32_t rxctl = EPE_READ(RXCtl); 715 716 /* disable receiver temporarily */ 717 EPE_WRITE(RXCtl, rxctl & ~RXCtl_SRxON); 718 719 rxctl &= ~(RXCtl_MA | RXCtl_PA | RXCtl_IA2 | RXCtl_IA3); 720 721 if (ifp->if_flags & IFF_PROMISC) 722 rxctl |= RXCtl_PA; 723 724 ifp->if_flags &= ~IFF_ALLMULTI; 725 726 ETHER_LOCK(ec); 727 ETHER_FIRST_MULTI(step, ec, enm); 728 while (enm != NULL) { 729 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 730 /* 731 * We must listen to a range of multicast addresses. 732 * For now, just accept all multicasts, rather than 733 * trying to set only those filter bits needed to match 734 * the range. (At this time, the only use of address 735 * ranges is for IP multicast routing, for which the 736 * range is big enough to require all bits set.) 737 */ 738 rxctl &= ~(RXCtl_IA2 | RXCtl_IA3); 739 rxctl |= RXCtl_MA; 740 hashes[0] = 0xffffffffUL; 741 hashes[1] = 0xffffffffUL; 742 ifp->if_flags |= IFF_ALLMULTI; 743 break; 744 } 745 746 if (nma < 2) { 747 /* We can program 2 perfect address filters for mcast */ 748 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 749 rxctl |= (1 << (nma + 2)); 750 } else { 751 /* 752 * XXX: Datasheet is not very clear here, I'm not sure 753 * if I'm doing this right. --joff 754 */ 755 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 756 757 /* Just want the 6 most-significant bits. */ 758 h = h >> 26; 759 760 hashes[ h / 32 ] |= (1 << (h % 32)); 761 rxctl |= RXCtl_MA; 762 } 763 ETHER_NEXT_MULTI(step, enm); 764 nma++; 765 } 766 ETHER_UNLOCK(ec); 767 768 EPE_WRITE(AFP, 0); 769 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 770 sc->sc_enaddr, ETHER_ADDR_LEN); 771 if (rxctl & RXCtl_IA2) { 772 EPE_WRITE(AFP, 2); 773 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 774 ias[0], ETHER_ADDR_LEN); 775 } 776 if (rxctl & RXCtl_IA3) { 777 EPE_WRITE(AFP, 3); 778 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 779 ias[1], ETHER_ADDR_LEN); 780 } 781 if (hashes[0] != 0 && hashes[1] != 0) { 782 EPE_WRITE(AFP, 7); 783 EPE_WRITE(HashTbl, hashes[0]); 784 EPE_WRITE(HashTbl + 4, hashes[1]); 785 } 786 EPE_WRITE(RXCtl, rxctl); 787 } 788
Indexes created Tue Sep 30 11:09:46 GMT 2025