epe.c revision 1.50
1 /* $NetBSD: epe.c,v 1.50 2022/09/27 06:36:41 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Jesse Off 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: epe.c,v 1.50 2022/09/27 06:36:41 skrll Exp $"); 31 32 #include <sys/types.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/ioctl.h> 36 #include <sys/kernel.h> 37 #include <sys/proc.h> 38 #include <sys/time.h> 39 #include <sys/device.h> 40 #include <uvm/uvm_extern.h> 41 42 #include <sys/bus.h> 43 #include <machine/intr.h> 44 45 #include <arm/cpufunc.h> 46 47 #include <arm/ep93xx/epsocvar.h> 48 #include <arm/ep93xx/ep93xxvar.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_types.h> 53 #include <net/if_media.h> 54 #include <net/if_ether.h> 55 #include <net/bpf.h> 56 57 #include <dev/mii/mii.h> 58 #include <dev/mii/miivar.h> 59 60 #ifdef INET 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/in_var.h> 64 #include <netinet/ip.h> 65 #include <netinet/if_inarp.h> 66 #endif 67 68 #include <arm/ep93xx/ep93xxreg.h> 69 #include <arm/ep93xx/epereg.h> 70 #include <arm/ep93xx/epevar.h> 71 72 #define DEFAULT_MDCDIV 32 73 74 #ifndef EPE_FAST 75 #define EPE_FAST 76 #endif 77 78 #ifndef EPE_FAST 79 #define EPE_READ(x) \ 80 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x)) 81 #define EPE_WRITE(x, y) \ 82 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x), (y)) 83 #define CTRLPAGE_DMASYNC(x, y, z) \ 84 bus_dmamap_sync(sc->sc_dmat, sc->ctrlpage_dmamap, (x), (y), (z)) 85 #else 86 #define EPE_READ(x) *(volatile uint32_t *) \ 87 (EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x)) 88 #define EPE_WRITE(x, y) *(volatile uint32_t *) \ 89 (EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x)) = y 90 #define CTRLPAGE_DMASYNC(x, y, z) 91 #endif /* ! EPE_FAST */ 92 93 static int epe_match(device_t , cfdata_t, void *); 94 static void epe_attach(device_t, device_t, void *); 95 static void epe_init(struct epe_softc *); 96 static int epe_intr(void* arg); 97 static int epe_gctx(struct epe_softc *); 98 int epe_mii_readreg (device_t, int, int, uint16_t *); 99 int epe_mii_writereg (device_t, int, int, uint16_t); 100 void epe_statchg (struct ifnet *); 101 void epe_tick (void *); 102 static int epe_ifioctl (struct ifnet *, u_long, void *); 103 static void epe_ifstart (struct ifnet *); 104 static void epe_ifwatchdog (struct ifnet *); 105 static int epe_ifinit (struct ifnet *); 106 static void epe_ifstop (struct ifnet *, int); 107 static void epe_setaddr (struct ifnet *); 108 109 CFATTACH_DECL_NEW(epe, sizeof(struct epe_softc), 110 epe_match, epe_attach, NULL, NULL); 111 112 static int 113 epe_match(device_t parent, cfdata_t match, void *aux) 114 { 115 return 2; 116 } 117 118 static void 119 epe_attach(device_t parent, device_t self, void *aux) 120 { 121 struct epe_softc *sc = device_private(self); 122 struct epsoc_attach_args *sa; 123 prop_data_t enaddr; 124 125 aprint_normal("\n"); 126 sa = aux; 127 sc->sc_dev = self; 128 sc->sc_iot = sa->sa_iot; 129 sc->sc_intr = sa->sa_intr; 130 sc->sc_dmat = sa->sa_dmat; 131 132 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 133 0, &sc->sc_ioh)) 134 panic("%s: Cannot map registers", device_xname(self)); 135 136 /* Fetch the Ethernet address from property if set. */ 137 enaddr = prop_dictionary_get(device_properties(self), "mac-address"); 138 if (enaddr != NULL) { 139 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA); 140 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN); 141 memcpy(sc->sc_enaddr, prop_data_data_nocopy(enaddr), 142 ETHER_ADDR_LEN); 143 bus_space_write_4(sc->sc_iot, sc->sc_ioh, EPE_AFP, 0); 144 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 145 sc->sc_enaddr, ETHER_ADDR_LEN); 146 } 147 148 ep93xx_intr_establish(sc->sc_intr, IPL_NET, epe_intr, sc); 149 epe_init(sc); 150 } 151 152 static int 153 epe_gctx(struct epe_softc *sc) 154 { 155 struct ifnet * ifp = &sc->sc_ec.ec_if; 156 uint32_t *cur, ndq = 0; 157 158 /* Handle transmit completions */ 159 cur = (uint32_t *)(EPE_READ(TXStsQCurAdd) - 160 sc->ctrlpage_dsaddr + (char*)sc->ctrlpage); 161 162 if (sc->TXStsQ_cur != cur) { 163 CTRLPAGE_DMASYNC(TX_QLEN * 2 * sizeof(uint32_t), 164 TX_QLEN * sizeof(uint32_t), BUS_DMASYNC_PREREAD); 165 } else 166 return 0; 167 168 do { 169 uint32_t tbi = *sc->TXStsQ_cur & 0x7fff; 170 struct mbuf *m = sc->txq[tbi].m; 171 172 if ((*sc->TXStsQ_cur & TXStsQ_TxWE) == 0) 173 if_statinc(ifp, if_oerrors); 174 175 bus_dmamap_unload(sc->sc_dmat, sc->txq[tbi].m_dmamap); 176 m_freem(m); 177 do { 178 sc->txq[tbi].m = NULL; 179 ndq++; 180 tbi = (tbi + 1) % TX_QLEN; 181 } while (sc->txq[tbi].m == m); 182 183 if_statinc(ifp, if_opackets); 184 sc->TXStsQ_cur++; 185 if (sc->TXStsQ_cur >= sc->TXStsQ + TX_QLEN) { 186 sc->TXStsQ_cur = sc->TXStsQ; 187 } 188 } while (sc->TXStsQ_cur != cur); 189 190 sc->TXDQ_avail += ndq; 191 if (sc->tx_busy) { 192 sc->tx_busy = false; 193 /* Disable end-of-tx-chain interrupt */ 194 EPE_WRITE(IntEn, IntEn_REOFIE); 195 } 196 return ndq; 197 } 198 199 static int 200 epe_intr(void *arg) 201 { 202 struct epe_softc *sc = (struct epe_softc *)arg; 203 struct ifnet * ifp = &sc->sc_ec.ec_if; 204 uint32_t ndq = 0, irq, *cur; 205 206 irq = EPE_READ(IntStsC); 207 begin: 208 cur = (uint32_t *)(EPE_READ(RXStsQCurAdd) - 209 sc->ctrlpage_dsaddr + (char*)sc->ctrlpage); 210 CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(uint32_t), 211 RX_QLEN * 4 * sizeof(uint32_t), 212 BUS_DMASYNC_PREREAD); 213 while (sc->RXStsQ_cur != cur) { 214 if ((sc->RXStsQ_cur[0] & (RXStsQ_RWE | RXStsQ_RFP |RXStsQ_EOB)) 215 == (RXStsQ_RWE | RXStsQ_RFP | RXStsQ_EOB)) { 216 uint32_t bi = (sc->RXStsQ_cur[1] >> 16) & 0x7fff; 217 uint32_t fl = sc->RXStsQ_cur[1] & 0xffff; 218 struct mbuf *m; 219 220 MGETHDR(m, M_DONTWAIT, MT_DATA); 221 if (m != NULL) MCLGET(m, M_DONTWAIT); 222 if (m != NULL && (m->m_flags & M_EXT)) { 223 bus_dmamap_unload(sc->sc_dmat, 224 sc->rxq[bi].m_dmamap); 225 m_set_rcvif(sc->rxq[bi].m, ifp); 226 sc->rxq[bi].m->m_pkthdr.len = 227 sc->rxq[bi].m->m_len = fl; 228 if_percpuq_enqueue(ifp->if_percpuq, 229 sc->rxq[bi].m); 230 sc->rxq[bi].m = m; 231 bus_dmamap_load(sc->sc_dmat, 232 sc->rxq[bi].m_dmamap, 233 m->m_ext.ext_buf, MCLBYTES, 234 NULL, BUS_DMA_NOWAIT); 235 sc->RXDQ[bi * 2] = 236 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr; 237 } else { 238 /* Drop packets until we can get replacement 239 * empty mbufs for the RXDQ. 240 */ 241 if (m != NULL) 242 m_freem(m); 243 244 if_statinc(ifp, if_ierrors); 245 } 246 } else 247 if_statinc(ifp, if_ierrors); 248 249 ndq++; 250 251 sc->RXStsQ_cur += 2; 252 if (sc->RXStsQ_cur >= sc->RXStsQ + (RX_QLEN * 2)) 253 sc->RXStsQ_cur = sc->RXStsQ; 254 } 255 256 if (ndq > 0) { 257 CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(uint32_t), 258 RX_QLEN * 4 * sizeof(uint32_t), 259 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 260 EPE_WRITE(RXStsEnq, ndq); 261 EPE_WRITE(RXDEnq, ndq); 262 ndq = 0; 263 } 264 265 if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 266 if_schedule_deferred_start(ifp); 267 } 268 269 irq = EPE_READ(IntStsC); 270 if ((irq & (IntSts_RxSQ | IntSts_ECI)) != 0) 271 goto begin; 272 273 return 1; 274 } 275 276 277 static void 278 epe_init(struct epe_softc *sc) 279 { 280 bus_dma_segment_t segs; 281 char *addr; 282 int rsegs, err, i; 283 struct ifnet * ifp = &sc->sc_ec.ec_if; 284 struct mii_data *mii = &sc->sc_mii; 285 int mdcdiv = DEFAULT_MDCDIV; 286 287 callout_init(&sc->epe_tick_ch, 0); 288 289 /* Select primary Individual Address in Address Filter Pointer */ 290 EPE_WRITE(AFP, 0); 291 /* Read ethernet MAC, should already be set by bootrom */ 292 bus_space_read_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 293 sc->sc_enaddr, ETHER_ADDR_LEN); 294 aprint_normal_dev(sc->sc_dev, "MAC address %s\n", 295 ether_sprintf(sc->sc_enaddr)); 296 297 /* Soft Reset the MAC */ 298 EPE_WRITE(SelfCtl, SelfCtl_RESET); 299 while (EPE_READ(SelfCtl) & SelfCtl_RESET) 300 ; 301 302 /* suggested magic initialization values from datasheet */ 303 EPE_WRITE(RXBufThrshld, 0x800040); 304 EPE_WRITE(TXBufThrshld, 0x200010); 305 EPE_WRITE(RXStsThrshld, 0x40002); 306 EPE_WRITE(TXStsThrshld, 0x40002); 307 EPE_WRITE(RXDThrshld, 0x40002); 308 EPE_WRITE(TXDThrshld, 0x40002); 309 310 /* Allocate a page of memory for descriptor and status queues */ 311 err = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, 0, PAGE_SIZE, 312 &segs, 1, &rsegs, BUS_DMA_WAITOK); 313 if (err == 0) { 314 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, PAGE_SIZE, 315 &sc->ctrlpage, (BUS_DMA_WAITOK | BUS_DMA_COHERENT)); 316 } 317 if (err == 0) { 318 err = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 319 0, BUS_DMA_WAITOK, &sc->ctrlpage_dmamap); 320 } 321 if (err == 0) { 322 err = bus_dmamap_load(sc->sc_dmat, sc->ctrlpage_dmamap, 323 sc->ctrlpage, PAGE_SIZE, NULL, BUS_DMA_WAITOK); 324 } 325 if (err != 0) { 326 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 327 } 328 sc->ctrlpage_dsaddr = sc->ctrlpage_dmamap->dm_segs[0].ds_addr; 329 memset(sc->ctrlpage, 0, PAGE_SIZE); 330 331 /* Set up pointers to start of each queue in kernel addr space. 332 * Each descriptor queue or status queue entry uses 2 words 333 */ 334 sc->TXDQ = (uint32_t *)sc->ctrlpage; 335 sc->TXDQ_cur = sc->TXDQ; 336 sc->TXDQ_avail = TX_QLEN - 1; 337 sc->TXStsQ = &sc->TXDQ[TX_QLEN * 2]; 338 sc->TXStsQ_cur = sc->TXStsQ; 339 sc->RXDQ = &sc->TXStsQ[TX_QLEN]; 340 sc->RXStsQ = &sc->RXDQ[RX_QLEN * 2]; 341 sc->RXStsQ_cur = sc->RXStsQ; 342 343 /* Program each queue's start addr, cur addr, and len registers 344 * with the physical addresses. 345 */ 346 addr = (char *)sc->ctrlpage_dmamap->dm_segs[0].ds_addr; 347 EPE_WRITE(TXDQBAdd, (uint32_t)addr); 348 EPE_WRITE(TXDQCurAdd, (uint32_t)addr); 349 EPE_WRITE(TXDQBLen, TX_QLEN * 2 * sizeof(uint32_t)); 350 351 addr += (sc->TXStsQ - sc->TXDQ) * sizeof(uint32_t); 352 EPE_WRITE(TXStsQBAdd, (uint32_t)addr); 353 EPE_WRITE(TXStsQCurAdd, (uint32_t)addr); 354 EPE_WRITE(TXStsQBLen, TX_QLEN * sizeof(uint32_t)); 355 356 addr += (sc->RXDQ - sc->TXStsQ) * sizeof(uint32_t); 357 EPE_WRITE(RXDQBAdd, (uint32_t)addr); 358 EPE_WRITE(RXDCurAdd, (uint32_t)addr); 359 EPE_WRITE(RXDQBLen, RX_QLEN * 2 * sizeof(uint32_t)); 360 361 addr += (sc->RXStsQ - sc->RXDQ) * sizeof(uint32_t); 362 EPE_WRITE(RXStsQBAdd, (uint32_t)addr); 363 EPE_WRITE(RXStsQCurAdd, (uint32_t)addr); 364 EPE_WRITE(RXStsQBLen, RX_QLEN * 2 * sizeof(uint32_t)); 365 366 /* Populate the RXDQ with mbufs */ 367 for (i = 0; i < RX_QLEN; i++) { 368 struct mbuf *m; 369 370 bus_dmamap_create(sc->sc_dmat, MCLBYTES, TX_QLEN/4, MCLBYTES, 371 0, BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 372 MGETHDR(m, M_WAIT, MT_DATA); 373 MCLGET(m, M_WAIT); 374 sc->rxq[i].m = m; 375 bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 376 m->m_ext.ext_buf, MCLBYTES, NULL, BUS_DMA_WAITOK); 377 378 sc->RXDQ[i * 2] = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr; 379 sc->RXDQ[i * 2 + 1] = (i << 16) | MCLBYTES; 380 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 381 MCLBYTES, BUS_DMASYNC_PREREAD); 382 } 383 384 for (i = 0; i < TX_QLEN; i++) { 385 bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 386 (BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW), 387 &sc->txq[i].m_dmamap); 388 sc->txq[i].m = NULL; 389 sc->TXDQ[i * 2 + 1] = (i << 16); 390 } 391 392 /* Divide HCLK by 32 for MDC clock */ 393 if (device_cfdata(sc->sc_dev)->cf_flags) 394 mdcdiv = device_cfdata(sc->sc_dev)->cf_flags; 395 EPE_WRITE(SelfCtl, (SelfCtl_MDCDIV(mdcdiv) | SelfCtl_PSPRS)); 396 397 mii->mii_ifp = ifp; 398 mii->mii_readreg = epe_mii_readreg; 399 mii->mii_writereg = epe_mii_writereg; 400 mii->mii_statchg = epe_statchg; 401 sc->sc_ec.ec_mii = mii; 402 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 403 ether_mediastatus); 404 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 405 MII_OFFSET_ANY, 0); 406 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 407 408 EPE_WRITE(BMCtl, BMCtl_RxEn | BMCtl_TxEn); 409 EPE_WRITE(IntEn, IntEn_REOFIE); 410 /* maximum valid max frame length */ 411 EPE_WRITE(MaxFrmLen, (0x7ff << 16) | MHLEN); 412 /* wait for receiver ready */ 413 while ((EPE_READ(BMSts) & BMSts_RxAct) == 0) 414 continue; 415 /* enqueue the entries in RXStsQ and RXDQ */ 416 CTRLPAGE_DMASYNC(0, sc->ctrlpage_dmamap->dm_mapsize, 417 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 418 EPE_WRITE(RXDEnq, RX_QLEN - 1); 419 EPE_WRITE(RXStsEnq, RX_QLEN - 1); 420 421 /* 422 * We can support 802.1Q VLAN-sized frames. 423 */ 424 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 425 426 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 427 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 428 ifp->if_ioctl = epe_ifioctl; 429 ifp->if_start = epe_ifstart; 430 ifp->if_watchdog = epe_ifwatchdog; 431 ifp->if_init = epe_ifinit; 432 ifp->if_stop = epe_ifstop; 433 ifp->if_timer = 0; 434 ifp->if_softc = sc; 435 IFQ_SET_READY(&ifp->if_snd); 436 if_attach(ifp); 437 if_deferred_start_init(ifp, NULL); 438 ether_ifattach(ifp, (sc)->sc_enaddr); 439 } 440 441 int 442 epe_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 443 { 444 uint32_t d; 445 446 d = EPE_READ(SelfCtl); 447 EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */ 448 EPE_WRITE(MIICmd, (MIICmd_READ | (phy << 5) | reg)); 449 while (EPE_READ(MIISts) & MIISts_BUSY) 450 ; 451 *val = EPE_READ(MIIData) & 0xffff; 452 EPE_WRITE(SelfCtl, d); /* restore old value */ 453 return 0; 454 } 455 456 int 457 epe_mii_writereg(device_t self, int phy, int reg, uint16_t val) 458 { 459 uint32_t d; 460 461 d = EPE_READ(SelfCtl); 462 EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */ 463 EPE_WRITE(MIIData, val); 464 EPE_WRITE(MIICmd, (MIICmd_WRITE | (phy << 5) | reg)); 465 while (EPE_READ(MIISts) & MIISts_BUSY) 466 ; 467 EPE_WRITE(SelfCtl, d); /* restore old value */ 468 469 return 0; 470 } 471 472 void 473 epe_statchg(struct ifnet *ifp) 474 { 475 struct epe_softc *sc = ifp->if_softc; 476 uint32_t reg; 477 478 /* 479 * We must keep the MAC and the PHY in sync as 480 * to the status of full-duplex! 481 */ 482 reg = EPE_READ(TestCtl); 483 if (sc->sc_mii.mii_media_active & IFM_FDX) 484 reg |= TestCtl_MFDX; 485 else 486 reg &= ~TestCtl_MFDX; 487 EPE_WRITE(TestCtl, reg); 488 } 489 490 void 491 epe_tick(void *arg) 492 { 493 struct epe_softc* sc = (struct epe_softc *)arg; 494 struct ifnet * ifp = &sc->sc_ec.ec_if; 495 int s; 496 uint32_t misses; 497 498 if_statadd(ifp, if_collisions, EPE_READ(TXCollCnt)); 499 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 500 misses = EPE_READ(RXMissCnt); 501 if (misses > 0) 502 printf("%s: %d rx misses\n", device_xname(sc->sc_dev), misses); 503 504 s = splnet(); 505 if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 506 epe_ifstart(ifp); 507 } 508 splx(s); 509 510 mii_tick(&sc->sc_mii); 511 callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc); 512 } 513 514 515 static int 516 epe_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 517 { 518 int s, error; 519 520 s = splnet(); 521 error = ether_ioctl(ifp, cmd, data); 522 if (error == ENETRESET) { 523 if (ifp->if_flags & IFF_RUNNING) 524 epe_setaddr(ifp); 525 error = 0; 526 } 527 splx(s); 528 return error; 529 } 530 531 static void 532 epe_ifstart(struct ifnet *ifp) 533 { 534 struct epe_softc *sc = (struct epe_softc *)ifp->if_softc; 535 struct mbuf *m; 536 bus_dma_segment_t *segs; 537 int s, bi, err, nsegs, ndq; 538 539 s = splnet(); 540 start: 541 ndq = 0; 542 if (sc->TXDQ_avail == 0) { 543 if (epe_gctx(sc) == 0) { 544 /* Enable End-Of-TX-Chain interrupt */ 545 EPE_WRITE(IntEn, IntEn_REOFIE | IntEn_ECIE); 546 sc->tx_busy = true; 547 ifp->if_timer = 10; 548 splx(s); 549 return; 550 } 551 } 552 553 bi = sc->TXDQ_cur - sc->TXDQ; 554 555 IFQ_POLL(&ifp->if_snd, m); 556 if (m == NULL) { 557 splx(s); 558 return; 559 } 560 more: 561 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 562 BUS_DMA_NOWAIT)) || 563 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 564 sc->txq[bi].m_dmamap->dm_nsegs > (sc->TXDQ_avail - ndq)) { 565 /* Copy entire mbuf chain to new and 32-bit aligned storage */ 566 struct mbuf *mn; 567 568 if (err == 0) 569 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 570 571 MGETHDR(mn, M_DONTWAIT, MT_DATA); 572 if (mn == NULL) goto stop; 573 if (m->m_pkthdr.len > (MHLEN & (~0x3))) { 574 MCLGET(mn, M_DONTWAIT); 575 if ((mn->m_flags & M_EXT) == 0) { 576 m_freem(mn); 577 goto stop; 578 } 579 } 580 mn->m_data = (void *)(((uint32_t)mn->m_data + 0x3) & (~0x3)); 581 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 582 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 583 IFQ_DEQUEUE(&ifp->if_snd, m); 584 m_freem(m); 585 m = mn; 586 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 587 BUS_DMA_NOWAIT); 588 } else { 589 IFQ_DEQUEUE(&ifp->if_snd, m); 590 } 591 592 bpf_mtap(ifp, m, BPF_D_OUT); 593 594 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 595 segs = sc->txq[bi].m_dmamap->dm_segs; 596 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 597 sc->txq[bi].m_dmamap->dm_mapsize, 598 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 599 600 /* XXX: This driver hasn't been tested w/nsegs > 1 */ 601 while (nsegs > 0) { 602 nsegs--; 603 sc->txq[bi].m = m; 604 sc->TXDQ[bi * 2] = segs->ds_addr; 605 if (nsegs == 0) 606 sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16) | 607 (1 << 31); 608 else 609 sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16); 610 segs++; 611 bi = (bi + 1) % TX_QLEN; 612 ndq++; 613 } 614 615 616 /* 617 * Enqueue another. Don't do more than half the available 618 * descriptors before telling the MAC about them 619 */ 620 if ((sc->TXDQ_avail - ndq) > 0 && ndq < TX_QLEN / 2) { 621 IFQ_POLL(&ifp->if_snd, m); 622 if (m != NULL) 623 goto more; 624 } 625 stop: 626 if (ndq > 0) { 627 sc->TXDQ_avail -= ndq; 628 sc->TXDQ_cur = &sc->TXDQ[bi]; 629 CTRLPAGE_DMASYNC(0, TX_QLEN * 2 * sizeof(uint32_t), 630 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 631 EPE_WRITE(TXDEnq, ndq); 632 } 633 634 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 635 goto start; 636 637 splx(s); 638 return; 639 } 640 641 static void 642 epe_ifwatchdog(struct ifnet *ifp) 643 { 644 struct epe_softc *sc = (struct epe_softc *)ifp->if_softc; 645 646 if ((ifp->if_flags & IFF_RUNNING) == 0) 647 return; 648 printf("%s: device timeout, BMCtl = 0x%08x, BMSts = 0x%08x\n", 649 device_xname(sc->sc_dev), EPE_READ(BMCtl), EPE_READ(BMSts)); 650 } 651 652 static int 653 epe_ifinit(struct ifnet *ifp) 654 { 655 struct epe_softc *sc = ifp->if_softc; 656 int rc, s = splnet(); 657 658 callout_stop(&sc->epe_tick_ch); 659 EPE_WRITE(RXCtl, RXCtl_IA0 | RXCtl_BA | RXCtl_RCRCA | RXCtl_SRxON); 660 EPE_WRITE(TXCtl, TXCtl_STxON); 661 EPE_WRITE(GIIntMsk, GIIntMsk_INT); /* start interrupting */ 662 663 if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 664 rc = 0; 665 else if (rc != 0) 666 goto out; 667 668 callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc); 669 ifp->if_flags |= IFF_RUNNING; 670 out: 671 splx(s); 672 return 0; 673 } 674 675 static void 676 epe_ifstop(struct ifnet *ifp, int disable) 677 { 678 struct epe_softc *sc = ifp->if_softc; 679 680 681 EPE_WRITE(RXCtl, 0); 682 EPE_WRITE(TXCtl, 0); 683 EPE_WRITE(GIIntMsk, 0); 684 callout_stop(&sc->epe_tick_ch); 685 686 /* Down the MII. */ 687 mii_down(&sc->sc_mii); 688 689 ifp->if_flags &= ~IFF_RUNNING; 690 ifp->if_timer = 0; 691 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 692 } 693 694 static void 695 epe_setaddr(struct ifnet *ifp) 696 { 697 struct epe_softc *sc = ifp->if_softc; 698 struct ethercom *ec = &sc->sc_ec; 699 struct ether_multi *enm; 700 struct ether_multistep step; 701 uint8_t ias[2][ETHER_ADDR_LEN]; 702 uint32_t h, nma = 0, hashes[2] = { 0, 0 }; 703 uint32_t rxctl = EPE_READ(RXCtl); 704 705 /* disable receiver temporarily */ 706 EPE_WRITE(RXCtl, rxctl & ~RXCtl_SRxON); 707 708 rxctl &= ~(RXCtl_MA | RXCtl_PA | RXCtl_IA2 | RXCtl_IA3); 709 710 if (ifp->if_flags & IFF_PROMISC) 711 rxctl |= RXCtl_PA; 712 713 ifp->if_flags &= ~IFF_ALLMULTI; 714 715 ETHER_LOCK(ec); 716 ETHER_FIRST_MULTI(step, ec, enm); 717 while (enm != NULL) { 718 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 719 /* 720 * We must listen to a range of multicast addresses. 721 * For now, just accept all multicasts, rather than 722 * trying to set only those filter bits needed to match 723 * the range. (At this time, the only use of address 724 * ranges is for IP multicast routing, for which the 725 * range is big enough to require all bits set.) 726 */ 727 rxctl &= ~(RXCtl_IA2 | RXCtl_IA3); 728 rxctl |= RXCtl_MA; 729 hashes[0] = 0xffffffffUL; 730 hashes[1] = 0xffffffffUL; 731 ifp->if_flags |= IFF_ALLMULTI; 732 break; 733 } 734 735 if (nma < 2) { 736 /* We can program 2 perfect address filters for mcast */ 737 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 738 rxctl |= (1 << (nma + 2)); 739 } else { 740 /* 741 * XXX: Datasheet is not very clear here, I'm not sure 742 * if I'm doing this right. --joff 743 */ 744 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 745 746 /* Just want the 6 most-significant bits. */ 747 h = h >> 26; 748 749 hashes[ h / 32 ] |= (1 << (h % 32)); 750 rxctl |= RXCtl_MA; 751 } 752 ETHER_NEXT_MULTI(step, enm); 753 nma++; 754 } 755 ETHER_UNLOCK(ec); 756 757 EPE_WRITE(AFP, 0); 758 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 759 sc->sc_enaddr, ETHER_ADDR_LEN); 760 if (rxctl & RXCtl_IA2) { 761 EPE_WRITE(AFP, 2); 762 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 763 ias[0], ETHER_ADDR_LEN); 764 } 765 if (rxctl & RXCtl_IA3) { 766 EPE_WRITE(AFP, 3); 767 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 768 ias[1], ETHER_ADDR_LEN); 769 } 770 if (hashes[0] != 0 && hashes[1] != 0) { 771 EPE_WRITE(AFP, 7); 772 EPE_WRITE(HashTbl, hashes[0]); 773 EPE_WRITE(HashTbl + 4, hashes[1]); 774 } 775 EPE_WRITE(RXCtl, rxctl); 776 } 777
Indexes created Mon Oct 27 04:09:48 GMT 2025