epe.c revision 1.52
1 /* $NetBSD: epe.c,v 1.52 2025/10/04 04:44:19 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Jesse Off 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: epe.c,v 1.52 2025/10/04 04:44:19 thorpej Exp $"); 31 32 #include <sys/types.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/ioctl.h> 36 #include <sys/kernel.h> 37 #include <sys/proc.h> 38 #include <sys/time.h> 39 #include <sys/device.h> 40 #include <uvm/uvm_extern.h> 41 42 #include <sys/bus.h> 43 #include <machine/intr.h> 44 45 #include <arm/cpufunc.h> 46 47 #include <arm/ep93xx/epsocvar.h> 48 #include <arm/ep93xx/ep93xxvar.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_types.h> 53 #include <net/if_media.h> 54 #include <net/if_ether.h> 55 #include <net/bpf.h> 56 57 #include <dev/mii/mii.h> 58 #include <dev/mii/miivar.h> 59 60 #ifdef INET 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/in_var.h> 64 #include <netinet/ip.h> 65 #include <netinet/if_inarp.h> 66 #endif 67 68 #include <arm/ep93xx/ep93xxreg.h> 69 #include <arm/ep93xx/epereg.h> 70 #include <arm/ep93xx/epevar.h> 71 72 #define DEFAULT_MDCDIV 32 73 74 #ifndef EPE_FAST 75 #define EPE_FAST 76 #endif 77 78 #ifndef EPE_FAST 79 #define EPE_READ(x) \ 80 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x)) 81 #define EPE_WRITE(x, y) \ 82 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x), (y)) 83 #define CTRLPAGE_DMASYNC(x, y, z) \ 84 bus_dmamap_sync(sc->sc_dmat, sc->ctrlpage_dmamap, (x), (y), (z)) 85 #else 86 #define EPE_READ(x) *(volatile uint32_t *) \ 87 (EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x)) 88 #define EPE_WRITE(x, y) *(volatile uint32_t *) \ 89 (EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x)) = y 90 #define CTRLPAGE_DMASYNC(x, y, z) 91 #endif /* ! EPE_FAST */ 92 93 static int epe_match(device_t , cfdata_t, void *); 94 static void epe_attach(device_t, device_t, void *); 95 static void epe_init(struct epe_softc *); 96 static int epe_intr(void* arg); 97 static int epe_gctx(struct epe_softc *); 98 int epe_mii_readreg (device_t, int, int, uint16_t *); 99 int epe_mii_writereg (device_t, int, int, uint16_t); 100 void epe_statchg (struct ifnet *); 101 void epe_tick (void *); 102 static int epe_ifioctl (struct ifnet *, u_long, void *); 103 static void epe_ifstart (struct ifnet *); 104 static void epe_ifwatchdog (struct ifnet *); 105 static int epe_ifinit (struct ifnet *); 106 static void epe_ifstop (struct ifnet *, int); 107 static void epe_setaddr (struct ifnet *); 108 109 CFATTACH_DECL_NEW(epe, sizeof(struct epe_softc), 110 epe_match, epe_attach, NULL, NULL); 111 112 static int 113 epe_match(device_t parent, cfdata_t match, void *aux) 114 { 115 return 2; 116 } 117 118 static void 119 epe_attach(device_t parent, device_t self, void *aux) 120 { 121 struct epe_softc *sc = device_private(self); 122 struct epsoc_attach_args *sa; 123 124 aprint_normal("\n"); 125 sa = aux; 126 sc->sc_dev = self; 127 sc->sc_iot = sa->sa_iot; 128 sc->sc_intr = sa->sa_intr; 129 sc->sc_dmat = sa->sa_dmat; 130 131 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 132 0, &sc->sc_ioh)) 133 panic("%s: Cannot map registers", device_xname(self)); 134 135 /* Fetch the Ethernet address from property if set. */ 136 if (ether_getaddr(self, sc->sc_enaddr)) { 137 bus_space_write_4(sc->sc_iot, sc->sc_ioh, EPE_AFP, 0); 138 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 139 sc->sc_enaddr, ETHER_ADDR_LEN); 140 } 141 142 ep93xx_intr_establish(sc->sc_intr, IPL_NET, epe_intr, sc); 143 epe_init(sc); 144 } 145 146 static int 147 epe_gctx(struct epe_softc *sc) 148 { 149 struct ifnet * ifp = &sc->sc_ec.ec_if; 150 uint32_t *cur, ndq = 0; 151 152 /* Handle transmit completions */ 153 cur = (uint32_t *)(EPE_READ(TXStsQCurAdd) - 154 sc->ctrlpage_dsaddr + (char*)sc->ctrlpage); 155 156 if (sc->TXStsQ_cur != cur) { 157 CTRLPAGE_DMASYNC(TX_QLEN * 2 * sizeof(uint32_t), 158 TX_QLEN * sizeof(uint32_t), BUS_DMASYNC_PREREAD); 159 } else 160 return 0; 161 162 do { 163 uint32_t tbi = *sc->TXStsQ_cur & 0x7fff; 164 struct mbuf *m = sc->txq[tbi].m; 165 166 if ((*sc->TXStsQ_cur & TXStsQ_TxWE) == 0) 167 if_statinc(ifp, if_oerrors); 168 169 bus_dmamap_unload(sc->sc_dmat, sc->txq[tbi].m_dmamap); 170 m_freem(m); 171 do { 172 sc->txq[tbi].m = NULL; 173 ndq++; 174 tbi = (tbi + 1) % TX_QLEN; 175 } while (sc->txq[tbi].m == m); 176 177 if_statinc(ifp, if_opackets); 178 sc->TXStsQ_cur++; 179 if (sc->TXStsQ_cur >= sc->TXStsQ + TX_QLEN) { 180 sc->TXStsQ_cur = sc->TXStsQ; 181 } 182 } while (sc->TXStsQ_cur != cur); 183 184 sc->TXDQ_avail += ndq; 185 if (sc->tx_busy) { 186 sc->tx_busy = false; 187 /* Disable end-of-tx-chain interrupt */ 188 EPE_WRITE(IntEn, IntEn_REOFIE); 189 } 190 return ndq; 191 } 192 193 static int 194 epe_intr(void *arg) 195 { 196 struct epe_softc *sc = (struct epe_softc *)arg; 197 struct ifnet * ifp = &sc->sc_ec.ec_if; 198 uint32_t ndq = 0, irq, *cur; 199 200 irq = EPE_READ(IntStsC); 201 begin: 202 cur = (uint32_t *)(EPE_READ(RXStsQCurAdd) - 203 sc->ctrlpage_dsaddr + (char*)sc->ctrlpage); 204 CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(uint32_t), 205 RX_QLEN * 4 * sizeof(uint32_t), 206 BUS_DMASYNC_PREREAD); 207 while (sc->RXStsQ_cur != cur) { 208 if ((sc->RXStsQ_cur[0] & (RXStsQ_RWE | RXStsQ_RFP |RXStsQ_EOB)) 209 == (RXStsQ_RWE | RXStsQ_RFP | RXStsQ_EOB)) { 210 uint32_t bi = (sc->RXStsQ_cur[1] >> 16) & 0x7fff; 211 uint32_t fl = sc->RXStsQ_cur[1] & 0xffff; 212 struct mbuf *m; 213 214 MGETHDR(m, M_DONTWAIT, MT_DATA); 215 if (m != NULL) MCLGET(m, M_DONTWAIT); 216 if (m != NULL && (m->m_flags & M_EXT)) { 217 bus_dmamap_unload(sc->sc_dmat, 218 sc->rxq[bi].m_dmamap); 219 m_set_rcvif(sc->rxq[bi].m, ifp); 220 sc->rxq[bi].m->m_pkthdr.len = 221 sc->rxq[bi].m->m_len = fl; 222 if_percpuq_enqueue(ifp->if_percpuq, 223 sc->rxq[bi].m); 224 sc->rxq[bi].m = m; 225 bus_dmamap_load(sc->sc_dmat, 226 sc->rxq[bi].m_dmamap, 227 m->m_ext.ext_buf, MCLBYTES, 228 NULL, BUS_DMA_NOWAIT); 229 sc->RXDQ[bi * 2] = 230 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr; 231 } else { 232 /* Drop packets until we can get replacement 233 * empty mbufs for the RXDQ. 234 */ 235 m_freem(m); 236 237 if_statinc(ifp, if_ierrors); 238 } 239 } else 240 if_statinc(ifp, if_ierrors); 241 242 ndq++; 243 244 sc->RXStsQ_cur += 2; 245 if (sc->RXStsQ_cur >= sc->RXStsQ + (RX_QLEN * 2)) 246 sc->RXStsQ_cur = sc->RXStsQ; 247 } 248 249 if (ndq > 0) { 250 CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(uint32_t), 251 RX_QLEN * 4 * sizeof(uint32_t), 252 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 253 EPE_WRITE(RXStsEnq, ndq); 254 EPE_WRITE(RXDEnq, ndq); 255 ndq = 0; 256 } 257 258 if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 259 if_schedule_deferred_start(ifp); 260 } 261 262 irq = EPE_READ(IntStsC); 263 if ((irq & (IntSts_RxSQ | IntSts_ECI)) != 0) 264 goto begin; 265 266 return 1; 267 } 268 269 270 static void 271 epe_init(struct epe_softc *sc) 272 { 273 bus_dma_segment_t segs; 274 char *addr; 275 int rsegs, err, i; 276 struct ifnet * ifp = &sc->sc_ec.ec_if; 277 struct mii_data *mii = &sc->sc_mii; 278 int mdcdiv = DEFAULT_MDCDIV; 279 280 callout_init(&sc->epe_tick_ch, 0); 281 282 /* Select primary Individual Address in Address Filter Pointer */ 283 EPE_WRITE(AFP, 0); 284 /* Read ethernet MAC, should already be set by bootrom */ 285 bus_space_read_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 286 sc->sc_enaddr, ETHER_ADDR_LEN); 287 aprint_normal_dev(sc->sc_dev, "MAC address %s\n", 288 ether_sprintf(sc->sc_enaddr)); 289 290 /* Soft Reset the MAC */ 291 EPE_WRITE(SelfCtl, SelfCtl_RESET); 292 while (EPE_READ(SelfCtl) & SelfCtl_RESET) 293 ; 294 295 /* suggested magic initialization values from datasheet */ 296 EPE_WRITE(RXBufThrshld, 0x800040); 297 EPE_WRITE(TXBufThrshld, 0x200010); 298 EPE_WRITE(RXStsThrshld, 0x40002); 299 EPE_WRITE(TXStsThrshld, 0x40002); 300 EPE_WRITE(RXDThrshld, 0x40002); 301 EPE_WRITE(TXDThrshld, 0x40002); 302 303 /* Allocate a page of memory for descriptor and status queues */ 304 err = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, 0, PAGE_SIZE, 305 &segs, 1, &rsegs, BUS_DMA_WAITOK); 306 if (err == 0) { 307 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, PAGE_SIZE, 308 &sc->ctrlpage, (BUS_DMA_WAITOK | BUS_DMA_COHERENT)); 309 } 310 if (err == 0) { 311 err = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 312 0, BUS_DMA_WAITOK, &sc->ctrlpage_dmamap); 313 } 314 if (err == 0) { 315 err = bus_dmamap_load(sc->sc_dmat, sc->ctrlpage_dmamap, 316 sc->ctrlpage, PAGE_SIZE, NULL, BUS_DMA_WAITOK); 317 } 318 if (err != 0) { 319 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 320 } 321 sc->ctrlpage_dsaddr = sc->ctrlpage_dmamap->dm_segs[0].ds_addr; 322 memset(sc->ctrlpage, 0, PAGE_SIZE); 323 324 /* Set up pointers to start of each queue in kernel addr space. 325 * Each descriptor queue or status queue entry uses 2 words 326 */ 327 sc->TXDQ = (uint32_t *)sc->ctrlpage; 328 sc->TXDQ_cur = sc->TXDQ; 329 sc->TXDQ_avail = TX_QLEN - 1; 330 sc->TXStsQ = &sc->TXDQ[TX_QLEN * 2]; 331 sc->TXStsQ_cur = sc->TXStsQ; 332 sc->RXDQ = &sc->TXStsQ[TX_QLEN]; 333 sc->RXStsQ = &sc->RXDQ[RX_QLEN * 2]; 334 sc->RXStsQ_cur = sc->RXStsQ; 335 336 /* Program each queue's start addr, cur addr, and len registers 337 * with the physical addresses. 338 */ 339 addr = (char *)sc->ctrlpage_dmamap->dm_segs[0].ds_addr; 340 EPE_WRITE(TXDQBAdd, (uint32_t)addr); 341 EPE_WRITE(TXDQCurAdd, (uint32_t)addr); 342 EPE_WRITE(TXDQBLen, TX_QLEN * 2 * sizeof(uint32_t)); 343 344 addr += (sc->TXStsQ - sc->TXDQ) * sizeof(uint32_t); 345 EPE_WRITE(TXStsQBAdd, (uint32_t)addr); 346 EPE_WRITE(TXStsQCurAdd, (uint32_t)addr); 347 EPE_WRITE(TXStsQBLen, TX_QLEN * sizeof(uint32_t)); 348 349 addr += (sc->RXDQ - sc->TXStsQ) * sizeof(uint32_t); 350 EPE_WRITE(RXDQBAdd, (uint32_t)addr); 351 EPE_WRITE(RXDCurAdd, (uint32_t)addr); 352 EPE_WRITE(RXDQBLen, RX_QLEN * 2 * sizeof(uint32_t)); 353 354 addr += (sc->RXStsQ - sc->RXDQ) * sizeof(uint32_t); 355 EPE_WRITE(RXStsQBAdd, (uint32_t)addr); 356 EPE_WRITE(RXStsQCurAdd, (uint32_t)addr); 357 EPE_WRITE(RXStsQBLen, RX_QLEN * 2 * sizeof(uint32_t)); 358 359 /* Populate the RXDQ with mbufs */ 360 for (i = 0; i < RX_QLEN; i++) { 361 struct mbuf *m; 362 363 bus_dmamap_create(sc->sc_dmat, MCLBYTES, TX_QLEN/4, MCLBYTES, 364 0, BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 365 MGETHDR(m, M_WAIT, MT_DATA); 366 MCLGET(m, M_WAIT); 367 sc->rxq[i].m = m; 368 bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 369 m->m_ext.ext_buf, MCLBYTES, NULL, BUS_DMA_WAITOK); 370 371 sc->RXDQ[i * 2] = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr; 372 sc->RXDQ[i * 2 + 1] = (i << 16) | MCLBYTES; 373 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 374 MCLBYTES, BUS_DMASYNC_PREREAD); 375 } 376 377 for (i = 0; i < TX_QLEN; i++) { 378 bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 379 (BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW), 380 &sc->txq[i].m_dmamap); 381 sc->txq[i].m = NULL; 382 sc->TXDQ[i * 2 + 1] = (i << 16); 383 } 384 385 /* Divide HCLK by 32 for MDC clock */ 386 if (device_cfdata(sc->sc_dev)->cf_flags) 387 mdcdiv = device_cfdata(sc->sc_dev)->cf_flags; 388 EPE_WRITE(SelfCtl, (SelfCtl_MDCDIV(mdcdiv) | SelfCtl_PSPRS)); 389 390 mii->mii_ifp = ifp; 391 mii->mii_readreg = epe_mii_readreg; 392 mii->mii_writereg = epe_mii_writereg; 393 mii->mii_statchg = epe_statchg; 394 sc->sc_ec.ec_mii = mii; 395 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 396 ether_mediastatus); 397 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 398 MII_OFFSET_ANY, 0); 399 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 400 401 EPE_WRITE(BMCtl, BMCtl_RxEn | BMCtl_TxEn); 402 EPE_WRITE(IntEn, IntEn_REOFIE); 403 /* maximum valid max frame length */ 404 EPE_WRITE(MaxFrmLen, (0x7ff << 16) | MHLEN); 405 /* wait for receiver ready */ 406 while ((EPE_READ(BMSts) & BMSts_RxAct) == 0) 407 continue; 408 /* enqueue the entries in RXStsQ and RXDQ */ 409 CTRLPAGE_DMASYNC(0, sc->ctrlpage_dmamap->dm_mapsize, 410 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 411 EPE_WRITE(RXDEnq, RX_QLEN - 1); 412 EPE_WRITE(RXStsEnq, RX_QLEN - 1); 413 414 /* 415 * We can support 802.1Q VLAN-sized frames. 416 */ 417 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 418 419 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 420 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 421 ifp->if_ioctl = epe_ifioctl; 422 ifp->if_start = epe_ifstart; 423 ifp->if_watchdog = epe_ifwatchdog; 424 ifp->if_init = epe_ifinit; 425 ifp->if_stop = epe_ifstop; 426 ifp->if_timer = 0; 427 ifp->if_softc = sc; 428 IFQ_SET_READY(&ifp->if_snd); 429 if_attach(ifp); 430 if_deferred_start_init(ifp, NULL); 431 ether_ifattach(ifp, (sc)->sc_enaddr); 432 } 433 434 int 435 epe_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 436 { 437 uint32_t d; 438 439 d = EPE_READ(SelfCtl); 440 EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */ 441 EPE_WRITE(MIICmd, (MIICmd_READ | (phy << 5) | reg)); 442 while (EPE_READ(MIISts) & MIISts_BUSY) 443 ; 444 *val = EPE_READ(MIIData) & 0xffff; 445 EPE_WRITE(SelfCtl, d); /* restore old value */ 446 return 0; 447 } 448 449 int 450 epe_mii_writereg(device_t self, int phy, int reg, uint16_t val) 451 { 452 uint32_t d; 453 454 d = EPE_READ(SelfCtl); 455 EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */ 456 EPE_WRITE(MIIData, val); 457 EPE_WRITE(MIICmd, (MIICmd_WRITE | (phy << 5) | reg)); 458 while (EPE_READ(MIISts) & MIISts_BUSY) 459 ; 460 EPE_WRITE(SelfCtl, d); /* restore old value */ 461 462 return 0; 463 } 464 465 void 466 epe_statchg(struct ifnet *ifp) 467 { 468 struct epe_softc *sc = ifp->if_softc; 469 uint32_t reg; 470 471 /* 472 * We must keep the MAC and the PHY in sync as 473 * to the status of full-duplex! 474 */ 475 reg = EPE_READ(TestCtl); 476 if (sc->sc_mii.mii_media_active & IFM_FDX) 477 reg |= TestCtl_MFDX; 478 else 479 reg &= ~TestCtl_MFDX; 480 EPE_WRITE(TestCtl, reg); 481 } 482 483 void 484 epe_tick(void *arg) 485 { 486 struct epe_softc* sc = (struct epe_softc *)arg; 487 struct ifnet * ifp = &sc->sc_ec.ec_if; 488 int s; 489 uint32_t misses; 490 491 if_statadd(ifp, if_collisions, EPE_READ(TXCollCnt)); 492 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 493 misses = EPE_READ(RXMissCnt); 494 if (misses > 0) 495 printf("%s: %d rx misses\n", device_xname(sc->sc_dev), misses); 496 497 s = splnet(); 498 if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 499 epe_ifstart(ifp); 500 } 501 splx(s); 502 503 mii_tick(&sc->sc_mii); 504 callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc); 505 } 506 507 508 static int 509 epe_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 510 { 511 int s, error; 512 513 s = splnet(); 514 error = ether_ioctl(ifp, cmd, data); 515 if (error == ENETRESET) { 516 if (ifp->if_flags & IFF_RUNNING) 517 epe_setaddr(ifp); 518 error = 0; 519 } 520 splx(s); 521 return error; 522 } 523 524 static void 525 epe_ifstart(struct ifnet *ifp) 526 { 527 struct epe_softc *sc = (struct epe_softc *)ifp->if_softc; 528 struct mbuf *m; 529 bus_dma_segment_t *segs; 530 int s, bi, err, nsegs, ndq; 531 532 s = splnet(); 533 start: 534 ndq = 0; 535 if (sc->TXDQ_avail == 0) { 536 if (epe_gctx(sc) == 0) { 537 /* Enable End-Of-TX-Chain interrupt */ 538 EPE_WRITE(IntEn, IntEn_REOFIE | IntEn_ECIE); 539 sc->tx_busy = true; 540 ifp->if_timer = 10; 541 splx(s); 542 return; 543 } 544 } 545 546 bi = sc->TXDQ_cur - sc->TXDQ; 547 548 IFQ_POLL(&ifp->if_snd, m); 549 if (m == NULL) { 550 splx(s); 551 return; 552 } 553 more: 554 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 555 BUS_DMA_NOWAIT)) || 556 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 557 sc->txq[bi].m_dmamap->dm_nsegs > (sc->TXDQ_avail - ndq)) { 558 /* Copy entire mbuf chain to new and 32-bit aligned storage */ 559 struct mbuf *mn; 560 561 if (err == 0) 562 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 563 564 MGETHDR(mn, M_DONTWAIT, MT_DATA); 565 if (mn == NULL) goto stop; 566 if (m->m_pkthdr.len > (MHLEN & (~0x3))) { 567 MCLGET(mn, M_DONTWAIT); 568 if ((mn->m_flags & M_EXT) == 0) { 569 m_freem(mn); 570 goto stop; 571 } 572 } 573 mn->m_data = (void *)(((uint32_t)mn->m_data + 0x3) & (~0x3)); 574 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 575 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 576 IFQ_DEQUEUE(&ifp->if_snd, m); 577 m_freem(m); 578 m = mn; 579 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 580 BUS_DMA_NOWAIT); 581 } else { 582 IFQ_DEQUEUE(&ifp->if_snd, m); 583 } 584 585 bpf_mtap(ifp, m, BPF_D_OUT); 586 587 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 588 segs = sc->txq[bi].m_dmamap->dm_segs; 589 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 590 sc->txq[bi].m_dmamap->dm_mapsize, 591 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 592 593 /* XXX: This driver hasn't been tested w/nsegs > 1 */ 594 while (nsegs > 0) { 595 nsegs--; 596 sc->txq[bi].m = m; 597 sc->TXDQ[bi * 2] = segs->ds_addr; 598 if (nsegs == 0) 599 sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16) | 600 (1 << 31); 601 else 602 sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16); 603 segs++; 604 bi = (bi + 1) % TX_QLEN; 605 ndq++; 606 } 607 608 609 /* 610 * Enqueue another. Don't do more than half the available 611 * descriptors before telling the MAC about them 612 */ 613 if ((sc->TXDQ_avail - ndq) > 0 && ndq < TX_QLEN / 2) { 614 IFQ_POLL(&ifp->if_snd, m); 615 if (m != NULL) 616 goto more; 617 } 618 stop: 619 if (ndq > 0) { 620 sc->TXDQ_avail -= ndq; 621 sc->TXDQ_cur = &sc->TXDQ[bi]; 622 CTRLPAGE_DMASYNC(0, TX_QLEN * 2 * sizeof(uint32_t), 623 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 624 EPE_WRITE(TXDEnq, ndq); 625 } 626 627 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 628 goto start; 629 630 splx(s); 631 return; 632 } 633 634 static void 635 epe_ifwatchdog(struct ifnet *ifp) 636 { 637 struct epe_softc *sc = (struct epe_softc *)ifp->if_softc; 638 639 if ((ifp->if_flags & IFF_RUNNING) == 0) 640 return; 641 printf("%s: device timeout, BMCtl = 0x%08x, BMSts = 0x%08x\n", 642 device_xname(sc->sc_dev), EPE_READ(BMCtl), EPE_READ(BMSts)); 643 } 644 645 static int 646 epe_ifinit(struct ifnet *ifp) 647 { 648 struct epe_softc *sc = ifp->if_softc; 649 int rc, s = splnet(); 650 651 callout_stop(&sc->epe_tick_ch); 652 EPE_WRITE(RXCtl, RXCtl_IA0 | RXCtl_BA | RXCtl_RCRCA | RXCtl_SRxON); 653 EPE_WRITE(TXCtl, TXCtl_STxON); 654 EPE_WRITE(GIIntMsk, GIIntMsk_INT); /* start interrupting */ 655 656 if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 657 rc = 0; 658 else if (rc != 0) 659 goto out; 660 661 callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc); 662 ifp->if_flags |= IFF_RUNNING; 663 out: 664 splx(s); 665 return 0; 666 } 667 668 static void 669 epe_ifstop(struct ifnet *ifp, int disable) 670 { 671 struct epe_softc *sc = ifp->if_softc; 672 673 674 EPE_WRITE(RXCtl, 0); 675 EPE_WRITE(TXCtl, 0); 676 EPE_WRITE(GIIntMsk, 0); 677 callout_stop(&sc->epe_tick_ch); 678 679 /* Down the MII. */ 680 mii_down(&sc->sc_mii); 681 682 ifp->if_flags &= ~IFF_RUNNING; 683 ifp->if_timer = 0; 684 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 685 } 686 687 static void 688 epe_setaddr(struct ifnet *ifp) 689 { 690 struct epe_softc *sc = ifp->if_softc; 691 struct ethercom *ec = &sc->sc_ec; 692 struct ether_multi *enm; 693 struct ether_multistep step; 694 uint8_t ias[2][ETHER_ADDR_LEN]; 695 uint32_t h, nma = 0, hashes[2] = { 0, 0 }; 696 uint32_t rxctl = EPE_READ(RXCtl); 697 698 /* disable receiver temporarily */ 699 EPE_WRITE(RXCtl, rxctl & ~RXCtl_SRxON); 700 701 rxctl &= ~(RXCtl_MA | RXCtl_PA | RXCtl_IA2 | RXCtl_IA3); 702 703 if (ifp->if_flags & IFF_PROMISC) 704 rxctl |= RXCtl_PA; 705 706 ifp->if_flags &= ~IFF_ALLMULTI; 707 708 ETHER_LOCK(ec); 709 ETHER_FIRST_MULTI(step, ec, enm); 710 while (enm != NULL) { 711 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 712 /* 713 * We must listen to a range of multicast addresses. 714 * For now, just accept all multicasts, rather than 715 * trying to set only those filter bits needed to match 716 * the range. (At this time, the only use of address 717 * ranges is for IP multicast routing, for which the 718 * range is big enough to require all bits set.) 719 */ 720 rxctl &= ~(RXCtl_IA2 | RXCtl_IA3); 721 rxctl |= RXCtl_MA; 722 hashes[0] = 0xffffffffUL; 723 hashes[1] = 0xffffffffUL; 724 ifp->if_flags |= IFF_ALLMULTI; 725 break; 726 } 727 728 if (nma < 2) { 729 /* We can program 2 perfect address filters for mcast */ 730 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 731 rxctl |= (1 << (nma + 2)); 732 } else { 733 /* 734 * XXX: Datasheet is not very clear here, I'm not sure 735 * if I'm doing this right. --joff 736 */ 737 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 738 739 /* Just want the 6 most-significant bits. */ 740 h = h >> 26; 741 742 hashes[ h / 32 ] |= (1 << (h % 32)); 743 rxctl |= RXCtl_MA; 744 } 745 ETHER_NEXT_MULTI(step, enm); 746 nma++; 747 } 748 ETHER_UNLOCK(ec); 749 750 EPE_WRITE(AFP, 0); 751 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 752 sc->sc_enaddr, ETHER_ADDR_LEN); 753 if (rxctl & RXCtl_IA2) { 754 EPE_WRITE(AFP, 2); 755 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 756 ias[0], ETHER_ADDR_LEN); 757 } 758 if (rxctl & RXCtl_IA3) { 759 EPE_WRITE(AFP, 3); 760 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 761 ias[1], ETHER_ADDR_LEN); 762 } 763 if (hashes[0] != 0 && hashes[1] != 0) { 764 EPE_WRITE(AFP, 7); 765 EPE_WRITE(HashTbl, hashes[0]); 766 EPE_WRITE(HashTbl + 4, hashes[1]); 767 } 768 EPE_WRITE(RXCtl, rxctl); 769 } 770
Indexes created Wed Oct 29 01:09:52 GMT 2025