epe.c revision 1.7
1 /* $NetBSD: epe.c,v 1.7 2006/03/29 04:16:45 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Jesse Off 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: epe.c,v 1.7 2006/03/29 04:16:45 thorpej Exp $"); 38 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/ioctl.h> 43 #include <sys/kernel.h> 44 #include <sys/proc.h> 45 #include <sys/malloc.h> 46 #include <sys/time.h> 47 #include <sys/device.h> 48 #include <uvm/uvm_extern.h> 49 50 #include <machine/bus.h> 51 #include <machine/intr.h> 52 53 #include <arm/cpufunc.h> 54 55 #include <arm/ep93xx/epsocvar.h> 56 #include <arm/ep93xx/ep93xxvar.h> 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_types.h> 61 #include <net/if_media.h> 62 #include <net/if_ether.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #ifdef INET 68 #include <netinet/in.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/in_var.h> 71 #include <netinet/ip.h> 72 #include <netinet/if_inarp.h> 73 #endif 74 75 #ifdef NS 76 #include <netns/ns.h> 77 #include <netns/ns_if.h> 78 #endif 79 80 #include "bpfilter.h" 81 #if NBPFILTER > 0 82 #include <net/bpf.h> 83 #include <net/bpfdesc.h> 84 #endif 85 86 #include <machine/bus.h> 87 88 #ifdef IPKDB_EP93XX 89 #include <ipkdb/ipkdb.h> 90 #endif 91 92 #include <arm/ep93xx/ep93xxreg.h> 93 #include <arm/ep93xx/epereg.h> 94 #include <arm/ep93xx/epevar.h> 95 96 #define DEFAULT_MDCDIV 32 97 98 #ifndef EPE_FAST 99 #define EPE_FAST 100 #endif 101 102 #ifndef EPE_FAST 103 #define EPE_READ(x) \ 104 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x)) 105 #define EPE_WRITE(x, y) \ 106 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x), (y)) 107 #define CTRLPAGE_DMASYNC(x, y, z) \ 108 bus_dmamap_sync(sc->sc_dmat, sc->ctrlpage_dmamap, (x), (y), (z)) 109 #else 110 #define EPE_READ(x) *(volatile u_int32_t *) \ 111 (EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x)) 112 #define EPE_WRITE(x, y) *(volatile u_int32_t *) \ 113 (EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x)) = y 114 #define CTRLPAGE_DMASYNC(x, y, z) 115 #endif /* ! EPE_FAST */ 116 117 static int epe_match(struct device *, struct cfdata *, void *); 118 static void epe_attach(struct device *, struct device *, void *); 119 static void epe_init(struct epe_softc *); 120 static int epe_intr(void* arg); 121 static int epe_gctx(struct epe_softc *); 122 static int epe_mediachange(struct ifnet *); 123 static void epe_mediastatus(struct ifnet *, struct ifmediareq *); 124 int epe_mii_readreg (struct device *, int, int); 125 void epe_mii_writereg (struct device *, int, int, int); 126 void epe_statchg (struct device *); 127 void epe_tick (void *); 128 static int epe_ifioctl (struct ifnet *, u_long, caddr_t); 129 static void epe_ifstart (struct ifnet *); 130 static void epe_ifwatchdog (struct ifnet *); 131 static int epe_ifinit (struct ifnet *); 132 static void epe_ifstop (struct ifnet *, int); 133 static void epe_setaddr (struct ifnet *); 134 135 CFATTACH_DECL(epe, sizeof(struct epe_softc), 136 epe_match, epe_attach, NULL, NULL); 137 138 static int 139 epe_match(struct device *parent, struct cfdata *match, void *aux) 140 { 141 return 2; 142 } 143 144 static void 145 epe_attach(struct device *parent, struct device *self, void *aux) 146 { 147 struct epe_softc *sc; 148 struct epsoc_attach_args *sa; 149 150 printf("\n"); 151 sc = (struct epe_softc*) self; 152 sa = aux; 153 sc->sc_iot = sa->sa_iot; 154 sc->sc_intr = sa->sa_intr; 155 sc->sc_dmat = sa->sa_dmat; 156 157 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 158 0, &sc->sc_ioh)) 159 panic("%s: Cannot map registers", self->dv_xname); 160 161 /* Fetch the Ethernet address from property if set. */ 162 if (devprop_get(self, "mac-addr", sc->sc_enaddr, 163 ETHER_ADDR_LEN, NULL) == ETHER_ADDR_LEN) { 164 bus_space_write_4(sc->sc_iot, sc->sc_ioh, EPE_AFP, 0); 165 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 166 sc->sc_enaddr, ETHER_ADDR_LEN); 167 } 168 169 ep93xx_intr_establish(sc->sc_intr, IPL_NET, epe_intr, sc); 170 epe_init(sc); 171 } 172 173 static int 174 epe_gctx(struct epe_softc *sc) 175 { 176 struct ifnet * ifp = &sc->sc_ec.ec_if; 177 u_int32_t *cur, ndq = 0; 178 179 /* Handle transmit completions */ 180 cur = (u_int32_t *)(EPE_READ(TXStsQCurAdd) - 181 sc->ctrlpage_dsaddr + sc->ctrlpage); 182 183 if (sc->TXStsQ_cur != cur) { 184 CTRLPAGE_DMASYNC(TX_QLEN * 2 * sizeof(u_int32_t), 185 TX_QLEN * sizeof(u_int32_t), BUS_DMASYNC_PREREAD); 186 } else { 187 return 0; 188 } 189 190 do { 191 u_int32_t tbi = *sc->TXStsQ_cur & 0x7fff; 192 struct mbuf *m = sc->txq[tbi].m; 193 194 if ((*sc->TXStsQ_cur & TXStsQ_TxWE) == 0) { 195 ifp->if_oerrors++; 196 } 197 bus_dmamap_unload(sc->sc_dmat, sc->txq[tbi].m_dmamap); 198 m_freem(m); 199 do { 200 sc->txq[tbi].m = NULL; 201 ndq++; 202 tbi = (tbi + 1) % TX_QLEN; 203 } while (sc->txq[tbi].m == m); 204 205 ifp->if_opackets++; 206 sc->TXStsQ_cur++; 207 if (sc->TXStsQ_cur >= sc->TXStsQ + TX_QLEN) { 208 sc->TXStsQ_cur = sc->TXStsQ; 209 } 210 } while (sc->TXStsQ_cur != cur); 211 212 sc->TXDQ_avail += ndq; 213 if (ifp->if_flags & IFF_OACTIVE) { 214 ifp->if_flags &= ~IFF_OACTIVE; 215 /* Disable end-of-tx-chain interrupt */ 216 EPE_WRITE(IntEn, IntEn_REOFIE); 217 } 218 return ndq; 219 } 220 221 static int 222 epe_intr(void *arg) 223 { 224 struct epe_softc *sc = (struct epe_softc *)arg; 225 struct ifnet * ifp = &sc->sc_ec.ec_if; 226 u_int32_t ndq = 0, irq, *cur; 227 228 irq = EPE_READ(IntStsC); 229 begin: 230 cur = (u_int32_t *)(EPE_READ(RXStsQCurAdd) - 231 sc->ctrlpage_dsaddr + sc->ctrlpage); 232 CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(u_int32_t), 233 RX_QLEN * 4 * sizeof(u_int32_t), 234 BUS_DMASYNC_PREREAD); 235 while (sc->RXStsQ_cur != cur) { 236 if ((sc->RXStsQ_cur[0] & (RXStsQ_RWE|RXStsQ_RFP|RXStsQ_EOB)) == 237 (RXStsQ_RWE|RXStsQ_RFP|RXStsQ_EOB)) { 238 u_int32_t bi = (sc->RXStsQ_cur[1] >> 16) & 0x7fff; 239 u_int32_t fl = sc->RXStsQ_cur[1] & 0xffff; 240 struct mbuf *m; 241 242 MGETHDR(m, M_DONTWAIT, MT_DATA); 243 if (m != NULL) MCLGET(m, M_DONTWAIT); 244 if (m != NULL && (m->m_flags & M_EXT)) { 245 bus_dmamap_unload(sc->sc_dmat, 246 sc->rxq[bi].m_dmamap); 247 sc->rxq[bi].m->m_pkthdr.rcvif = ifp; 248 sc->rxq[bi].m->m_pkthdr.len = 249 sc->rxq[bi].m->m_len = fl; 250 #if NBPFILTER > 0 251 if (ifp->if_bpf) 252 bpf_mtap(ifp->if_bpf, sc->rxq[bi].m); 253 #endif /* NBPFILTER > 0 */ 254 (*ifp->if_input)(ifp, sc->rxq[bi].m); 255 sc->rxq[bi].m = m; 256 bus_dmamap_load(sc->sc_dmat, 257 sc->rxq[bi].m_dmamap, 258 m->m_ext.ext_buf, MCLBYTES, 259 NULL, BUS_DMA_NOWAIT); 260 sc->RXDQ[bi * 2] = 261 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr; 262 } else { 263 /* Drop packets until we can get replacement 264 * empty mbufs for the RXDQ. 265 */ 266 if (m != NULL) { 267 m_freem(m); 268 } 269 ifp->if_ierrors++; 270 } 271 } else { 272 ifp->if_ierrors++; 273 } 274 275 ndq++; 276 277 sc->RXStsQ_cur += 2; 278 if (sc->RXStsQ_cur >= sc->RXStsQ + (RX_QLEN * 2)) { 279 sc->RXStsQ_cur = sc->RXStsQ; 280 } 281 } 282 283 if (ndq > 0) { 284 ifp->if_ipackets += ndq; 285 CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(u_int32_t), 286 RX_QLEN * 4 * sizeof(u_int32_t), 287 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 288 EPE_WRITE(RXStsEnq, ndq); 289 EPE_WRITE(RXDEnq, ndq); 290 ndq = 0; 291 } 292 293 if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 294 epe_ifstart(ifp); 295 } 296 297 irq = EPE_READ(IntStsC); 298 if ((irq & (IntSts_RxSQ|IntSts_ECI)) != 0) 299 goto begin; 300 301 return (1); 302 } 303 304 305 static void 306 epe_init(struct epe_softc *sc) 307 { 308 bus_dma_segment_t segs; 309 caddr_t addr; 310 int rsegs, err, i; 311 struct ifnet * ifp = &sc->sc_ec.ec_if; 312 int mdcdiv = DEFAULT_MDCDIV; 313 314 callout_init(&sc->epe_tick_ch); 315 316 /* Select primary Individual Address in Address Filter Pointer */ 317 EPE_WRITE(AFP, 0); 318 /* Read ethernet MAC, should already be set by bootrom */ 319 bus_space_read_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 320 sc->sc_enaddr, ETHER_ADDR_LEN); 321 printf("%s: MAC address %s\n", sc->sc_dev.dv_xname, 322 ether_sprintf(sc->sc_enaddr)); 323 324 /* Soft Reset the MAC */ 325 EPE_WRITE(SelfCtl, SelfCtl_RESET); 326 while(EPE_READ(SelfCtl) & SelfCtl_RESET); 327 328 /* suggested magic initialization values from datasheet */ 329 EPE_WRITE(RXBufThrshld, 0x800040); 330 EPE_WRITE(TXBufThrshld, 0x200010); 331 EPE_WRITE(RXStsThrshld, 0x40002); 332 EPE_WRITE(TXStsThrshld, 0x40002); 333 EPE_WRITE(RXDThrshld, 0x40002); 334 EPE_WRITE(TXDThrshld, 0x40002); 335 336 /* Allocate a page of memory for descriptor and status queues */ 337 err = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, 0, PAGE_SIZE, 338 &segs, 1, &rsegs, BUS_DMA_WAITOK); 339 if (err == 0) { 340 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, PAGE_SIZE, 341 &sc->ctrlpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT)); 342 } 343 if (err == 0) { 344 err = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 345 0, BUS_DMA_WAITOK, &sc->ctrlpage_dmamap); 346 } 347 if (err == 0) { 348 err = bus_dmamap_load(sc->sc_dmat, sc->ctrlpage_dmamap, 349 sc->ctrlpage, PAGE_SIZE, NULL, BUS_DMA_WAITOK); 350 } 351 if (err != 0) { 352 panic("%s: Cannot get DMA memory", sc->sc_dev.dv_xname); 353 } 354 sc->ctrlpage_dsaddr = sc->ctrlpage_dmamap->dm_segs[0].ds_addr; 355 bzero(sc->ctrlpage, PAGE_SIZE); 356 357 /* Set up pointers to start of each queue in kernel addr space. 358 * Each descriptor queue or status queue entry uses 2 words 359 */ 360 sc->TXDQ = (u_int32_t *)sc->ctrlpage; 361 sc->TXDQ_cur = sc->TXDQ; 362 sc->TXDQ_avail = TX_QLEN - 1; 363 sc->TXStsQ = &sc->TXDQ[TX_QLEN * 2]; 364 sc->TXStsQ_cur = sc->TXStsQ; 365 sc->RXDQ = &sc->TXStsQ[TX_QLEN]; 366 sc->RXStsQ = &sc->RXDQ[RX_QLEN * 2]; 367 sc->RXStsQ_cur = sc->RXStsQ; 368 369 /* Program each queue's start addr, cur addr, and len registers 370 * with the physical addresses. 371 */ 372 addr = (caddr_t)sc->ctrlpage_dmamap->dm_segs[0].ds_addr; 373 EPE_WRITE(TXDQBAdd, (u_int32_t)addr); 374 EPE_WRITE(TXDQCurAdd, (u_int32_t)addr); 375 EPE_WRITE(TXDQBLen, TX_QLEN * 2 * sizeof(u_int32_t)); 376 377 addr += (sc->TXStsQ - sc->TXDQ) * sizeof(u_int32_t); 378 EPE_WRITE(TXStsQBAdd, (u_int32_t)addr); 379 EPE_WRITE(TXStsQCurAdd, (u_int32_t)addr); 380 EPE_WRITE(TXStsQBLen, TX_QLEN * sizeof(u_int32_t)); 381 382 addr += (sc->RXDQ - sc->TXStsQ) * sizeof(u_int32_t); 383 EPE_WRITE(RXDQBAdd, (u_int32_t)addr); 384 EPE_WRITE(RXDCurAdd, (u_int32_t)addr); 385 EPE_WRITE(RXDQBLen, RX_QLEN * 2 * sizeof(u_int32_t)); 386 387 addr += (sc->RXStsQ - sc->RXDQ) * sizeof(u_int32_t); 388 EPE_WRITE(RXStsQBAdd, (u_int32_t)addr); 389 EPE_WRITE(RXStsQCurAdd, (u_int32_t)addr); 390 EPE_WRITE(RXStsQBLen, RX_QLEN * 2 * sizeof(u_int32_t)); 391 392 /* Populate the RXDQ with mbufs */ 393 for(i = 0; i < RX_QLEN; i++) { 394 struct mbuf *m; 395 396 bus_dmamap_create(sc->sc_dmat, MCLBYTES, TX_QLEN/4, MCLBYTES, 0, 397 BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 398 MGETHDR(m, M_WAIT, MT_DATA); 399 MCLGET(m, M_WAIT); 400 sc->rxq[i].m = m; 401 bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 402 m->m_ext.ext_buf, MCLBYTES, NULL, 403 BUS_DMA_WAITOK); 404 405 sc->RXDQ[i * 2] = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr; 406 sc->RXDQ[i * 2 + 1] = (i << 16) | MCLBYTES; 407 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 408 MCLBYTES, BUS_DMASYNC_PREREAD); 409 } 410 411 for(i = 0; i < TX_QLEN; i++) { 412 bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 413 (BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW), 414 &sc->txq[i].m_dmamap); 415 sc->txq[i].m = NULL; 416 sc->TXDQ[i * 2 + 1] = (i << 16); 417 } 418 419 /* Divide HCLK by 32 for MDC clock */ 420 if (device_cfdata(&sc->sc_dev)->cf_flags) 421 mdcdiv = device_cfdata(&sc->sc_dev)->cf_flags; 422 EPE_WRITE(SelfCtl, (SelfCtl_MDCDIV(mdcdiv)|SelfCtl_PSPRS)); 423 424 sc->sc_mii.mii_ifp = ifp; 425 sc->sc_mii.mii_readreg = epe_mii_readreg; 426 sc->sc_mii.mii_writereg = epe_mii_writereg; 427 sc->sc_mii.mii_statchg = epe_statchg; 428 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, epe_mediachange, 429 epe_mediastatus); 430 mii_attach((struct device *)sc, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 431 MII_OFFSET_ANY, 0); 432 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 433 434 EPE_WRITE(BMCtl, BMCtl_RxEn|BMCtl_TxEn); 435 EPE_WRITE(IntEn, IntEn_REOFIE); 436 /* maximum valid max frame length */ 437 EPE_WRITE(MaxFrmLen, (0x7ff << 16)|MHLEN); 438 /* wait for receiver ready */ 439 while((EPE_READ(BMSts) & BMSts_RxAct) == 0); 440 /* enqueue the entries in RXStsQ and RXDQ */ 441 CTRLPAGE_DMASYNC(0, sc->ctrlpage_dmamap->dm_mapsize, 442 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 443 EPE_WRITE(RXDEnq, RX_QLEN - 1); 444 EPE_WRITE(RXStsEnq, RX_QLEN - 1); 445 446 /* 447 * We can support 802.1Q VLAN-sized frames. 448 */ 449 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 450 451 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 452 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 453 ifp->if_ioctl = epe_ifioctl; 454 ifp->if_start = epe_ifstart; 455 ifp->if_watchdog = epe_ifwatchdog; 456 ifp->if_init = epe_ifinit; 457 ifp->if_stop = epe_ifstop; 458 ifp->if_timer = 0; 459 ifp->if_softc = sc; 460 IFQ_SET_READY(&ifp->if_snd); 461 if_attach(ifp); 462 ether_ifattach(ifp, (sc)->sc_enaddr); 463 } 464 465 static int 466 epe_mediachange(ifp) 467 struct ifnet *ifp; 468 { 469 if (ifp->if_flags & IFF_UP) 470 epe_ifinit(ifp); 471 return (0); 472 } 473 474 static void 475 epe_mediastatus(ifp, ifmr) 476 struct ifnet *ifp; 477 struct ifmediareq *ifmr; 478 { 479 struct epe_softc *sc = ifp->if_softc; 480 481 mii_pollstat(&sc->sc_mii); 482 ifmr->ifm_active = sc->sc_mii.mii_media_active; 483 ifmr->ifm_status = sc->sc_mii.mii_media_status; 484 } 485 486 487 int 488 epe_mii_readreg(self, phy, reg) 489 struct device *self; 490 int phy, reg; 491 { 492 u_int32_t d, v; 493 struct epe_softc *sc; 494 495 sc = (struct epe_softc *)self; 496 d = EPE_READ(SelfCtl); 497 EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */ 498 EPE_WRITE(MIICmd, (MIICmd_READ | (phy << 5) | reg)); 499 while(EPE_READ(MIISts) & MIISts_BUSY); 500 v = EPE_READ(MIIData); 501 EPE_WRITE(SelfCtl, d); /* restore old value */ 502 return v; 503 } 504 505 void 506 epe_mii_writereg(self, phy, reg, val) 507 struct device *self; 508 int phy, reg, val; 509 { 510 struct epe_softc *sc; 511 u_int32_t d; 512 513 sc = (struct epe_softc *)self; 514 d = EPE_READ(SelfCtl); 515 EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */ 516 EPE_WRITE(MIIData, val); 517 EPE_WRITE(MIICmd, (MIICmd_WRITE | (phy << 5) | reg)); 518 while(EPE_READ(MIISts) & MIISts_BUSY); 519 EPE_WRITE(SelfCtl, d); /* restore old value */ 520 } 521 522 523 void 524 epe_statchg(self) 525 struct device *self; 526 { 527 struct epe_softc *sc = (struct epe_softc *)self; 528 u_int32_t reg; 529 530 /* 531 * We must keep the MAC and the PHY in sync as 532 * to the status of full-duplex! 533 */ 534 reg = EPE_READ(TestCtl); 535 if (sc->sc_mii.mii_media_active & IFM_FDX) 536 reg |= TestCtl_MFDX; 537 else 538 reg &= ~TestCtl_MFDX; 539 EPE_WRITE(TestCtl, reg); 540 } 541 542 void 543 epe_tick(arg) 544 void *arg; 545 { 546 struct epe_softc* sc = (struct epe_softc *)arg; 547 struct ifnet * ifp = &sc->sc_ec.ec_if; 548 int s; 549 u_int32_t misses; 550 551 ifp->if_collisions += EPE_READ(TXCollCnt); 552 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 553 misses = EPE_READ(RXMissCnt); 554 if (misses > 0) 555 printf("%s: %d rx misses\n", sc->sc_dev.dv_xname, misses); 556 557 s = splnet(); 558 if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 559 epe_ifstart(ifp); 560 } 561 splx(s); 562 563 mii_tick(&sc->sc_mii); 564 callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc); 565 } 566 567 568 static int 569 epe_ifioctl(ifp, cmd, data) 570 struct ifnet *ifp; 571 u_long cmd; 572 caddr_t data; 573 { 574 struct epe_softc *sc = ifp->if_softc; 575 struct ifreq *ifr = (struct ifreq *)data; 576 int s, error; 577 578 s = splnet(); 579 switch(cmd) { 580 case SIOCSIFMEDIA: 581 case SIOCGIFMEDIA: 582 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 583 break; 584 default: 585 error = ether_ioctl(ifp, cmd, data); 586 if (error == ENETRESET) { 587 if (ifp->if_flags & IFF_RUNNING) 588 epe_setaddr(ifp); 589 error = 0; 590 } 591 } 592 splx(s); 593 return error; 594 } 595 596 static void 597 epe_ifstart(ifp) 598 struct ifnet *ifp; 599 { 600 struct epe_softc *sc = (struct epe_softc *)ifp->if_softc; 601 struct mbuf *m; 602 bus_dma_segment_t *segs; 603 int s, bi, err, nsegs, ndq; 604 605 s = splnet(); 606 start: 607 ndq = 0; 608 if (sc->TXDQ_avail == 0) { 609 if (epe_gctx(sc) == 0) { 610 /* Enable End-Of-TX-Chain interrupt */ 611 EPE_WRITE(IntEn, IntEn_REOFIE|IntEn_ECIE); 612 ifp->if_flags |= IFF_OACTIVE; 613 ifp->if_timer = 10; 614 splx(s); 615 return; 616 } 617 } 618 619 bi = sc->TXDQ_cur - sc->TXDQ; 620 621 IFQ_POLL(&ifp->if_snd, m); 622 if (m == NULL) { 623 splx(s); 624 return; 625 } 626 more: 627 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 628 BUS_DMA_NOWAIT)) || 629 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 630 sc->txq[bi].m_dmamap->dm_nsegs > (sc->TXDQ_avail - ndq)) { 631 /* Copy entire mbuf chain to new and 32-bit aligned storage */ 632 struct mbuf *mn; 633 634 if (err == 0) 635 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 636 637 MGETHDR(mn, M_DONTWAIT, MT_DATA); 638 if (mn == NULL) goto stop; 639 if (m->m_pkthdr.len > (MHLEN & (~0x3))) { 640 MCLGET(mn, M_DONTWAIT); 641 if ((mn->m_flags & M_EXT) == 0) { 642 m_freem(mn); 643 goto stop; 644 } 645 } 646 mn->m_data = (caddr_t)(((u_int32_t)mn->m_data + 0x3) & (~0x3)); 647 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, caddr_t)); 648 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 649 IFQ_DEQUEUE(&ifp->if_snd, m); 650 m_freem(m); 651 m = mn; 652 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 653 BUS_DMA_NOWAIT); 654 } else { 655 IFQ_DEQUEUE(&ifp->if_snd, m); 656 } 657 658 #if NBPFILTER > 0 659 if (ifp->if_bpf) 660 bpf_mtap(ifp->if_bpf, m); 661 #endif /* NBPFILTER > 0 */ 662 663 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 664 segs = sc->txq[bi].m_dmamap->dm_segs; 665 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 666 sc->txq[bi].m_dmamap->dm_mapsize, 667 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 668 669 /* XXX: This driver hasn't been tested w/nsegs > 1 */ 670 while (nsegs > 0) { 671 nsegs--; 672 sc->txq[bi].m = m; 673 sc->TXDQ[bi * 2] = segs->ds_addr; 674 if (nsegs == 0) 675 sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16) | 676 (1 << 31); 677 else 678 sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16); 679 segs++; 680 bi = (bi + 1) % TX_QLEN; 681 ndq++; 682 } 683 684 685 /* 686 * Enqueue another. Don't do more than half the available 687 * descriptors before telling the MAC about them 688 */ 689 if ((sc->TXDQ_avail - ndq) > 0 && ndq < TX_QLEN / 2) { 690 IFQ_POLL(&ifp->if_snd, m); 691 if (m != NULL) { 692 goto more; 693 } 694 } 695 stop: 696 if (ndq > 0) { 697 sc->TXDQ_avail -= ndq; 698 sc->TXDQ_cur = &sc->TXDQ[bi]; 699 CTRLPAGE_DMASYNC(0, TX_QLEN * 2 * sizeof(u_int32_t), 700 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 701 EPE_WRITE(TXDEnq, ndq); 702 } 703 704 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 705 goto start; 706 707 splx(s); 708 return; 709 } 710 711 static void 712 epe_ifwatchdog(ifp) 713 struct ifnet *ifp; 714 { 715 struct epe_softc *sc = (struct epe_softc *)ifp->if_softc; 716 717 if ((ifp->if_flags & IFF_RUNNING) == 0) 718 return; 719 printf("%s: device timeout, BMCtl = 0x%08x, BMSts = 0x%08x\n", 720 sc->sc_dev.dv_xname, EPE_READ(BMCtl), EPE_READ(BMSts)); 721 } 722 723 static int 724 epe_ifinit(ifp) 725 struct ifnet *ifp; 726 { 727 struct epe_softc *sc = ifp->if_softc; 728 int s = splnet(); 729 730 callout_stop(&sc->epe_tick_ch); 731 EPE_WRITE(RXCtl, RXCtl_IA0|RXCtl_BA|RXCtl_RCRCA|RXCtl_SRxON); 732 EPE_WRITE(TXCtl, TXCtl_STxON); 733 EPE_WRITE(GIIntMsk, GIIntMsk_INT); /* start interrupting */ 734 mii_mediachg(&sc->sc_mii); 735 callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc); 736 ifp->if_flags |= IFF_RUNNING; 737 splx(s); 738 return 0; 739 } 740 741 static void 742 epe_ifstop(ifp, disable) 743 struct ifnet *ifp; 744 int disable; 745 { 746 struct epe_softc *sc = ifp->if_softc; 747 748 749 EPE_WRITE(RXCtl, 0); 750 EPE_WRITE(TXCtl, 0); 751 EPE_WRITE(GIIntMsk, 0); 752 callout_stop(&sc->epe_tick_ch); 753 754 /* Down the MII. */ 755 mii_down(&sc->sc_mii); 756 757 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 758 ifp->if_timer = 0; 759 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 760 } 761 762 static void 763 epe_setaddr(ifp) 764 struct ifnet *ifp; 765 { 766 struct epe_softc *sc = ifp->if_softc; 767 struct ethercom *ac = &sc->sc_ec; 768 struct ether_multi *enm; 769 struct ether_multistep step; 770 u_int8_t ias[2][ETHER_ADDR_LEN]; 771 u_int32_t h, nma = 0, hashes[2] = { 0, 0 }; 772 u_int32_t rxctl = EPE_READ(RXCtl); 773 774 /* disable receiver temporarily */ 775 EPE_WRITE(RXCtl, rxctl & ~RXCtl_SRxON); 776 777 rxctl &= ~(RXCtl_MA|RXCtl_PA|RXCtl_IA2|RXCtl_IA3); 778 779 if (ifp->if_flags & IFF_PROMISC) { 780 rxctl |= RXCtl_PA; 781 } 782 783 ifp->if_flags &= ~IFF_ALLMULTI; 784 785 ETHER_FIRST_MULTI(step, ac, enm); 786 while (enm != NULL) { 787 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 788 /* 789 * We must listen to a range of multicast addresses. 790 * For now, just accept all multicasts, rather than 791 * trying to set only those filter bits needed to match 792 * the range. (At this time, the only use of address 793 * ranges is for IP multicast routing, for which the 794 * range is big enough to require all bits set.) 795 */ 796 rxctl &= ~(RXCtl_IA2|RXCtl_IA3); 797 rxctl |= RXCtl_MA; 798 hashes[0] = 0xffffffffUL; 799 hashes[1] = 0xffffffffUL; 800 ifp->if_flags |= IFF_ALLMULTI; 801 break; 802 } 803 804 if (nma < 2) { 805 /* We can program 2 perfect address filters for mcast */ 806 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 807 rxctl |= (1 << (nma + 2)); 808 } else { 809 /* 810 * XXX: Datasheet is not very clear here, I'm not sure 811 * if I'm doing this right. --joff 812 */ 813 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 814 815 /* Just want the 6 most-significant bits. */ 816 h = h >> 26; 817 818 hashes[ h / 32 ] |= (1 << (h % 32)); 819 rxctl |= RXCtl_MA; 820 } 821 ETHER_NEXT_MULTI(step, enm); 822 nma++; 823 } 824 825 EPE_WRITE(AFP, 0); 826 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 827 sc->sc_enaddr, ETHER_ADDR_LEN); 828 if (rxctl & RXCtl_IA2) { 829 EPE_WRITE(AFP, 2); 830 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 831 ias[0], ETHER_ADDR_LEN); 832 } 833 if (rxctl & RXCtl_IA3) { 834 EPE_WRITE(AFP, 3); 835 bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd, 836 ias[1], ETHER_ADDR_LEN); 837 } 838 if (hashes[0] != 0 && hashes[1] != 0) { 839 EPE_WRITE(AFP, 7); 840 EPE_WRITE(HashTbl, hashes[0]); 841 EPE_WRITE(HashTbl + 4, hashes[1]); 842 } 843 EPE_WRITE(RXCtl, rxctl); 844 } 845
Indexes created Tue Sep 30 17:09:57 GMT 2025