eppcic.c revision 1.1
1 /* $NetBSD: eppcic.c,v 1.1 2005/11/12 05:33:23 hamajima Exp $ */ 2 3 /* 4 * Copyright (c) 2005 HAMAJIMA Katsuomi. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: eppcic.c,v 1.1 2005/11/12 05:33:23 hamajima Exp $"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/malloc.h> 35 #include <sys/device.h> 36 #include <sys/kthread.h> 37 #include <uvm/uvm_param.h> 38 #include <machine/bus.h> 39 #include <dev/pcmcia/pcmciareg.h> 40 #include <dev/pcmcia/pcmciavar.h> 41 #include <dev/pcmcia/pcmciachip.h> 42 #include <arm/ep93xx/epsocvar.h> 43 #include <arm/ep93xx/epgpiovar.h> 44 #include <arm/ep93xx/eppcicvar.h> 45 #include <arm/ep93xx/ep93xxreg.h> 46 #include <arm/ep93xx/epsmcreg.h> 47 #include "epled.h" 48 #if NEPLED > 0 49 #include <arm/ep93xx/epledvar.h> 50 #endif 51 52 #include "epgpio.h" 53 #if NEPGPIO == 0 54 #error "epgpio requires in eppcic" 55 #endif 56 57 #ifdef EPPCIC_DEBUG 58 int eppcic_debug = EPPCIC_DEBUG; 59 #define DPRINTFN(n,x) if (eppcic_debug>(n)) printf x; 60 #else 61 #define DPRINTFN(n,x) 62 #endif 63 64 /* Mem & I/O */ 65 #define SOCKET0_MCCD1 1 /* pin36/pin26 (negative) Card Detect 1 */ 66 #define SOCKET0_MCCD2 2 /* pin67/pin25 (negative) Card Detect 2 */ 67 #define SOCKET0_VS1 5 /* pin33/pin43 (negative) Voltage Sense 1 */ 68 #define SOCKET0_VS2 7 /* pin57/pin40 (negative) Voltage Sense 2 */ 69 /* Memory */ 70 #define SOCKET0_WP 0 /* pin33/pin24 Write Protect */ 71 #define SOCKET0_MCBVD1 3 /* pin63/pin46 Battery Voltage Detect 1 */ 72 #define SOCKET0_MCBVD2 4 /* pin62/pin45 Battery Voltage Detect 2 */ 73 #define SOCKET0_READY 6 /* pin16/pin37 Ready */ 74 /* I/O */ 75 #define SOCKET0_STSCHG 3 /* pin63/pin46 (negative) Status Change */ 76 #define SOCKET0_SPKR 4 /* pin62/pin45 (negative) Speaker */ 77 #define SOCKET0_IREQ 6 /* pin16/pin37 Interrupt Request */ 78 79 struct eppcic_handle { 80 int ph_socket; /* socket number */ 81 struct eppcic_softc *ph_sc; 82 struct device *ph_card; 83 int (*ph_ih_func)(void *); 84 void *ph_ih_arg; 85 struct proc *ph_event_thread; 86 int ph_run; /* ktread running */ 87 int ph_width; /* 8 or 16 */ 88 int ph_vcc; /* 3 or 5 */ 89 int ph_status[2]; /* cd1 and cd2 */ 90 int ph_port; /* GPIO port */ 91 int ph_cd[2]; /* card detect */ 92 int ph_vs[2]; /* voltage sense */ 93 int ph_ireq; /* interrupt request */ 94 struct { 95 bus_size_t reg; 96 bus_addr_t base; 97 bus_size_t size; 98 } ph_space[3]; 99 #define IO 0 100 #define COMMON 1 101 #define ATTRIBUTE 2 102 }; 103 104 static int eppcic_intr_carddetect(void *); 105 static int eppcic_intr_socket(void *); 106 static int eppcic_print(void *, const char *); 107 static void eppcic_create_event_thread(void *); 108 static void eppcic_event_thread(void *); 109 void eppcic_shutdown(void *); 110 111 static int eppcic_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 112 struct pcmcia_mem_handle *); 113 static void eppcic_mem_free(pcmcia_chipset_handle_t, 114 struct pcmcia_mem_handle *); 115 static int eppcic_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, bus_size_t, 116 struct pcmcia_mem_handle *, bus_size_t *, int *); 117 static void eppcic_mem_unmap(pcmcia_chipset_handle_t, int); 118 static int eppcic_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, bus_size_t, 119 bus_size_t, struct pcmcia_io_handle *); 120 static void eppcic_io_free(pcmcia_chipset_handle_t, struct pcmcia_io_handle *); 121 static int eppcic_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, bus_size_t, 122 struct pcmcia_io_handle *, int *); 123 static void eppcic_io_unmap(pcmcia_chipset_handle_t, int); 124 static void *eppcic_intr_establish(pcmcia_chipset_handle_t, 125 struct pcmcia_function *, 126 int, int (*)(void *), void *); 127 static void eppcic_intr_disestablish(pcmcia_chipset_handle_t, void *); 128 static void eppcic_socket_enable(pcmcia_chipset_handle_t); 129 static void eppcic_socket_disable(pcmcia_chipset_handle_t); 130 static void eppcic_socket_settype(pcmcia_chipset_handle_t, int); 131 132 static void eppcic_attach_socket(struct eppcic_handle *); 133 static void eppcic_config_socket(struct eppcic_handle *); 134 static int eppcic_get_voltage(struct eppcic_handle *); 135 static void eppcic_set_pcreg(struct eppcic_handle *, int); 136 137 static struct pcmcia_chip_functions eppcic_functions = { 138 eppcic_mem_alloc, eppcic_mem_free, 139 eppcic_mem_map, eppcic_mem_unmap, 140 eppcic_io_alloc, eppcic_io_free, 141 eppcic_io_map, eppcic_io_unmap, 142 eppcic_intr_establish, eppcic_intr_disestablish, 143 eppcic_socket_enable, eppcic_socket_disable, 144 eppcic_socket_settype 145 }; 146 147 void 148 eppcic_attach_common(struct device *parent, struct device *self, void *aux, 149 eppcic_chipset_tag_t pcic) 150 { 151 struct eppcic_softc *sc = (struct eppcic_softc *)self; 152 struct epsoc_attach_args *sa = aux; 153 struct eppcic_handle *ph; 154 int reg; 155 int i; 156 157 if (!sa->sa_gpio) { 158 printf("%s: epgpio requires\n", self->dv_xname); 159 return; 160 } 161 sc->sc_gpio = sa->sa_gpio; 162 sc->sc_iot = sa->sa_iot; 163 sc->sc_hclk = sa->sa_hclk; 164 sc->sc_pcic = pcic; 165 sc->sc_enable = 0; 166 if (bus_space_map(sa->sa_iot, sa->sa_addr, 167 sa->sa_size, 0, &sc->sc_ioh)){ 168 printf("%s: Cannot map registers\n", self->dv_xname); 169 return; 170 } 171 printf("\n"); 172 173 #if NEPLED > 0 174 epled_green_on(); 175 epled_red_off(); 176 #endif 177 /* socket 0 */ 178 if (!(ph = malloc(sizeof(struct eppcic_handle), M_DEVBUF, M_NOWAIT))) { 179 printf("%s: Cannot allocate memory\n", self->dv_xname); 180 return; /* ENOMEM */ 181 } 182 sc->sc_ph[0] = ph; 183 ph->ph_sc = sc; 184 ph->ph_socket = 0; 185 ph->ph_port = PORT_F; 186 ph->ph_cd[0] = SOCKET0_MCCD1; 187 ph->ph_cd[1] = SOCKET0_MCCD2; 188 ph->ph_vs[0] = SOCKET0_VS1; 189 ph->ph_vs[1] = SOCKET0_VS2; 190 ph->ph_ireq = SOCKET0_IREQ; 191 ph->ph_space[IO].reg = EP93XX_PCMCIA0_IO; 192 ph->ph_space[IO].base = EP93XX_PCMCIA0_HWBASE + EP93XX_PCMCIA_IO; 193 ph->ph_space[IO].size = EP93XX_PCMCIA_IO_SIZE; 194 ph->ph_space[COMMON].reg = EP93XX_PCMCIA0_Common; 195 ph->ph_space[COMMON].base = EP93XX_PCMCIA0_HWBASE 196 + EP93XX_PCMCIA_COMMON; 197 ph->ph_space[COMMON].size = EP93XX_PCMCIA_COMMON_SIZE; 198 ph->ph_space[ATTRIBUTE].reg = EP93XX_PCMCIA0_Attribute; 199 ph->ph_space[ATTRIBUTE].base = EP93XX_PCMCIA0_HWBASE 200 + EP93XX_PCMCIA_ATTRIBUTE; 201 ph->ph_space[ATTRIBUTE].size = EP93XX_PCMCIA_ATTRIBUTE_SIZE; 202 eppcic_attach_socket(ph); 203 204 reg = EP93XX_PCMCIA_WEN | (pcic->socket_type)(sc, 0); 205 bus_space_write_4(sc->sc_iot, sc->sc_ioh, EP93XX_PCMCIA_Ctrl, 206 EP93XX_PCMCIA_RST | reg); 207 delay(10); 208 bus_space_write_4(sc->sc_iot, sc->sc_ioh, EP93XX_PCMCIA_Ctrl, reg); 209 delay(500); 210 211 for (i = 0; i < EP93XX_PCMCIA_NSOCKET; i++) 212 eppcic_config_socket(sc->sc_ph[i]); 213 #if NEPLED > 0 214 epled_green_off(); 215 #endif 216 } 217 218 static void 219 eppcic_attach_socket(struct eppcic_handle *ph) 220 { 221 struct eppcic_softc *sc = ph->ph_sc; 222 eppcic_chipset_tag_t pcic = sc->sc_pcic; 223 int wait; 224 225 ph->ph_width = 16; 226 ph->ph_vcc = 3; 227 ph->ph_event_thread = NULL; 228 ph->ph_run = 0; 229 ph->ph_ih_func = NULL; 230 ph->ph_ih_arg = NULL; 231 epgpio_in(sc->sc_gpio, ph->ph_port, ph->ph_cd[0]); 232 epgpio_in(sc->sc_gpio, ph->ph_port, ph->ph_cd[1]); 233 epgpio_in(sc->sc_gpio, ph->ph_port, ph->ph_vs[0]); 234 epgpio_in(sc->sc_gpio, ph->ph_port, ph->ph_vs[1]); 235 ph->ph_status[0] = epgpio_read(sc->sc_gpio, ph->ph_port, ph->ph_cd[0]); 236 ph->ph_status[1] = epgpio_read(sc->sc_gpio, ph->ph_port, ph->ph_cd[1]); 237 wait = (pcic->power_ctl)(sc, ph->ph_socket, POWER_OFF); 238 delay(wait); 239 eppcic_set_pcreg(ph, ph->ph_space[IO].reg); 240 eppcic_set_pcreg(ph, ph->ph_space[COMMON].reg); 241 eppcic_set_pcreg(ph, ph->ph_space[ATTRIBUTE].reg); 242 wait = (pcic->power_ctl)(sc, ph->ph_socket, POWER_ON); 243 delay(wait); 244 } 245 246 static void 247 eppcic_config_socket(struct eppcic_handle *ph) 248 { 249 struct eppcic_softc *sc = ph->ph_sc; 250 eppcic_chipset_tag_t pcic = sc->sc_pcic; 251 struct pcmciabus_attach_args paa; 252 int wait; 253 254 paa.paa_busname = "pcmcia"; 255 paa.pct = (pcmcia_chipset_tag_t)&eppcic_functions; 256 paa.pch = (pcmcia_chipset_handle_t)ph; 257 paa.iobase = ph->ph_space[IO].base; 258 paa.iosize = ph->ph_space[IO].size; 259 ph->ph_card = config_found_ia((void*)sc, "pcmciabus", &paa, 260 eppcic_print); 261 262 epgpio_intr_establish(sc->sc_gpio, ph->ph_port, ph->ph_cd[0], 263 EDGE_TRIGGER | FALLING_EDGE | DEBOUNCE, 264 IPL_TTY, eppcic_intr_carddetect, ph); 265 epgpio_intr_establish(sc->sc_gpio, ph->ph_port, ph->ph_cd[1], 266 EDGE_TRIGGER | RISING_EDGE | DEBOUNCE, 267 IPL_TTY, eppcic_intr_carddetect, ph); 268 wait = (pcic->power_ctl)(sc, ph->ph_socket, POWER_OFF); 269 delay(wait); 270 271 kthread_create(eppcic_create_event_thread, ph); 272 } 273 274 static int 275 eppcic_print(void *arg, const char *pnp) 276 { 277 return (UNCONF); 278 } 279 280 static void 281 eppcic_create_event_thread(void *arg) 282 { 283 struct eppcic_handle *ph = arg; 284 struct eppcic_softc *sc = ph->ph_sc; 285 286 ph->ph_status[0] = epgpio_read(sc->sc_gpio, ph->ph_port, ph->ph_cd[0]); 287 ph->ph_status[1] = epgpio_read(sc->sc_gpio, ph->ph_port, ph->ph_cd[1]); 288 289 DPRINTFN(1, ("eppcic_create_event_thread: cd1=%d, cd2=%d\n",ph->ph_status[0],ph->ph_status[1])); 290 291 if (!(ph->ph_status[0] | ph->ph_status[1])) 292 pcmcia_card_attach(ph->ph_card); 293 294 ph->ph_run = 1; 295 kthread_create1(eppcic_event_thread, ph, &ph->ph_event_thread, 296 "%s,%d", sc->sc_dev.dv_xname, ph->ph_socket); 297 } 298 299 static void 300 eppcic_event_thread(void *arg) 301 { 302 struct eppcic_handle *ph = arg; 303 304 for (;;) { 305 tsleep(ph, PWAIT, "CSC wait", 0); 306 if (!ph->ph_run) 307 break; 308 309 DPRINTFN(1, ("eppcic_event_thread: cd1=%d, cd2=%d\n",ph->ph_status[0],ph->ph_status[1])); 310 311 if (!ph->ph_status[0] && !ph->ph_status[1]) 312 pcmcia_card_attach(ph->ph_card); 313 else if (ph->ph_status[0] && ph->ph_status[1]) 314 pcmcia_card_detach(ph->ph_card, DETACH_FORCE); 315 } 316 317 DPRINTFN(1, ("eppcic_event_thread: run=%d\n",ph->ph_run)); 318 ph->ph_event_thread = NULL; 319 kthread_exit(0); 320 } 321 322 void 323 eppcic_shutdown(void *arg) 324 { 325 struct eppcic_handle *ph = arg; 326 327 DPRINTFN(1, ("eppcic_shutdown\n")); 328 ph->ph_run = 0; 329 wakeup(ph); 330 } 331 332 static int 333 eppcic_intr_carddetect(void *arg) 334 { 335 struct eppcic_handle *ph = arg; 336 struct eppcic_softc *sc = ph->ph_sc; 337 int nstatus[2]; 338 339 nstatus[0] = epgpio_read(sc->sc_gpio, ph->ph_port, ph->ph_cd[0]); 340 nstatus[1] = epgpio_read(sc->sc_gpio, ph->ph_port, ph->ph_cd[1]); 341 342 DPRINTFN(1, ("eppcic_intr: cd1=%#x, cd2=%#x\n",nstatus[0],nstatus[1])); 343 344 if (nstatus[0] != ph->ph_status[0] || nstatus[1] != ph->ph_status[1]) 345 wakeup(ph); 346 ph->ph_status[0] = nstatus[0]; 347 ph->ph_status[1] = nstatus[1]; 348 return 0; 349 } 350 351 static int 352 eppcic_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 353 struct pcmcia_mem_handle *pmh) 354 { 355 struct eppcic_handle *ph = (struct eppcic_handle *)pch; 356 struct eppcic_softc *sc = ph->ph_sc; 357 358 DPRINTFN(1, ("eppcic_mem_alloc: size=%#x\n",(unsigned)size)); 359 360 pmh->memt = sc->sc_iot; 361 return 0; 362 } 363 364 static void 365 eppcic_mem_free(pcmcia_chipset_handle_t pch, struct pcmcia_mem_handle *pmh) 366 { 367 DPRINTFN(1, ("eppcic_mem_free\n")); 368 } 369 370 static int 371 eppcic_mem_map(pcmcia_chipset_handle_t pch, int kind, bus_addr_t addr, 372 bus_size_t size, struct pcmcia_mem_handle *pmh, 373 bus_size_t *offsetp, int *windowp) 374 { 375 struct eppcic_handle *ph = (struct eppcic_handle *)pch; 376 struct eppcic_softc *sc = ph->ph_sc; 377 bus_addr_t pa; 378 int err; 379 380 DPRINTFN(1, ("eppcic_mem_map: kind=%d, addr=%#x, size=%#x\n",kind,(unsigned)addr,(unsigned)size)); 381 382 pa = addr; 383 *offsetp = 0; 384 size = round_page(size); 385 pmh->realsize = size; 386 if (kind & PCMCIA_WIDTH_MEM8) 387 ph->ph_width = 8; 388 else 389 ph->ph_width = 16; 390 switch (kind & ~PCMCIA_WIDTH_MEM_MASK) { 391 case PCMCIA_MEM_ATTR: 392 eppcic_set_pcreg(ph, ph->ph_space[ATTRIBUTE].reg); 393 pa += ph->ph_space[ATTRIBUTE].base; 394 break; 395 case PCMCIA_MEM_COMMON: 396 eppcic_set_pcreg(ph, ph->ph_space[COMMON].reg); 397 pa += ph->ph_space[COMMON].base; 398 break; 399 default: 400 return -1; 401 } 402 403 DPRINTFN(1, ("eppcic_mem_map: pa=%#x, *offsetp=%#x, size=%#x\n",(unsigned)pa,(unsigned)addr,(unsigned)size)); 404 405 if (!(err = bus_space_map(sc->sc_iot, pa, size, 0, &pmh->memh))) 406 *windowp = (int)pmh->memh; 407 return err; 408 } 409 410 static void 411 eppcic_mem_unmap(pcmcia_chipset_handle_t pch, int window) 412 { 413 struct eppcic_handle *ph = (struct eppcic_handle *)pch; 414 struct eppcic_softc *sc = ph->ph_sc; 415 416 DPRINTFN(1, ("eppcic_mem_unmap: window=%#x\n",window)); 417 418 bus_space_unmap(sc->sc_iot, (bus_addr_t)window, 0x400); 419 } 420 421 static int 422 eppcic_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, bus_size_t size, 423 bus_size_t align, struct pcmcia_io_handle *pih) 424 { 425 struct eppcic_handle *ph = (struct eppcic_handle *)pch; 426 struct eppcic_softc *sc = ph->ph_sc; 427 bus_addr_t pa; 428 429 DPRINTFN(1, ("eppcic_io_alloc: start=%#x, size=%#x, align=%#x\n",(unsigned)start,(unsigned)size,(unsigned)align)); 430 431 pih->iot = sc->sc_iot; 432 pih->addr = start; 433 pih->size = size; 434 pa = pih->addr + ph->ph_space[IO].base; 435 return bus_space_map(sc->sc_iot, pa, size, 0, &pih->ioh); 436 } 437 438 static void 439 eppcic_io_free(pcmcia_chipset_handle_t pch, struct pcmcia_io_handle *pih) 440 { 441 struct eppcic_handle *ph = (struct eppcic_handle *)pch; 442 struct eppcic_softc *sc = ph->ph_sc; 443 444 DPRINTFN(1, ("eppcic_io_free\n")); 445 446 bus_space_unmap(sc->sc_iot, pih->ioh, pih->size); 447 } 448 449 static int 450 eppcic_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 451 bus_size_t size, struct pcmcia_io_handle *pih, int *windowp) 452 { 453 struct eppcic_handle *ph = (struct eppcic_handle *)pch; 454 455 DPRINTFN(1, ("eppcic_io_map: offset=%#x, size=%#x, width=%d",(unsigned)offset,(unsigned)size,width)); 456 457 switch (width) { 458 case PCMCIA_WIDTH_IO8: 459 DPRINTFN(1, ("(8bit)\n")); 460 ph->ph_width = 8; 461 break; 462 case PCMCIA_WIDTH_IO16: 463 case PCMCIA_WIDTH_AUTO: /* I don't understand how I check it */ 464 DPRINTFN(1, ("(16bit)\n")); 465 ph->ph_width = 16; 466 break; 467 default: 468 DPRINTFN(1, ("(unknown)\n")); 469 return -1; 470 } 471 eppcic_set_pcreg(ph, ph->ph_space[IO].reg); 472 *windowp = 0; /* unused */ 473 return 0; 474 } 475 476 static void 477 eppcic_io_unmap(pcmcia_chipset_handle_t pch, int window) 478 { 479 DPRINTFN(1, ("eppcic_io_unmap: window=%#x\n",window)); 480 } 481 482 static void * 483 eppcic_intr_establish(pcmcia_chipset_handle_t pch, struct pcmcia_function *pf, 484 int ipl, int (*ih_func)(void *), void *ih_arg) 485 { 486 struct eppcic_handle *ph = (struct eppcic_handle *)pch; 487 struct eppcic_softc *sc = ph->ph_sc; 488 489 DPRINTFN(1, ("eppcic_intr_establish\n")); 490 491 if (ph->ph_ih_func) 492 return 0; 493 494 ph->ph_ih_func = ih_func; 495 ph->ph_ih_arg = ih_arg; 496 return epgpio_intr_establish(sc->sc_gpio, ph->ph_port, ph->ph_ireq, 497 LEVEL_SENSE | LOW_LEVEL, 498 ipl, eppcic_intr_socket, ph); 499 } 500 501 static void 502 eppcic_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 503 { 504 struct eppcic_handle *ph = (struct eppcic_handle *)pch; 505 struct eppcic_softc *sc = ph->ph_sc; 506 507 DPRINTFN(1, ("eppcic_intr_disestablish\n")); 508 509 ph->ph_ih_func = NULL; 510 ph->ph_ih_arg = NULL; 511 epgpio_intr_disestablish(sc->sc_gpio, ph->ph_port, ph->ph_ireq); 512 } 513 514 static int 515 eppcic_intr_socket(void *arg) 516 { 517 struct eppcic_handle *ph = arg; 518 int err = 0; 519 520 if (ph->ph_ih_func) { 521 #if NEPLED > 0 522 epled_red_on(); 523 #endif 524 err = (*ph->ph_ih_func)(ph->ph_ih_arg); 525 #if NEPLED > 0 526 epled_red_off(); 527 #endif 528 } 529 return err; 530 } 531 532 533 static void 534 eppcic_socket_enable(pcmcia_chipset_handle_t pch) 535 { 536 struct eppcic_handle *ph = (struct eppcic_handle *)pch; 537 struct eppcic_softc *sc = ph->ph_sc; 538 eppcic_chipset_tag_t pcic = sc->sc_pcic; 539 int wait; 540 541 DPRINTFN(1, ("eppcic_socket_enable\n")); 542 543 wait = (pcic->power_ctl)(sc, ph->ph_socket, POWER_ON); 544 delay(wait); 545 #if NEPLED > 0 546 if (!sc->sc_enable++) 547 epled_green_on(); 548 #endif 549 ph->ph_vcc = eppcic_get_voltage(ph); 550 } 551 552 static void 553 eppcic_socket_disable(pcmcia_chipset_handle_t pch) 554 { 555 struct eppcic_handle *ph = (struct eppcic_handle *)pch; 556 struct eppcic_softc *sc = ph->ph_sc; 557 eppcic_chipset_tag_t pcic = sc->sc_pcic; 558 int wait; 559 560 DPRINTFN(1, ("eppcic_socket_disable\n")); 561 562 wait = (pcic->power_ctl)(sc, ph->ph_socket, POWER_OFF); 563 delay(wait); 564 #if NEPLED > 0 565 if (!--sc->sc_enable) 566 epled_green_off(); 567 #endif 568 } 569 570 static void 571 eppcic_socket_settype(pcmcia_chipset_handle_t pch, int type) 572 { 573 DPRINTFN(1, ("eppcic_socket_settype: type=%d",type)); 574 575 switch (type) { 576 case PCMCIA_IFTYPE_MEMORY: 577 DPRINTFN(1, ("(Memory)\n")); 578 break; 579 case PCMCIA_IFTYPE_IO: 580 DPRINTFN(1, ("(I/O)\n")); 581 break; 582 default: 583 DPRINTFN(1, ("(unknown)\n")); 584 return; 585 } 586 } 587 588 static int 589 eppcic_get_voltage(struct eppcic_handle *ph) 590 { 591 struct eppcic_softc *sc = ph->ph_sc; 592 eppcic_chipset_tag_t pcic = sc->sc_pcic; 593 int cap, vcc = 0; 594 595 cap = (pcic->power_capability)(sc, ph->ph_socket); 596 if (epgpio_read(sc->sc_gpio, ph->ph_port, ph->ph_vs[0])) { 597 if (cap | VCC_5V) 598 vcc = 5; 599 else 600 printf("%s: unsupported Vcc 5 Volts", 601 sc->sc_dev.dv_xname); 602 } else { 603 if (cap | VCC_3V) 604 vcc = 3; 605 else 606 printf("%s: unsupported Vcc 3.3 Volts", 607 sc->sc_dev.dv_xname); 608 } 609 DPRINTFN(1, ("eppcic_get_voltage: vs1=%d, vs2=%d (%dV)\n",epgpio_read_bit(sc->sc_gpio, ph->ph_port, ph->ph_vs[0]),epgpio_read_bit(sc->sc_gpio, ph->ph_port, ph->ph_vs[1]),vcc)); 610 return vcc; 611 } 612 613 #define EXTRA_DELAY 40 614 615 static void 616 eppcic_set_pcreg(struct eppcic_handle *ph, int kind) 617 { 618 struct eppcic_softc *sc = ph->ph_sc; 619 int atiming, htiming, ptiming; 620 int period = 1000000000 / sc->sc_hclk; 621 int width; 622 623 switch (ph->ph_width) { 624 case 8: 625 width = 0; 626 break; 627 case 16: 628 width = EP93XX_PCMCIA_WIDTH_16; 629 break; 630 default: 631 return; 632 } 633 switch (kind) { 634 case IO: 635 atiming = 165; htiming = 20; ptiming = 70; 636 break; 637 case COMMON: 638 #if linux_timing!=hamajima20050816 639 switch (ph->ph_vcc) { 640 case 3: 641 atiming = 465; htiming = 35; ptiming = 100; 642 break; 643 case 5: 644 atiming = 200; htiming = 20; ptiming = 30; 645 break; 646 default: 647 return; 648 } 649 break; 650 #endif 651 case ATTRIBUTE: 652 switch (ph->ph_vcc) { 653 case 3: 654 #if linux_timing!=hamajima20050816 655 atiming = 465; htiming = 35; ptiming = 100; 656 #else 657 atiming = 600; htiming = 35; ptiming = 100; 658 #endif 659 break; 660 case 5: 661 #if linux_timing!=hamajima20050816 662 atiming = 250; htiming = 20; ptiming = 30; 663 #else 664 atiming = 300; htiming = 20; ptiming = 30; 665 #endif 666 break; 667 default: 668 return; 669 } 670 break; 671 default: 672 return; 673 } 674 675 #if linux_timing!=hamajima20050816 676 period = 1000000000 / 50000000; 677 width = EP93XX_PCMCIA_WIDTH_16; 678 #endif 679 680 atiming = (atiming + EXTRA_DELAY) / period; 681 if (atiming>0xff) 682 atiming = 0xff; 683 htiming = ((htiming + EXTRA_DELAY) / period) + 1; 684 if (htiming>0xf) 685 htiming = 0xf; 686 ptiming = (ptiming + EXTRA_DELAY) / period; 687 if (ptiming>0xff) 688 ptiming = 0xff; 689 690 DPRINTFN(1, ("eppcic_set_pcreg: width=%d, access=%d, hold=%d, pre-charge=%d\n",ph->ph_width,atiming,htiming,ptiming)); 691 692 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ph->ph_space[kind].reg, 693 width 694 | (atiming<<EP93XX_PCMCIA_ACCESS_SHIFT) 695 | (htiming<<EP93XX_PCMCIA_HOLD_SHIFT) 696 | (ptiming<<EP93XX_PCMCIA_PRECHARGE_SHIFT)); 697 } 698
Indexes created Tue Sep 30 11:09:46 GMT 2025