a9tmr_fdt.c revision 1.8 
1/* $NetBSD: a9tmr_fdt.c,v 1.8 2022/11/01 11:05:18 jmcneill Exp $ */
2
3/*-
4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30__KERNEL_RCSID(0, "$NetBSD: a9tmr_fdt.c,v 1.8 2022/11/01 11:05:18 jmcneill Exp $");
31
32#include <sys/param.h>
33#include <sys/bus.h>
34#include <sys/device.h>
35#include <sys/intr.h>
36#include <sys/systm.h>
37#include <sys/kernel.h>
38#include <sys/kmem.h>
39
40#include <arm/cortex/a9tmr_intr.h>
41#include <arm/cortex/mpcore_var.h>
42#include <arm/cortex/a9tmr_var.h>
43
44#include <arm/armreg.h>
45
46#include <dev/fdt/fdtvar.h>
47#include <arm/fdt/arm_fdtvar.h>
48
49static int	a9tmr_fdt_match(device_t, cfdata_t, void *);
50static void	a9tmr_fdt_attach(device_t, device_t, void *);
51
52static void	a9tmr_fdt_cpu_hatch(void *, struct cpu_info *);
53static void	a9tmr_fdt_speed_changed(device_t);
54
55struct a9tmr_fdt_softc {
56	device_t	sc_dev;
57	struct clk	*sc_clk;
58};
59
60CFATTACH_DECL_NEW(a9tmr_fdt, sizeof(struct a9tmr_fdt_softc),
61    a9tmr_fdt_match, a9tmr_fdt_attach, NULL, NULL);
62
63static const struct device_compatible_entry compat_data[] = {
64	{ .compat = "arm,cortex-a5-global-timer" },
65	{ .compat = "arm,cortex-a9-global-timer" },
66	DEVICE_COMPAT_EOL
67};
68
69static int
70a9tmr_fdt_match(device_t parent, cfdata_t cf, void *aux)
71{
72	struct fdt_attach_args * const faa = aux;
73
74	return of_compatible_match(faa->faa_phandle, compat_data);
75}
76
77static void
78a9tmr_fdt_attach(device_t parent, device_t self, void *aux)
79{
80	struct a9tmr_fdt_softc * const sc = device_private(self);
81	struct fdt_attach_args * const faa = aux;
82	const int phandle = faa->faa_phandle;
83	bus_space_handle_t bsh;
84	uint32_t mpidr;
85	bool is_hardclock;
86
87	sc->sc_dev = self;
88	sc->sc_clk = fdtbus_clock_get_index(phandle, 0);
89	if (sc->sc_clk == NULL) {
90		aprint_error(": couldn't get clock\n");
91		return;
92	}
93	if (clk_enable(sc->sc_clk) != 0) {
94		aprint_error(": couldn't enable clock\n");
95		return;
96	}
97
98	uint32_t rate = clk_get_rate(sc->sc_clk);
99	prop_dictionary_t dict = device_properties(self);
100	prop_dictionary_set_uint32(dict, "frequency", rate);
101
102	char intrstr[128];
103	if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
104		aprint_error(": failed to decode interrupt\n");
105		return;
106	}
107
108	aprint_naive("\n");
109	aprint_normal("\n");
110
111	mpidr = armreg_mpidr_read();
112	is_hardclock = (mpidr & MPIDR_U) != 0;	/* Global timer for UP */
113
114	if (is_hardclock) {
115		void *ih = fdtbus_intr_establish_xname(phandle, 0, IPL_CLOCK,
116		    FDT_INTR_MPSAFE, a9tmr_intr, NULL, device_xname(self));
117		if (ih == NULL) {
118			aprint_error_dev(self, "couldn't install interrupt handler\n");
119			return;
120		}
121		aprint_normal_dev(self, "interrupting on %s\n", intrstr);
122	}
123
124	bus_addr_t addr;
125	bus_size_t size;
126	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
127		aprint_error(": couldn't get distributor address\n");
128		return;
129	}
130	if (bus_space_map(faa->faa_bst, addr, size, 0, &bsh)) {
131		aprint_error(": couldn't map registers\n");
132		return;
133	}
134
135	struct mpcore_attach_args mpcaa = {
136		.mpcaa_name = "arma9tmr",
137		.mpcaa_memt = faa->faa_bst,
138		.mpcaa_memh = bsh,
139		.mpcaa_irq = -1,
140	};
141
142	config_found(self, &mpcaa, NULL, CFARGS_NONE);
143
144	if (is_hardclock) {
145		arm_fdt_cpu_hatch_register(self, a9tmr_fdt_cpu_hatch);
146		arm_fdt_timer_register(a9tmr_cpu_initclocks);
147	}
148
149	pmf_event_register(self, PMFE_SPEED_CHANGED, a9tmr_fdt_speed_changed, true);
150}
151
152static void
153a9tmr_fdt_cpu_hatch(void *priv, struct cpu_info *ci)
154{
155	a9tmr_init_cpu_clock(ci);
156}
157
158static void
159a9tmr_fdt_speed_changed(device_t dev)
160{
161	struct a9tmr_fdt_softc * const sc = device_private(dev);
162	prop_dictionary_t dict = device_properties(dev);
163	uint32_t rate;
164
165	rate = clk_get_rate(sc->sc_clk);
166	prop_dictionary_set_uint32(dict, "frequency", rate);
167
168	a9tmr_update_freq(rate);
169}
170