cpu_fdt.c revision 1.21 1 /* $NetBSD: cpu_fdt.c,v 1.21 2019/01/19 20:56:03 jmcneill Exp $ */
2
3 /*-
4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include "opt_multiprocessor.h"
30 #include "psci_fdt.h"
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: cpu_fdt.c,v 1.21 2019/01/19 20:56:03 jmcneill Exp $");
34
35 #include <sys/param.h>
36 #include <sys/atomic.h>
37 #include <sys/bus.h>
38 #include <sys/device.h>
39 #include <sys/lwp.h>
40 #include <sys/systm.h>
41 #include <sys/kernel.h>
42
43 #include <dev/fdt/fdtvar.h>
44
45 #include <arm/armreg.h>
46 #include <arm/cpu.h>
47 #include <arm/cpufunc.h>
48 #include <arm/locore.h>
49
50 #include <arm/arm/psci.h>
51 #include <arm/fdt/arm_fdtvar.h>
52 #include <arm/fdt/psci_fdtvar.h>
53
54 #include <uvm/uvm_extern.h>
55
56 static int cpu_fdt_match(device_t, cfdata_t, void *);
57 static void cpu_fdt_attach(device_t, device_t, void *);
58
59 enum cpu_fdt_type {
60 ARM_CPU_UP = 1,
61 ARM_CPU_ARMV7,
62 ARM_CPU_ARMV8,
63 };
64
65 struct cpu_fdt_softc {
66 device_t sc_dev;
67 int sc_phandle;
68 };
69
70 static const struct of_compat_data compat_data[] = {
71 { "arm,arm1176jzf-s", ARM_CPU_UP },
72
73 { "arm,arm-v7", ARM_CPU_ARMV7 },
74 { "arm,cortex-a5", ARM_CPU_ARMV7 },
75 { "arm,cortex-a7", ARM_CPU_ARMV7 },
76 { "arm,cortex-a8", ARM_CPU_ARMV7 },
77 { "arm,cortex-a9", ARM_CPU_ARMV7 },
78 { "arm,cortex-a12", ARM_CPU_ARMV7 },
79 { "arm,cortex-a15", ARM_CPU_ARMV7 },
80 { "arm,cortex-a17", ARM_CPU_ARMV7 },
81
82 { "arm,armv8", ARM_CPU_ARMV8 },
83 { "arm,cortex-a53", ARM_CPU_ARMV8 },
84 { "arm,cortex-a57", ARM_CPU_ARMV8 },
85 { "arm,cortex-a72", ARM_CPU_ARMV8 },
86 { "arm,cortex-a73", ARM_CPU_ARMV8 },
87
88 { NULL }
89 };
90
91 CFATTACH_DECL_NEW(cpu_fdt, sizeof(struct cpu_fdt_softc),
92 cpu_fdt_match, cpu_fdt_attach, NULL, NULL);
93
94 static int
95 cpu_fdt_match(device_t parent, cfdata_t cf, void *aux)
96 {
97 struct fdt_attach_args * const faa = aux;
98 const int phandle = faa->faa_phandle;
99 enum cpu_fdt_type type;
100 int is_compatible;
101 bus_addr_t mpidr;
102
103 is_compatible = of_match_compat_data(phandle, compat_data);
104 if (!is_compatible)
105 return 0;
106
107 type = of_search_compatible(phandle, compat_data)->data;
108 switch (type) {
109 case ARM_CPU_ARMV7:
110 case ARM_CPU_ARMV8:
111 if (fdtbus_get_reg(phandle, 0, &mpidr, NULL) != 0)
112 return 0;
113 default:
114 break;
115 }
116
117 return is_compatible;
118 }
119
120 static void
121 cpu_fdt_attach(device_t parent, device_t self, void *aux)
122 {
123 struct cpu_fdt_softc * const sc = device_private(self);
124 struct fdt_attach_args * const faa = aux;
125 const int phandle = faa->faa_phandle;
126 enum cpu_fdt_type type;
127 bus_addr_t mpidr;
128 cpuid_t cpuid;
129
130 sc->sc_dev = self;
131 sc->sc_phandle = phandle;
132
133 type = of_search_compatible(phandle, compat_data)->data;
134
135 switch (type) {
136 case ARM_CPU_ARMV7:
137 case ARM_CPU_ARMV8:
138 if (fdtbus_get_reg(phandle, 0, &mpidr, NULL) != 0) {
139 aprint_error(": missing 'reg' property\n");
140 return;
141 }
142 cpuid = mpidr;
143 break;
144 default:
145 cpuid = 0;
146 break;
147 }
148
149 /* Attach the CPU */
150 cpu_attach(self, cpuid);
151
152 /* Attach CPU frequency scaling provider */
153 config_found(self, faa, NULL);
154 }
155
156 #ifdef MULTIPROCESSOR
157 static register_t
158 cpu_fdt_mpstart_pa(void)
159 {
160 bool ok __diagused;
161 paddr_t pa;
162
163 ok = pmap_extract(pmap_kernel(), (vaddr_t)cpu_mpstart, &pa);
164 KASSERT(ok);
165
166 return pa;
167 }
168
169 static int
170 spintable_cpu_on(u_int cpuindex, paddr_t entry_point_address, paddr_t cpu_release_addr)
171 {
172 /*
173 * we need devmap for cpu-release-addr in advance.
174 * __HAVE_MM_MD_DIRECT_MAPPED_PHYS nor pmap didn't work at this point.
175 */
176 if (pmap_devmap_find_pa(cpu_release_addr, sizeof(paddr_t)) == NULL) {
177 aprint_error("%s: devmap for cpu-release-addr"
178 " 0x%08"PRIxPADDR" required\n", __func__, cpu_release_addr);
179 return -1;
180 } else {
181 extern struct bus_space arm_generic_bs_tag;
182 bus_space_handle_t ioh;
183
184 bus_space_map(&arm_generic_bs_tag, cpu_release_addr,
185 sizeof(paddr_t), 0, &ioh);
186 bus_space_write_4(&arm_generic_bs_tag, ioh, 0,
187 entry_point_address);
188 bus_space_unmap(&arm_generic_bs_tag, ioh, sizeof(paddr_t));
189 }
190
191 return 0;
192 }
193 #endif /* MULTIPROCESSOR */
194
195 #ifdef MULTIPROCESSOR
196 static bool
197 arm_fdt_cpu_okay(const int child)
198 {
199 const char *s;
200
201 s = fdtbus_get_string(child, "device_type");
202 if (!s || strcmp(s, "cpu") != 0)
203 return false;
204
205 s = fdtbus_get_string(child, "status");
206 if (s) {
207 if (strcmp(s, "okay") == 0)
208 return false;
209 if (strcmp(s, "disabled") == 0)
210 return of_hasprop(child, "enable-method");
211 return false;
212 } else {
213 return true;
214 }
215 }
216 #endif /* MULTIPROCESSOR */
217
218 void
219 arm_fdt_cpu_bootstrap(void)
220 {
221 #ifdef MULTIPROCESSOR
222 uint64_t mpidr, bp_mpidr;
223 u_int cpuindex;
224 int child;
225
226 const int cpus = OF_finddevice("/cpus");
227 if (cpus == -1) {
228 aprint_error("%s: no /cpus node found\n", __func__);
229 arm_cpu_max = 1;
230 return;
231 }
232
233 /* Count CPUs */
234 arm_cpu_max = 0;
235
236 /* MPIDR affinity levels of boot processor. */
237 bp_mpidr = cpu_mpidr_aff_read();
238
239 /* Boot APs */
240 cpuindex = 1;
241 for (child = OF_child(cpus); child; child = OF_peer(child)) {
242 if (!arm_fdt_cpu_okay(child))
243 continue;
244
245 arm_cpu_max++;
246 if (fdtbus_get_reg64(child, 0, &mpidr, NULL) != 0)
247 continue;
248 if (mpidr == bp_mpidr)
249 continue; /* BP already started */
250
251 KASSERT(cpuindex < MAXCPUS);
252 cpu_mpidr[cpuindex] = mpidr;
253 cpu_dcache_wb_range((vaddr_t)&cpu_mpidr[cpuindex],
254 sizeof(cpu_mpidr[cpuindex]));
255
256 cpuindex++;
257 }
258 #endif
259 }
260
261 #ifdef MULTIPROCESSOR
262 static int
263 arm_fdt_cpu_enable(int phandle, const char *method)
264 {
265 __link_set_decl(arm_cpu_methods, struct arm_cpu_method);
266 struct arm_cpu_method * const *acm;
267 __link_set_foreach(acm, arm_cpu_methods) {
268 if (strcmp(method, (*acm)->acm_compat) == 0)
269 return (*acm)->acm_enable(phandle);
270 }
271 return ENOSYS;
272 }
273 #endif
274
275 void
276 arm_fdt_cpu_mpstart(void)
277 {
278 #ifdef MULTIPROCESSOR
279 uint64_t mpidr, bp_mpidr;
280 u_int cpuindex, i;
281 int child, error;
282 const char *method;
283
284 const int cpus = OF_finddevice("/cpus");
285 if (cpus == -1) {
286 aprint_error("%s: no /cpus node found\n", __func__);
287 return;
288 }
289
290 /* MPIDR affinity levels of boot processor. */
291 bp_mpidr = cpu_mpidr_aff_read();
292
293 /* Boot APs */
294 cpuindex = 1;
295 for (child = OF_child(cpus); child; child = OF_peer(child)) {
296 if (!arm_fdt_cpu_okay(child))
297 continue;
298
299 if (fdtbus_get_reg64(child, 0, &mpidr, NULL) != 0)
300 continue;
301
302 if (mpidr == bp_mpidr)
303 continue; /* BP already started */
304
305 method = fdtbus_get_string(child, "enable-method");
306 if (method == NULL)
307 method = fdtbus_get_string(cpus, "enable-method");
308 if (method == NULL)
309 continue;
310
311 error = arm_fdt_cpu_enable(child, method);
312 if (error != 0) {
313 aprint_error("%s: %s: unsupported enable-method\n", __func__, method);
314 continue;
315 }
316
317 /* Wake up AP in case firmware has placed it in WFE state */
318 __asm __volatile("sev" ::: "memory");
319
320 /* Wait for AP to start */
321 for (i = 0x10000000; i > 0; i--) {
322 membar_consumer();
323 if (arm_cpu_hatched & __BIT(cpuindex))
324 break;
325 }
326 if (i == 0)
327 aprint_error("cpu%d: WARNING: AP failed to start\n", cpuindex);
328
329 cpuindex++;
330 }
331 #endif /* MULTIPROCESSOR */
332 }
333
334 static int
335 cpu_enable_nullop(int phandle)
336 {
337 return ENXIO;
338 }
339 ARM_CPU_METHOD(default, "", cpu_enable_nullop);
340
341 #if defined(MULTIPROCESSOR) && NPSCI_FDT > 0
342 static int
343 cpu_enable_psci(int phandle)
344 {
345 static bool psci_probed, psci_p;
346 uint64_t mpidr;
347 int ret;
348
349 if (!psci_probed) {
350 psci_probed = true;
351 psci_p = psci_fdt_preinit() == 0;
352 }
353 if (!psci_p)
354 return ENXIO;
355
356 fdtbus_get_reg64(phandle, 0, &mpidr, NULL);
357
358 ret = psci_cpu_on(mpidr, cpu_fdt_mpstart_pa(), 0);
359 if (ret != PSCI_SUCCESS)
360 return EIO;
361
362 return 0;
363 }
364 ARM_CPU_METHOD(psci, "psci", cpu_enable_psci);
365 #endif
366
367 #if defined(MULTIPROCESSOR)
368 static int
369 cpu_enable_spin_table(int phandle)
370 {
371 uint64_t mpidr, addr;
372 int ret;
373
374 fdtbus_get_reg64(phandle, 0, &mpidr, NULL);
375
376 if (of_getprop_uint64(phandle, "cpu-release-addr", &addr) != 0)
377 return ENXIO;
378
379 ret = spintable_cpu_on(mpidr, cpu_fdt_mpstart_pa(), (paddr_t)addr);
380 if (ret != 0)
381 return EIO;
382
383 return 0;
384 }
385 ARM_CPU_METHOD(spin_table, "spin-table", cpu_enable_spin_table);
386 #endif
387