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cpu_fdt.c revision 1.30.2.2 
      1 /* $NetBSD: cpu_fdt.c,v 1.30.2.2 2020/01/25 22:38:38 ad Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #include "opt_multiprocessor.h"
     30 #include "psci_fdt.h"
     31 
     32 #include <sys/cdefs.h>
     33 __KERNEL_RCSID(0, "$NetBSD: cpu_fdt.c,v 1.30.2.2 2020/01/25 22:38:38 ad Exp $");
     34 
     35 #include <sys/param.h>
     36 #include <sys/atomic.h>
     37 #include <sys/bus.h>
     38 #include <sys/device.h>
     39 #include <sys/lwp.h>
     40 #include <sys/systm.h>
     41 #include <sys/kernel.h>
     42 
     43 #include <dev/fdt/fdtvar.h>
     44 
     45 #include <arm/armreg.h>
     46 #include <arm/cpu.h>
     47 #include <arm/cpufunc.h>
     48 #include <arm/locore.h>
     49 
     50 #include <arm/arm/psci.h>
     51 #include <arm/fdt/arm_fdtvar.h>
     52 #include <arm/fdt/psci_fdtvar.h>
     53 
     54 #include <uvm/uvm_extern.h>
     55 
     56 static int	cpu_fdt_match(device_t, cfdata_t, void *);
     57 static void	cpu_fdt_attach(device_t, device_t, void *);
     58 
     59 enum cpu_fdt_type {
     60 	ARM_CPU_UP = 1,
     61 	ARM_CPU_ARMV7,
     62 	ARM_CPU_ARMV8,
     63 };
     64 
     65 struct cpu_fdt_softc {
     66 	device_t		sc_dev;
     67 	int			sc_phandle;
     68 };
     69 
     70 static const struct of_compat_data compat_data[] = {
     71 	{ "arm,arm1176jzf-s",		ARM_CPU_UP },
     72 
     73 	{ "arm,arm-v7",			ARM_CPU_ARMV7 },
     74 	{ "arm,cortex-a5",		ARM_CPU_ARMV7 },
     75 	{ "arm,cortex-a7",		ARM_CPU_ARMV7 },
     76 	{ "arm,cortex-a8",		ARM_CPU_ARMV7 },
     77 	{ "arm,cortex-a9",		ARM_CPU_ARMV7 },
     78 	{ "arm,cortex-a12",		ARM_CPU_ARMV7 },
     79 	{ "arm,cortex-a15",		ARM_CPU_ARMV7 },
     80 	{ "arm,cortex-a17",		ARM_CPU_ARMV7 },
     81 
     82 	{ "arm,armv8",			ARM_CPU_ARMV8 },
     83 	{ "arm,cortex-a53",		ARM_CPU_ARMV8 },
     84 	{ "arm,cortex-a57",		ARM_CPU_ARMV8 },
     85 	{ "arm,cortex-a72",		ARM_CPU_ARMV8 },
     86 	{ "arm,cortex-a73",		ARM_CPU_ARMV8 },
     87 
     88 	{ NULL }
     89 };
     90 
     91 CFATTACH_DECL_NEW(cpu_fdt, sizeof(struct cpu_fdt_softc),
     92 	cpu_fdt_match, cpu_fdt_attach, NULL, NULL);
     93 
     94 static int
     95 cpu_fdt_match(device_t parent, cfdata_t cf, void *aux)
     96 {
     97 	struct fdt_attach_args * const faa = aux;
     98 	const int phandle = faa->faa_phandle;
     99 	enum cpu_fdt_type type;
    100 	int is_compatible;
    101 	bus_addr_t mpidr;
    102 
    103 	is_compatible = of_match_compat_data(phandle, compat_data);
    104 	if (!is_compatible)
    105 		return 0;
    106 
    107 	type = of_search_compatible(phandle, compat_data)->data;
    108 	switch (type) {
    109 	case ARM_CPU_ARMV7:
    110 	case ARM_CPU_ARMV8:
    111 		if (fdtbus_get_reg(phandle, 0, &mpidr, NULL) != 0)
    112 			return 0;
    113 	default:
    114 		break;
    115 	}
    116 
    117 	return is_compatible;
    118 }
    119 
    120 static void
    121 cpu_fdt_attach(device_t parent, device_t self, void *aux)
    122 {
    123 	struct cpu_fdt_softc * const sc = device_private(self);
    124 	struct fdt_attach_args * const faa = aux;
    125 	const int phandle = faa->faa_phandle;
    126 	enum cpu_fdt_type type;
    127 	bus_addr_t mpidr;
    128 	cpuid_t cpuid;
    129 	const uint32_t *cap_ptr;
    130 	int len;
    131 
    132 	sc->sc_dev = self;
    133 	sc->sc_phandle = phandle;
    134 
    135  	cap_ptr = fdtbus_get_prop(phandle, "capacity-dmips-mhz", &len);
    136 	if (cap_ptr && len == 4) {
    137 		prop_dictionary_t dict = device_properties(self);
    138 		uint32_t capacity_dmips_mhz = be32toh(*cap_ptr);
    139 
    140 		prop_dictionary_set_uint32(dict, "capacity_dmips_mhz",
    141 		    capacity_dmips_mhz);
    142 	}
    143 
    144 	type = of_search_compatible(phandle, compat_data)->data;
    145 
    146 	switch (type) {
    147 	case ARM_CPU_ARMV7:
    148 	case ARM_CPU_ARMV8:
    149 		if (fdtbus_get_reg(phandle, 0, &mpidr, NULL) != 0) {
    150 			aprint_error(": missing 'reg' property\n");
    151 			return;
    152 		}
    153 		cpuid = mpidr;
    154 		break;
    155 	default:
    156 		cpuid = 0;
    157 		break;
    158 	}
    159 
    160 	/* Attach the CPU */
    161 	cpu_attach(self, cpuid);
    162 
    163 	/* Attach CPU frequency scaling provider */
    164 	config_found(self, faa, NULL);
    165 }
    166 
    167 #if defined(MULTIPROCESSOR) && (NPSCI_FDT > 0 || defined(__aarch64__))
    168 static register_t
    169 cpu_fdt_mpstart_pa(void)
    170 {
    171 	bool ok __diagused;
    172 	paddr_t pa;
    173 
    174 	ok = pmap_extract(pmap_kernel(), (vaddr_t)cpu_mpstart, &pa);
    175 	KASSERT(ok);
    176 
    177 	return pa;
    178 }
    179 #endif
    180 
    181 #ifdef MULTIPROCESSOR
    182 static bool
    183 arm_fdt_cpu_okay(const int child)
    184 {
    185 	const char *s;
    186 
    187 	s = fdtbus_get_string(child, "device_type");
    188 	if (!s || strcmp(s, "cpu") != 0)
    189 		return false;
    190 
    191 	s = fdtbus_get_string(child, "status");
    192 	if (s) {
    193 		if (strcmp(s, "okay") == 0)
    194 			return false;
    195 		if (strcmp(s, "disabled") == 0)
    196 			return of_hasprop(child, "enable-method");
    197 		return false;
    198 	} else {
    199 		return true;
    200 	}
    201 }
    202 #endif /* MULTIPROCESSOR */
    203 
    204 void
    205 arm_fdt_cpu_bootstrap(void)
    206 {
    207 #ifdef MULTIPROCESSOR
    208 	uint64_t mpidr, bp_mpidr;
    209 	u_int cpuindex;
    210 	int child;
    211 
    212 	const int cpus = OF_finddevice("/cpus");
    213 	if (cpus == -1) {
    214 		aprint_error("%s: no /cpus node found\n", __func__);
    215 		arm_cpu_max = 1;
    216 		return;
    217 	}
    218 
    219 	/* Count CPUs */
    220 	arm_cpu_max = 0;
    221 
    222 	/* MPIDR affinity levels of boot processor. */
    223 	bp_mpidr = cpu_mpidr_aff_read();
    224 
    225 	/* Boot APs */
    226 	cpuindex = 1;
    227 	for (child = OF_child(cpus); child; child = OF_peer(child)) {
    228 		if (!arm_fdt_cpu_okay(child))
    229 			continue;
    230 
    231 		arm_cpu_max++;
    232 		if (fdtbus_get_reg64(child, 0, &mpidr, NULL) != 0)
    233 			continue;
    234 		if (mpidr == bp_mpidr)
    235 			continue; 	/* BP already started */
    236 
    237 		KASSERT(cpuindex < MAXCPUS);
    238 		cpu_mpidr[cpuindex] = mpidr;
    239 		cpu_dcache_wb_range((vaddr_t)&cpu_mpidr[cpuindex],
    240 		    sizeof(cpu_mpidr[cpuindex]));
    241 
    242 		cpuindex++;
    243 	}
    244 #endif
    245 }
    246 
    247 #ifdef MULTIPROCESSOR
    248 static struct arm_cpu_method *
    249 arm_fdt_cpu_enable_method(int phandle)
    250 {
    251 	const char *method;
    252 
    253  	method = fdtbus_get_string(phandle, "enable-method");
    254 	if (method == NULL)
    255 		return NULL;
    256 
    257 	__link_set_decl(arm_cpu_methods, struct arm_cpu_method);
    258 	struct arm_cpu_method * const *acmp;
    259 	__link_set_foreach(acmp, arm_cpu_methods) {
    260 		if (strcmp(method, (*acmp)->acm_compat) == 0)
    261 			return *acmp;
    262 	}
    263 
    264 	return NULL;
    265 }
    266 
    267 static int
    268 arm_fdt_cpu_enable(int phandle, struct arm_cpu_method *acm)
    269 {
    270 	return acm->acm_enable(phandle);
    271 }
    272 #endif
    273 
    274 int
    275 arm_fdt_cpu_mpstart(void)
    276 {
    277 	int ret = 0;
    278 #ifdef MULTIPROCESSOR
    279 	uint64_t mpidr, bp_mpidr;
    280 	u_int cpuindex, i;
    281 	int child, error;
    282 	struct arm_cpu_method *acm;
    283 
    284 	const int cpus = OF_finddevice("/cpus");
    285 	if (cpus == -1) {
    286 		aprint_error("%s: no /cpus node found\n", __func__);
    287 		return 0;
    288 	}
    289 
    290 	/* MPIDR affinity levels of boot processor. */
    291 	bp_mpidr = cpu_mpidr_aff_read();
    292 
    293 	/* Boot APs */
    294 	cpuindex = 1;
    295 	for (child = OF_child(cpus); child; child = OF_peer(child)) {
    296 		if (!arm_fdt_cpu_okay(child))
    297 			continue;
    298 
    299 		if (fdtbus_get_reg64(child, 0, &mpidr, NULL) != 0)
    300 			continue;
    301 
    302 		if (mpidr == bp_mpidr)
    303 			continue; 	/* BP already started */
    304 
    305 		acm = arm_fdt_cpu_enable_method(child);
    306 		if (acm == NULL)
    307 			acm = arm_fdt_cpu_enable_method(cpus);
    308 		if (acm == NULL)
    309 			continue;
    310 
    311 		error = arm_fdt_cpu_enable(child, acm);
    312 		if (error != 0) {
    313 			aprint_error("%s: failed to enable CPU %#" PRIx64 "\n",
    314 			    __func__, mpidr);
    315 			continue;
    316 		}
    317 
    318 		/* Wake up AP in case firmware has placed it in WFE state */
    319 		__asm __volatile("sev" ::: "memory");
    320 
    321 		/* Wait for AP to start */
    322 		for (i = 0x10000000; i > 0; i--) {
    323 			if (cpu_hatched_p(cpuindex))
    324 				break;
    325 		}
    326 
    327 		if (i == 0) {
    328 			ret++;
    329 			aprint_error("cpu%d: WARNING: AP failed to start\n", cpuindex);
    330 		}
    331 
    332 		cpuindex++;
    333 	}
    334 #endif /* MULTIPROCESSOR */
    335 	return ret;
    336 }
    337 
    338 static int
    339 cpu_enable_nullop(int phandle)
    340 {
    341 	return ENXIO;
    342 }
    343 ARM_CPU_METHOD(default, "", cpu_enable_nullop);
    344 
    345 #if defined(MULTIPROCESSOR) && NPSCI_FDT > 0
    346 static int
    347 cpu_enable_psci(int phandle)
    348 {
    349 	static bool psci_probed, psci_p;
    350 	uint64_t mpidr;
    351 	int ret;
    352 
    353 	if (!psci_probed) {
    354 		psci_probed = true;
    355 		psci_p = psci_fdt_preinit() == 0;
    356 	}
    357 	if (!psci_p)
    358 		return ENXIO;
    359 
    360 	fdtbus_get_reg64(phandle, 0, &mpidr, NULL);
    361 
    362 #if !defined(AARCH64)
    363 	/*
    364 	 * not necessary on AARCH64. beside there it hangs the system
    365 	 * because cache ops are only functional after cpu_attach()
    366 	 * was called.
    367 	 */
    368 	cpu_dcache_wbinv_all();
    369 #endif
    370 	ret = psci_cpu_on(mpidr, cpu_fdt_mpstart_pa(), 0);
    371 	if (ret != PSCI_SUCCESS)
    372 		return EIO;
    373 
    374 	return 0;
    375 }
    376 ARM_CPU_METHOD(psci, "psci", cpu_enable_psci);
    377 #endif
    378 
    379 #if defined(MULTIPROCESSOR) && defined(__aarch64__)
    380 static int
    381 spintable_cpu_on(u_int cpuindex, paddr_t entry_point_address, paddr_t cpu_release_addr)
    382 {
    383 	/*
    384 	 * we need devmap for cpu-release-addr in advance.
    385 	 * __HAVE_MM_MD_DIRECT_MAPPED_PHYS nor pmap didn't work at this point.
    386 	 */
    387 	if (pmap_devmap_find_pa(cpu_release_addr, sizeof(paddr_t)) == NULL) {
    388 		aprint_error("%s: devmap for cpu-release-addr"
    389 		    " 0x%08"PRIxPADDR" required\n", __func__, cpu_release_addr);
    390 		return -1;
    391 	} else {
    392 		extern struct bus_space arm_generic_bs_tag;
    393 		bus_space_handle_t ioh;
    394 
    395 		bus_space_map(&arm_generic_bs_tag, cpu_release_addr,
    396 		    sizeof(paddr_t), 0, &ioh);
    397 		bus_space_write_4(&arm_generic_bs_tag, ioh, 0,
    398 		    entry_point_address);
    399 		bus_space_unmap(&arm_generic_bs_tag, ioh, sizeof(paddr_t));
    400 	}
    401 
    402 	return 0;
    403 }
    404 
    405 static int
    406 cpu_enable_spin_table(int phandle)
    407 {
    408 	uint64_t mpidr, addr;
    409 	int ret;
    410 
    411 	fdtbus_get_reg64(phandle, 0, &mpidr, NULL);
    412 
    413 	if (of_getprop_uint64(phandle, "cpu-release-addr", &addr) != 0)
    414 		return ENXIO;
    415 
    416 	ret = spintable_cpu_on(mpidr, cpu_fdt_mpstart_pa(), (paddr_t)addr);
    417 	if (ret != 0)
    418 		return EIO;
    419 
    420 	return 0;
    421 }
    422 ARM_CPU_METHOD(spin_table, "spin-table", cpu_enable_spin_table);
    423 #endif
    424