gic_fdt.c revision 1.12
1 /* $NetBSD: gic_fdt.c,v 1.12 2018/07/15 13:34:43 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: gic_fdt.c,v 1.12 2018/07/15 13:34:43 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/lwp.h> 39 #include <sys/kmem.h> 40 #include <sys/queue.h> 41 42 #include <arm/cortex/gic_intr.h> 43 #include <arm/cortex/mpcore_var.h> 44 45 #include <dev/fdt/fdtvar.h> 46 47 #define GIC_MAXIRQ 1020 48 49 static int gic_fdt_match(device_t, cfdata_t, void *); 50 static void gic_fdt_attach(device_t, device_t, void *); 51 52 static int gic_fdt_intr(void *); 53 54 static void * gic_fdt_establish(device_t, u_int *, int, int, 55 int (*)(void *), void *); 56 static void gic_fdt_disestablish(device_t, void *); 57 static bool gic_fdt_intrstr(device_t, u_int *, char *, size_t); 58 59 struct fdtbus_interrupt_controller_func gic_fdt_funcs = { 60 .establish = gic_fdt_establish, 61 .disestablish = gic_fdt_disestablish, 62 .intrstr = gic_fdt_intrstr 63 }; 64 65 struct gic_fdt_softc; 66 struct gic_fdt_irq; 67 68 struct gic_fdt_irqhandler { 69 struct gic_fdt_irq *ih_irq; 70 int (*ih_fn)(void *); 71 void *ih_arg; 72 bool ih_mpsafe; 73 TAILQ_ENTRY(gic_fdt_irqhandler) ih_next; 74 }; 75 76 struct gic_fdt_irq { 77 struct gic_fdt_softc *intr_sc; 78 void *intr_ih; 79 void *intr_arg; 80 int intr_refcnt; 81 int intr_ipl; 82 int intr_level; 83 int intr_mpsafe; 84 TAILQ_HEAD(, gic_fdt_irqhandler) intr_handlers; 85 int intr_irq; 86 }; 87 88 struct gic_fdt_softc { 89 device_t sc_dev; 90 int sc_phandle; 91 92 struct gic_fdt_irq *sc_irq[GIC_MAXIRQ]; 93 }; 94 95 CFATTACH_DECL_NEW(gic_fdt, sizeof(struct gic_fdt_softc), 96 gic_fdt_match, gic_fdt_attach, NULL, NULL); 97 98 static int 99 gic_fdt_match(device_t parent, cfdata_t cf, void *aux) 100 { 101 const char * const compatible[] = { 102 "arm,gic-400", 103 "arm,cortex-a15-gic", 104 "arm,cortex-a9-gic", 105 "arm,cortex-a7-gic", 106 NULL 107 }; 108 struct fdt_attach_args * const faa = aux; 109 110 return of_compatible(faa->faa_phandle, compatible) >= 0; 111 } 112 113 static void 114 gic_fdt_attach(device_t parent, device_t self, void *aux) 115 { 116 struct gic_fdt_softc * const sc = device_private(self); 117 struct fdt_attach_args * const faa = aux; 118 bus_addr_t addr_d, addr_c; 119 bus_size_t size_d, size_c; 120 bus_space_handle_t bsh; 121 int error; 122 123 sc->sc_dev = self; 124 sc->sc_phandle = faa->faa_phandle; 125 126 error = fdtbus_register_interrupt_controller(self, faa->faa_phandle, 127 &gic_fdt_funcs); 128 if (error) { 129 aprint_error(": couldn't register with fdtbus: %d\n", error); 130 return; 131 } 132 133 aprint_naive("\n"); 134 aprint_normal(": GIC\n"); 135 136 if (fdtbus_get_reg(sc->sc_phandle, 0, &addr_d, &size_d) != 0) { 137 aprint_error(": couldn't get distributor address\n"); 138 return; 139 } 140 if (fdtbus_get_reg(sc->sc_phandle, 1, &addr_c, &size_c) != 0) { 141 aprint_error(": couldn't get cpu interface address\n"); 142 return; 143 } 144 145 const bus_addr_t addr = min(addr_d, addr_c); 146 const bus_size_t end = max(addr_d + size_d, addr_c + size_c); 147 const bus_size_t size = end - addr; 148 149 error = bus_space_map(faa->faa_bst, addr, size, 0, &bsh); 150 if (error) { 151 aprint_error(": couldn't map registers: %d\n", error); 152 return; 153 } 154 155 struct mpcore_attach_args mpcaa = { 156 .mpcaa_name = "armgic", 157 .mpcaa_memt = faa->faa_bst, 158 .mpcaa_memh = bsh, 159 .mpcaa_off1 = addr_d - addr, 160 .mpcaa_off2 = addr_c - addr, 161 }; 162 163 config_found(self, &mpcaa, NULL); 164 165 arm_fdt_irq_set_handler(armgic_irq_handler); 166 } 167 168 static void * 169 gic_fdt_establish(device_t dev, u_int *specifier, int ipl, int flags, 170 int (*func)(void *), void *arg) 171 { 172 struct gic_fdt_softc * const sc = device_private(dev); 173 struct gic_fdt_irq *firq; 174 struct gic_fdt_irqhandler *firqh; 175 176 /* 1st cell is the interrupt type; 0 is SPI, 1 is PPI */ 177 /* 2nd cell is the interrupt number */ 178 /* 3rd cell is flags */ 179 180 const u_int type = be32toh(specifier[0]); 181 const u_int intr = be32toh(specifier[1]); 182 const u_int irq = type == 0 ? IRQ_SPI(intr) : IRQ_PPI(intr); 183 const u_int trig = be32toh(specifier[2]) & 0xf; 184 const u_int level = (trig & 0x3) ? IST_EDGE : IST_LEVEL; 185 186 const u_int mpsafe = (flags & FDT_INTR_MPSAFE) ? IST_MPSAFE : 0; 187 188 firq = sc->sc_irq[irq]; 189 if (firq == NULL) { 190 firq = kmem_alloc(sizeof(*firq), KM_SLEEP); 191 firq->intr_sc = sc; 192 firq->intr_refcnt = 0; 193 firq->intr_arg = arg; 194 firq->intr_ipl = ipl; 195 firq->intr_level = level; 196 firq->intr_mpsafe = mpsafe; 197 TAILQ_INIT(&firq->intr_handlers); 198 firq->intr_irq = irq; 199 if (arg == NULL) { 200 firq->intr_ih = intr_establish(irq, ipl, level | mpsafe, 201 func, NULL); 202 } else { 203 firq->intr_ih = intr_establish(irq, ipl, level | mpsafe, 204 gic_fdt_intr, firq); 205 } 206 if (firq->intr_ih == NULL) { 207 kmem_free(firq, sizeof(*firq)); 208 return NULL; 209 } 210 sc->sc_irq[irq] = firq; 211 } else { 212 if (firq->intr_arg == NULL && arg != NULL) { 213 device_printf(dev, "cannot share irq with NULL arg\n"); 214 return NULL; 215 } 216 if (firq->intr_ipl != ipl) { 217 device_printf(dev, "cannot share irq with different " 218 "ipl\n"); 219 return NULL; 220 } 221 if (firq->intr_level != level) { 222 device_printf(dev, "cannot share edge and level " 223 "interrupts\n"); 224 return NULL; 225 } 226 if (firq->intr_mpsafe != mpsafe) { 227 device_printf(dev, "cannot share between " 228 "mpsafe/non-mpsafe\n"); 229 return NULL; 230 } 231 } 232 233 firq->intr_refcnt++; 234 235 firqh = kmem_alloc(sizeof(*firqh), KM_SLEEP); 236 firqh->ih_mpsafe = (flags & FDT_INTR_MPSAFE) != 0; 237 firqh->ih_irq = firq; 238 firqh->ih_fn = func; 239 firqh->ih_arg = arg; 240 TAILQ_INSERT_TAIL(&firq->intr_handlers, firqh, ih_next); 241 242 return firq->intr_ih; 243 } 244 245 static void 246 gic_fdt_disestablish(device_t dev, void *ih) 247 { 248 struct gic_fdt_softc * const sc = device_private(dev); 249 struct gic_fdt_irqhandler *firqh; 250 struct gic_fdt_irq *firq; 251 u_int n; 252 253 for (n = 0; n < GIC_MAXIRQ; n++) { 254 firq = sc->sc_irq[n]; 255 if (firq->intr_ih != ih) 256 continue; 257 258 KASSERT(firq->intr_refcnt > 0); 259 260 if (firq->intr_refcnt > 1) 261 panic("%s: cannot disestablish shared irq", __func__); 262 263 firqh = TAILQ_FIRST(&firq->intr_handlers); 264 kmem_free(firqh, sizeof(*firqh)); 265 intr_disestablish(firq->intr_ih); 266 kmem_free(firq, sizeof(*firq)); 267 sc->sc_irq[n] = NULL; 268 return; 269 } 270 271 panic("%s: interrupt not established", __func__); 272 } 273 274 static int 275 gic_fdt_intr(void *priv) 276 { 277 struct gic_fdt_irq *firq = priv; 278 struct gic_fdt_irqhandler *firqh; 279 int handled = 0; 280 281 TAILQ_FOREACH(firqh, &firq->intr_handlers, ih_next) 282 handled += firqh->ih_fn(firqh->ih_arg); 283 284 return handled; 285 } 286 287 static bool 288 gic_fdt_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 289 { 290 /* 1st cell is the interrupt type; 0 is SPI, 1 is PPI */ 291 /* 2nd cell is the interrupt number */ 292 /* 3rd cell is flags */ 293 294 if (!specifier) 295 return false; 296 const u_int type = be32toh(specifier[0]); 297 const u_int intr = be32toh(specifier[1]); 298 const u_int irq = type == 0 ? IRQ_SPI(intr) : IRQ_PPI(intr); 299 300 snprintf(buf, buflen, "GIC irq %d", irq); 301 302 return true; 303 } 304
Indexes created Thu Oct 02 07:10:07 GMT 2025