gic_fdt.c revision 1.5
1 /* $NetBSD: gic_fdt.c,v 1.5 2017/06/28 23:49:29 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: gic_fdt.c,v 1.5 2017/06/28 23:49:29 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/lwp.h> 39 #include <sys/kmem.h> 40 41 #include <arm/cortex/gic_intr.h> 42 #include <arm/cortex/mpcore_var.h> 43 44 #include <dev/fdt/fdtvar.h> 45 46 #define GIC_MAXIRQ 1020 47 48 static int gic_fdt_match(device_t, cfdata_t, void *); 49 static void gic_fdt_attach(device_t, device_t, void *); 50 51 static int gic_fdt_intr(void *); 52 53 static void * gic_fdt_establish(device_t, u_int *, int, int, 54 int (*)(void *), void *); 55 static void gic_fdt_disestablish(device_t, void *); 56 static bool gic_fdt_intrstr(device_t, u_int *, char *, size_t); 57 58 struct fdtbus_interrupt_controller_func gic_fdt_funcs = { 59 .establish = gic_fdt_establish, 60 .disestablish = gic_fdt_disestablish, 61 .intrstr = gic_fdt_intrstr 62 }; 63 64 struct gic_fdt_softc; 65 struct gic_fdt_irq; 66 67 struct gic_fdt_irqhandler { 68 struct gic_fdt_irq *ih_irq; 69 int (*ih_fn)(void *); 70 void *ih_arg; 71 bool ih_mpsafe; 72 TAILQ_ENTRY(gic_fdt_irqhandler) ih_next; 73 }; 74 75 struct gic_fdt_irq { 76 struct gic_fdt_softc *intr_sc; 77 void *intr_ih; 78 int intr_refcnt; 79 int intr_ipl; 80 TAILQ_HEAD(, gic_fdt_irqhandler) intr_handlers; 81 }; 82 83 struct gic_fdt_softc { 84 device_t sc_dev; 85 int sc_phandle; 86 87 struct gic_fdt_irq *sc_irq[GIC_MAXIRQ]; 88 }; 89 90 CFATTACH_DECL_NEW(gic_fdt, sizeof(struct gic_fdt_softc), 91 gic_fdt_match, gic_fdt_attach, NULL, NULL); 92 93 static int 94 gic_fdt_match(device_t parent, cfdata_t cf, void *aux) 95 { 96 const char * const compatible[] = { 97 "arm,gic-400", 98 "arm,cortex-a15-gic", 99 "arm,cortex-a9-gic", 100 "arm,cortex-a7-gic", 101 NULL 102 }; 103 struct fdt_attach_args * const faa = aux; 104 105 return of_compatible(faa->faa_phandle, compatible) >= 0; 106 } 107 108 static void 109 gic_fdt_attach(device_t parent, device_t self, void *aux) 110 { 111 struct gic_fdt_softc * const sc = device_private(self); 112 struct fdt_attach_args * const faa = aux; 113 bus_addr_t addr_d, addr_c; 114 bus_size_t size_d, size_c; 115 bus_space_handle_t bsh; 116 int error; 117 118 sc->sc_dev = self; 119 sc->sc_phandle = faa->faa_phandle; 120 121 error = fdtbus_register_interrupt_controller(self, faa->faa_phandle, 122 &gic_fdt_funcs); 123 if (error) { 124 aprint_error(": couldn't register with fdtbus: %d\n", error); 125 return; 126 } 127 128 aprint_naive("\n"); 129 aprint_normal(": GIC\n"); 130 131 if (fdtbus_get_reg(sc->sc_phandle, 0, &addr_d, &size_d) != 0) { 132 aprint_error(": couldn't get distributor address\n"); 133 return; 134 } 135 if (fdtbus_get_reg(sc->sc_phandle, 1, &addr_c, &size_c) != 0) { 136 aprint_error(": couldn't get cpu interface address\n"); 137 return; 138 } 139 140 const bus_addr_t addr = addr_d; 141 const bus_size_t size = (addr_c + size_c) - addr_d; 142 143 error = bus_space_map(faa->faa_bst, addr, size, 0, &bsh); 144 if (error) { 145 aprint_error(": couldn't map registers: %d\n", error); 146 return; 147 } 148 149 struct mpcore_attach_args mpcaa = { 150 .mpcaa_name = "armgic", 151 .mpcaa_memt = faa->faa_bst, 152 .mpcaa_memh = bsh, 153 .mpcaa_off1 = 0, 154 .mpcaa_off2 = addr_c - addr_d 155 }; 156 157 config_found(self, &mpcaa, NULL); 158 159 arm_fdt_irq_set_handler(armgic_irq_handler); 160 } 161 162 static void * 163 gic_fdt_establish(device_t dev, u_int *specifier, int ipl, int flags, 164 int (*func)(void *), void *arg) 165 { 166 struct gic_fdt_softc * const sc = device_private(dev); 167 struct gic_fdt_irq *firq; 168 struct gic_fdt_irqhandler *firqh; 169 170 /* 1st cell is the interrupt type; 0 is SPI, 1 is PPI */ 171 /* 2nd cell is the interrupt number */ 172 /* 3rd cell is flags */ 173 174 const u_int type = be32toh(specifier[0]); 175 const u_int intr = be32toh(specifier[1]); 176 const u_int irq = type == 0 ? IRQ_SPI(intr) : IRQ_PPI(intr); 177 const u_int trig = be32toh(specifier[2]) & 0xf; 178 const u_int level = (trig & 0x3) ? IST_EDGE : IST_LEVEL; 179 180 firq = sc->sc_irq[irq]; 181 if (firq == NULL) { 182 firq = kmem_alloc(sizeof(*firq), KM_SLEEP); 183 firq->intr_sc = sc; 184 firq->intr_refcnt = 0; 185 firq->intr_ipl = ipl; 186 TAILQ_INIT(&firq->intr_handlers); 187 firq->intr_ih = intr_establish(irq, ipl, level | IST_MPSAFE, 188 gic_fdt_intr, firq); 189 if (firq->intr_ih == NULL) { 190 kmem_free(firq, sizeof(*firq)); 191 return NULL; 192 } 193 sc->sc_irq[irq] = firq; 194 } 195 196 if (firq->intr_ipl != ipl) { 197 device_printf(dev, "cannot share irq with different ipl\n"); 198 return NULL; 199 } 200 201 firq->intr_refcnt++; 202 203 firqh = kmem_alloc(sizeof(*firqh), KM_SLEEP); 204 firqh->ih_mpsafe = (flags & FDT_INTR_MPSAFE) != 0; 205 firqh->ih_irq = firq; 206 firqh->ih_fn = func; 207 firqh->ih_arg = arg; 208 TAILQ_INSERT_TAIL(&firq->intr_handlers, firqh, ih_next); 209 210 return firqh; 211 } 212 213 static void 214 gic_fdt_disestablish(device_t dev, void *ih) 215 { 216 struct gic_fdt_irqhandler *firqh = ih; 217 struct gic_fdt_irq *firq = firqh->ih_irq; 218 219 KASSERT(firq->intr_refcnt > 0); 220 221 TAILQ_REMOVE(&firq->intr_handlers, firqh, ih_next); 222 kmem_free(firqh, sizeof(*firqh)); 223 224 firq->intr_refcnt--; 225 if (firq->intr_refcnt == 0) { 226 intr_disestablish(firq->intr_ih); 227 kmem_free(firq, sizeof(*firq)); 228 } 229 } 230 231 static int 232 gic_fdt_intr(void *priv) 233 { 234 struct gic_fdt_irq *firq = priv; 235 struct gic_fdt_irqhandler *firqh; 236 int handled = 0; 237 238 TAILQ_FOREACH(firqh, &firq->intr_handlers, ih_next) { 239 if (!firqh->ih_mpsafe) 240 KERNEL_LOCK(1, curlwp); 241 handled += firqh->ih_fn(firqh->ih_arg); 242 if (!firqh->ih_mpsafe) 243 KERNEL_UNLOCK_ONE(curlwp); 244 } 245 246 return handled; 247 } 248 249 static bool 250 gic_fdt_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 251 { 252 /* 1st cell is the interrupt type; 0 is SPI, 1 is PPI */ 253 /* 2nd cell is the interrupt number */ 254 /* 3rd cell is flags */ 255 256 if (!specifier) 257 return false; 258 const u_int type = be32toh(specifier[0]); 259 const u_int intr = be32toh(specifier[1]); 260 const u_int irq = type == 0 ? IRQ_SPI(intr) : IRQ_PPI(intr); 261 262 snprintf(buf, buflen, "GIC irq %d", irq); 263 264 return true; 265 } 266
Indexes created Thu Oct 02 14:10:14 GMT 2025