gic_fdt.c revision 1.7
1 /* $NetBSD: gic_fdt.c,v 1.7 2017/07/02 21:59:14 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: gic_fdt.c,v 1.7 2017/07/02 21:59:14 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/lwp.h> 39 #include <sys/kmem.h> 40 41 #include <arm/cortex/gic_intr.h> 42 #include <arm/cortex/mpcore_var.h> 43 44 #include <dev/fdt/fdtvar.h> 45 46 #define GIC_MAXIRQ 1020 47 48 static int gic_fdt_match(device_t, cfdata_t, void *); 49 static void gic_fdt_attach(device_t, device_t, void *); 50 51 static int gic_fdt_intr(void *); 52 53 static void * gic_fdt_establish(device_t, u_int *, int, int, 54 int (*)(void *), void *); 55 static void gic_fdt_disestablish(device_t, void *); 56 static bool gic_fdt_intrstr(device_t, u_int *, char *, size_t); 57 58 struct fdtbus_interrupt_controller_func gic_fdt_funcs = { 59 .establish = gic_fdt_establish, 60 .disestablish = gic_fdt_disestablish, 61 .intrstr = gic_fdt_intrstr 62 }; 63 64 struct gic_fdt_softc; 65 struct gic_fdt_irq; 66 67 struct gic_fdt_irqhandler { 68 struct gic_fdt_irq *ih_irq; 69 int (*ih_fn)(void *); 70 void *ih_arg; 71 bool ih_mpsafe; 72 TAILQ_ENTRY(gic_fdt_irqhandler) ih_next; 73 }; 74 75 struct gic_fdt_irq { 76 struct gic_fdt_softc *intr_sc; 77 void *intr_ih; 78 int intr_refcnt; 79 int intr_ipl; 80 int intr_level; 81 int intr_mpsafe; 82 TAILQ_HEAD(, gic_fdt_irqhandler) intr_handlers; 83 }; 84 85 struct gic_fdt_softc { 86 device_t sc_dev; 87 int sc_phandle; 88 89 struct gic_fdt_irq *sc_irq[GIC_MAXIRQ]; 90 }; 91 92 CFATTACH_DECL_NEW(gic_fdt, sizeof(struct gic_fdt_softc), 93 gic_fdt_match, gic_fdt_attach, NULL, NULL); 94 95 static int 96 gic_fdt_match(device_t parent, cfdata_t cf, void *aux) 97 { 98 const char * const compatible[] = { 99 "arm,gic-400", 100 "arm,cortex-a15-gic", 101 "arm,cortex-a9-gic", 102 "arm,cortex-a7-gic", 103 NULL 104 }; 105 struct fdt_attach_args * const faa = aux; 106 107 return of_compatible(faa->faa_phandle, compatible) >= 0; 108 } 109 110 static void 111 gic_fdt_attach(device_t parent, device_t self, void *aux) 112 { 113 struct gic_fdt_softc * const sc = device_private(self); 114 struct fdt_attach_args * const faa = aux; 115 bus_addr_t addr_d, addr_c; 116 bus_size_t size_d, size_c; 117 bus_space_handle_t bsh; 118 int error; 119 120 sc->sc_dev = self; 121 sc->sc_phandle = faa->faa_phandle; 122 123 error = fdtbus_register_interrupt_controller(self, faa->faa_phandle, 124 &gic_fdt_funcs); 125 if (error) { 126 aprint_error(": couldn't register with fdtbus: %d\n", error); 127 return; 128 } 129 130 aprint_naive("\n"); 131 aprint_normal(": GIC\n"); 132 133 if (fdtbus_get_reg(sc->sc_phandle, 0, &addr_d, &size_d) != 0) { 134 aprint_error(": couldn't get distributor address\n"); 135 return; 136 } 137 if (fdtbus_get_reg(sc->sc_phandle, 1, &addr_c, &size_c) != 0) { 138 aprint_error(": couldn't get cpu interface address\n"); 139 return; 140 } 141 142 const bus_addr_t addr = addr_d; 143 const bus_size_t size = (addr_c + size_c) - addr_d; 144 145 error = bus_space_map(faa->faa_bst, addr, size, 0, &bsh); 146 if (error) { 147 aprint_error(": couldn't map registers: %d\n", error); 148 return; 149 } 150 151 struct mpcore_attach_args mpcaa = { 152 .mpcaa_name = "armgic", 153 .mpcaa_memt = faa->faa_bst, 154 .mpcaa_memh = bsh, 155 .mpcaa_off1 = 0, 156 .mpcaa_off2 = addr_c - addr_d 157 }; 158 159 config_found(self, &mpcaa, NULL); 160 161 arm_fdt_irq_set_handler(armgic_irq_handler); 162 } 163 164 static void * 165 gic_fdt_establish(device_t dev, u_int *specifier, int ipl, int flags, 166 int (*func)(void *), void *arg) 167 { 168 struct gic_fdt_softc * const sc = device_private(dev); 169 struct gic_fdt_irq *firq; 170 struct gic_fdt_irqhandler *firqh; 171 172 /* 1st cell is the interrupt type; 0 is SPI, 1 is PPI */ 173 /* 2nd cell is the interrupt number */ 174 /* 3rd cell is flags */ 175 176 const u_int type = be32toh(specifier[0]); 177 const u_int intr = be32toh(specifier[1]); 178 const u_int irq = type == 0 ? IRQ_SPI(intr) : IRQ_PPI(intr); 179 const u_int trig = be32toh(specifier[2]) & 0xf; 180 const u_int level = (trig & 0x3) ? IST_EDGE : IST_LEVEL; 181 182 const u_int mpsafe = (flags & FDT_INTR_MPSAFE) ? IST_MPSAFE : 0; 183 184 firq = sc->sc_irq[irq]; 185 if (firq == NULL) { 186 firq = kmem_alloc(sizeof(*firq), KM_SLEEP); 187 firq->intr_sc = sc; 188 firq->intr_refcnt = 0; 189 firq->intr_ipl = ipl; 190 firq->intr_level = level; 191 firq->intr_mpsafe = mpsafe; 192 TAILQ_INIT(&firq->intr_handlers); 193 firq->intr_ih = intr_establish(irq, ipl, level | mpsafe, 194 gic_fdt_intr, firq); 195 if (firq->intr_ih == NULL) { 196 kmem_free(firq, sizeof(*firq)); 197 return NULL; 198 } 199 sc->sc_irq[irq] = firq; 200 } 201 202 if (firq->intr_ipl != ipl) { 203 device_printf(dev, "cannot share irq with different ipl\n"); 204 return NULL; 205 } 206 if (firq->intr_level != level) { 207 device_printf(dev, "cannot share edge and level interrupts\n"); 208 return NULL; 209 } 210 if (firq->intr_mpsafe != mpsafe) { 211 device_printf(dev, "cannot share between mpsafe/non-mpsafe\n"); 212 return NULL; 213 } 214 215 firq->intr_refcnt++; 216 217 firqh = kmem_alloc(sizeof(*firqh), KM_SLEEP); 218 firqh->ih_mpsafe = (flags & FDT_INTR_MPSAFE) != 0; 219 firqh->ih_irq = firq; 220 firqh->ih_fn = func; 221 firqh->ih_arg = arg; 222 TAILQ_INSERT_TAIL(&firq->intr_handlers, firqh, ih_next); 223 224 return firqh; 225 } 226 227 static void 228 gic_fdt_disestablish(device_t dev, void *ih) 229 { 230 struct gic_fdt_irqhandler *firqh = ih; 231 struct gic_fdt_irq *firq = firqh->ih_irq; 232 233 KASSERT(firq->intr_refcnt > 0); 234 235 TAILQ_REMOVE(&firq->intr_handlers, firqh, ih_next); 236 kmem_free(firqh, sizeof(*firqh)); 237 238 firq->intr_refcnt--; 239 if (firq->intr_refcnt == 0) { 240 intr_disestablish(firq->intr_ih); 241 kmem_free(firq, sizeof(*firq)); 242 } 243 } 244 245 static int 246 gic_fdt_intr(void *priv) 247 { 248 struct gic_fdt_irq *firq = priv; 249 struct gic_fdt_irqhandler *firqh; 250 int handled = 0; 251 252 TAILQ_FOREACH(firqh, &firq->intr_handlers, ih_next) 253 handled += firqh->ih_fn(firqh->ih_arg); 254 255 return handled; 256 } 257 258 static bool 259 gic_fdt_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 260 { 261 /* 1st cell is the interrupt type; 0 is SPI, 1 is PPI */ 262 /* 2nd cell is the interrupt number */ 263 /* 3rd cell is flags */ 264 265 if (!specifier) 266 return false; 267 const u_int type = be32toh(specifier[0]); 268 const u_int intr = be32toh(specifier[1]); 269 const u_int irq = type == 0 ? IRQ_SPI(intr) : IRQ_PPI(intr); 270 271 snprintf(buf, buflen, "GIC irq %d", irq); 272 273 return true; 274 } 275
Indexes created Thu Oct 02 14:10:14 GMT 2025